SAML21 USB: Add host side register defintiions
This commit is contained in:
Gregory Nutt
parent
d1582aac2e
commit
046e849459
@ -106,6 +106,49 @@
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/* USB Host Register Offsets */
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#define SAM_USBHOST_CTRLB_OFFSET 0x0008 /* Control B Register */
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#define SAM_USBHOST_HSOFC_OFFSET 0x000a /* Host Start-of-Frame Control Register */
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#define SAM_USBHOST_STATUS_OFFSET 0x000c /* Status Register */
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#define SAM_USBHOST_FNUM_OFFSET 0x0010 /* Host Frame Number Register */
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#define SAM_USBHOST_FLENHIGH_OFFSET 0x0012 /* Host Frame Length Register */
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#define SAM_USBHOST_INTENCLR_OFFSET 0x0014 /* Host Interrupt Enable Clear Register */
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#define SAM_USBHOST_INTENSET_OFFSET 0x0018 /* Host Interrupt Enable Set Register */
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#define SAM_USBHOST_INTFLAG_OFFSET 0x001c /* Host Interrupt Flag Status and Clear Register */
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#define SAM_USBHOST_PINTSMRY_OFFSET 0x0020 /* Pipe Interrupt Summary Register */
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/* Pipe Register n Register */
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#define SAM_USBHOST_PIPE_OFFSET(n) (0x0100 + ((n) << 4))
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/* The following are then relative to the pipe register n offset */
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#define SAM_USBHOST_PCFG_OFFSET 0x0000 /* Host Pipe Configuration Register */
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#define SAM_USBHOST_BINTERVAL_OFFSET 0x0003 /* Interval for Bulk-OUT/Ping Transaction Register */
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#define SAM_USBHOST_PSTATUSCLR_OFFSET 0x0004 /* Pipe Status Clear Register */
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#define SAM_USBHOST_PSTATUSET_OFFSET 0x0005 /* Pipe Status Set Register */
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#define SAM_USBHOST_PSTATUS_OFFSET 0x0006 /* Pipe Status Register */
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#define SAM_USBHOST_PINTFLAG_OFFSET 0x0007 /* Host Pipe Interrupt Flag Register */
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#define SAM_USBHOST_PINTENCLR_OFFSET 0x0008 /* Host Pipe Interrupt Clear Register */
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#define SAM_USBHOST_PINTENSET_OFFSET 0x0009 /* Host Pipe Interrupt Set Register */
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#define SAM_USBHOST_PnCFG_OFFSET(n) (SAM_USBHOST_PIPE_OFFSET(n)+SAM_USBHOST_PCFG_OFFSET)
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#define SAM_USBHOST_BINTERVALn_OFFSET(n) (SAM_USBHOST_PIPE_OFFSET(n)+SAM_USBHOST_BINTERVAL_OFFSET)
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#define SAM_USBHOST_PnSTATUSCLR_OFFSET(n) (SAM_USBHOST_PIPE_OFFSET(n)+SAM_USBHOST_PSTATUSCLR_OFFSET)
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#define SAM_USBHOST_PnSTATUSET_OFFSET(n) (SAM_USBHOST_PIPE_OFFSET(n)+SAM_USBHOST_PSTATUSET_OFFSET)
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#define SAM_USBHOST_PnSTATUS_OFFSET(n) (SAM_USBHOST_PIPE_OFFSET(n)+SAM_USBHOST_PSTATUS_OFFSET)
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#define SAM_USBHOST_PnINTFLAG_OFFSET(n) (SAM_USBHOST_PIPE_OFFSET(n)+SAM_USBHOST_PINTFLAG_OFFSET)
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#define SAM_USBHOST_PnINTENCLR_OFFSET(n) (SAM_USBHOST_PIPE_OFFSET(n)+SAM_USBHOST_PINTENCLR_OFFSET)
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#define SAM_USBHOST_PnINTENSET_OFFSET(n) (SAM_USBHOST_PIPE_OFFSET(n)+SAM_USBHOST_PINTENSET_OFFSET)
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/* Host Pipe Descriptor */
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#define SAM_USBHOST_ADDR_OFFSET 0x0000 /* Data buffer address (Both banks) */
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#define SAM_USBHOST_PKTSIZE_OFFSET 0x0004 /* Packet size (Both banks) */
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#define SAM_USBHOST_EXTREG_OFFSET 0x0008 /* Extended register (Bank 0 only) */
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#define SAM_USBHOST_STATUSBK_OFFSET 0x000a /* host status bank (Both banks) */
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#define SAM_USBHOST_CTRLPIPE_OFFSET 0x000c /* Host control pipe (Bank 0 only) */
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#define SAM_USBHOST_STATUSPIPE_OFFSET 0x000e /* Host status pipe (Both banks) */
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/* USB register addresses ******************************************************************/
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/* Common USB Device/Host Register Addresses */
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@ -132,7 +175,7 @@
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#define SAM_USBDEV_EP_BASE(n) (SAM_USB_BASE+SAM_USBDEV_EP_OFFSET(n))
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/* The following are then relative to the endpoint register n offset */
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/* Endpoint n Register Addresses */
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#define SAM_USBDEV_EPCFG(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPCFG_OFFSET)
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#define SAM_USBDEV_EPSTATUSCLR(n) (SAM_USBDEV_EP_BASE(n)+SAM_USBDEV_EPSTATUSCLR_OFFSET)
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@ -144,6 +187,31 @@
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/* USB Host Register Addresses */
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#define SAM_USBHOST_CTRLB (SAM_USB_BASE+SAM_USBHOST_CTRLB_OFFSET)
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#define SAM_USBHOST_HSOFC (SAM_USB_BASE+SAM_USBHOST_HSOFC_OFFSET)
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#define SAM_USBHOST_STATUS (SAM_USB_BASE+SAM_USBHOST_STATUS_OFFSET)
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#define SAM_USBHOST_FNUM (SAM_USB_BASE+SAM_USBHOST_FNUM_OFFSET)
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#define SAM_USBHOST_FLENHIGH (SAM_USB_BASE+SAM_USBHOST_FLENHIGH_OFFSET)
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#define SAM_USBHOST_INTENCLR (SAM_USB_BASE+SAM_USBHOST_INTENCLR_OFFSET)
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#define SAM_USBHOST_INTENSET (SAM_USB_BASE+SAM_USBHOST_INTENSET_OFFSET)
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#define SAM_USBHOST_INTFLAG (SAM_USB_BASE+SAM_USBHOST_INTFLAG_OFFSET)
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#define SAM_USBHOST_PINTSMRY (SAM_USB_BASE+SAM_USBHOST_PINTSMRY_OFFSET)
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/* Pipe Register n Base Address */
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#define SAM_USBHOST_PIPE_BASE(n) (SAM_USB_BASE+SAM_USBHOST_PIPE_OFFSET(n))
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/* Pipe n Register Addresses */
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#define SAM_USBHOST_PCFG(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PCFG_OFFSET)
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#define SAM_USBHOST_BINTERVAL(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_BINTERVAL_OFFSET)
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#define SAM_USBHOST_PSTATUSCLR(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PSTATUSCLR_OFFSET)
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#define SAM_USBHOST_PSTATUSET(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PSTATUSET_OFFSET)
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#define SAM_USBHOST_PSTATUS(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PSTATUS_OFFSET)
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#define SAM_USBHOST_PINTFLAG(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PINTFLAG_OFFSET)
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#define SAM_USBHOST_PINTENCLR(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PINTENCLR_OFFSET)
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#define SAM_USBHOST_PINTENSET(n) (SAM_USBHOST_PIPE_BASE(n)+SAM_USBHOST_PINTENSET_OFFSET)
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/* USB register bit definitions ************************************************************/
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/* Common USB Device/Host Register Offsets */
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@ -309,9 +377,9 @@
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/* Packet Size (Both banks) */
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#define USBDEV_PKTSIZE_BYTECOUNT_SHIFT (0) /* Bits 0-5: */
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#define USBDEV_PKTSIZE_BYTECOUNT_MASK (0x3f << USBDEV_PKTSIZE_BYTECOUNT_SHIFT)
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# define USBDEV_PKTSIZE_BYTECOUNT(n) ((uint32_t)(n) << USBDEV_PKTSIZE_BYTECOUNT_SHIFT)
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#define USBDEV_PKTSIZE_BCNT_SHIFT (0) /* Bits 0-5: Byte count */
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#define USBDEV_PKTSIZE_BCNT_MASK (0x3f << USBDEV_PKTSIZE_BCNT_SHIFT)
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# define USBDEV_PKTSIZE_BCNT(n) ((uint32_t)(n) << USBDEV_PKTSIZE_BCNT_SHIFT)
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#define USBDEV_PKTSIZE_MPKTSIZE_SHIFT (14) /* Bits 14-27: Multi-packet size */
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#define USBDEV_PKTSIZE_MPKTSIZE_MASK (0x3fff << USBDEV_PKTSIZE_MPKTSIZE_SHIFT)
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# define USBDEV_PKTSIZE_MPKTSIZE(n) ((uint32_t)(n) << USBDEV_PKTSIZE_MPKTSIZE_SHIFT)
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@ -343,11 +411,170 @@
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/* USB Host Register Offsets */
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/* Control B Register */
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#define USBHOST_CTRLB_RESUME (1 << 1) /* Bit 1: Send USB resume */
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#define USBHOST_CTRLB_SPDCONF_SHIFT (2) /* Bits 2-3: Host speed configuration */
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#define USBHOST_CTRLB_SPDCONF_MASK (3 << USBHOST_CTRLB_SPDCONF_SHIFT)
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# define USBHOST_CTRLB_SPDCONF_LF (0 << USBHOST_CTRLB_SPDCONF_SHIFT) /* Low and full capable */
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#define USBHOST_CTRLB_TSTJ (1 << 5) /* Bit 5: TSTJ */
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#define USBHOST_CTRLB_TSTK (1 << 6) /* Bit 6: TSTK */
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#define USBHOST_CTRLB_SOFE (1 << 8) /* Bit 8: Start of frame generation enable */
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#define USBHOST_CTRLB_BUSRESET (1 << 9) /* Bit 9: Send USB reset */
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#define USBHOST_CTRLB_VBUSOK (1 << 10) /* Bit 10: VBUS is OK */
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#define USBHOST_CTRLB_L1RESUME (1 << 11) /* Bit 11: Send USB L1 resume */
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/* Host Start-of-Frame Control Register */
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#define USBHOST_HSOFC_FLENC_SHIFT (0) /* Bits 0-3: Frame length control */
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#define USBHOST_HSOFC_FLENC_MASK (15 << USBHOST_HSOFC_FLENC_SHIFT)
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# define USBHOST_HSOFC_FLENC(n) ((uint8_t)(n) << USBHOST_HSOFC_FLENC_SHIFT)
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#define USBHOST_HSOFC_FLENCE (1 << 7) /* Bit 7: Frame length control enable */
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/* Status Register */
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#define USBHOST_STATUS_SPEED_SHIFT (0) /* Bits 0-1: Speed status */
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#define USBHOST_STATUS_SPEED_MASK (3 << USBHOST_STATUS_SPEED_SHIFT)
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# define USBHOST_STATUS_SPEED_LOW (0 << USBHOST_STATUS_SPEED_SHIFT) /* Full speed mode */
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# define USBHOST_STATUS_SPEED_FULL (2 << USBHOST_STATUS_SPEED_SHIFT) /* Low speed mode */
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#define USBHOST_STATUS_LNSTATE_SHIFT (6) /* Bits 6-7: USB line status */
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#define USBHOST_STATUS_LNSTATE_MASK (3 << USBHOST_STATUS_LNSTATE_SHIFT)
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# define USBHOST_STATUS_LNSTATE_SE0 (0 << USBHOST_STATUS_LNSTATE_SHIFT) /* SE0/RESET */
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# define USBHOST_STATUS_LNSTATE_FJLK (1 << USBHOST_STATUS_LNSTATE_SHIFT) /* FS-J or LS-K */
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# define USBHOST_STATUS_LNSTATE_FKLJ (2 << USBHOST_STATUS_LNSTATE_SHIFT) /* FS-K or :S-L */
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/* Host Frame Number Register */
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#define USBHOST_FNUM_SHIFT (3) /* Bits 3-13: Frame number */
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#define USBHOST_FNUM_MASK (0x07ff << USBHOST_FNUM_SHIFT)
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/* Host Frame Length Register (8-bit data) */
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/* Common definitions for Host Interrupt Enable Clear Register, Host Interrupt Enable
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* Set Register, and Host Interrupt Flag Status and Clear Register
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*/
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#define USBHOST_INT_HSOF (1 << 2) /* Bit 2: Host start of frame interrupt */
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#define USBHOST_INT_RST (1 << 3) /* Bit 3: Bus reset interrupt */
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#define USBHOST_INT_WAKEUP (1 << 4) /* Bit 4: Wake up interrupt */
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#define USBHOST_INT_DNRSM (1 << 5) /* Bit 5: Downstream resume interrupt */
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#define USBHOST_INT_UPRSM (1 << 6) /* Bit 6: Upstream resume from device interrupt */
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#define USBHOST_INT_RAMACER (1 << 7) /* Bit 7: FAM access interrupt */
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#define USBHOST_INT_DCONN (1 << 8) /* Bit 8: Device connection interrupt */
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#define USBHOST_INT_DDISC (1 << 9) /* Bit 9: Device disconnection interrupt */
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/* Pipe Interrupt Summary Register */
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#define USBHOST_PINTSMRY_PIPEINT(n) (1 << (n))
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/* Host Pipe Configuration Register */
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#define USBHOST_PCFG_PTOKEN_SHIFT (0) /* Bits 0-1: Pipe token */
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#define USBHOST_PCFG_PTOKEN_MASK (3 << USBHOST_PCFG_PTOKEN_SHIFT)
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# define USBHOST_PCFG_PTOKEN_SETUP (0 << USBHOST_PCFG_PTOKEN_SHIFT)
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# define USBHOST_PCFG_PTOKEN_IN (1 << USBHOST_PCFG_PTOKEN_SHIFT)
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# define USBHOST_PCFG_PTOKEN_OUT (2 << USBHOST_PCFG_PTOKEN_SHIFT)
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#define USBHOST_PCFG_BK (1 << 2) /* Bit 2: Pipe bank */
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#define USBHOST_PCFG_BK_SINGLE (0) /* 0=Single bank endpoint */
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#define USBHOST_PCFG_BK_DUAL (1 << 2) /* 1=Dual bank endpoint */
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#define USBHOST_PCFG_PTYPE_SHIFT (3) /* Bits 3-5: Type of pipe */
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#define USBHOST_PCFG_PTYPE_MASK (7 << USBHOST_PCFG_PTYPE_SHIFT)
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# define USBHOST_PCFG_PTYPE_DISABLED (0 << USBHOST_PCFG_PTYPE_SHIFT) /* Disabled */
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# define USBHOST_PCFG_PTYPE_CTRL (1 << USBHOST_PCFG_PTYPE_SHIFT) /* Control pipe */
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# define USBHOST_PCFG_PTYPE_ISOC (2 << USBHOST_PCFG_PTYPE_SHIFT) /* Isochronous pipe */
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# define USBHOST_PCFG_PTYPE_BULK (3 << USBHOST_PCFG_PTYPE_SHIFT) /* Bulk pipe */
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# define USBHOST_PCFG_PTYPE_INT (4 << USBHOST_PCFG_PTYPE_SHIFT) /* Interrupt pipe */
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# define USBHOST_PCFG_PTYPE_EXTENDED (5 << USBHOST_PCFG_PTYPE_SHIFT) /* Extended pipe */
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/* Interval for Bulk-OUT/Ping Transaction Register (8-bit data) */
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/* Common definitions for Pipe Status Clear Register, Pipe Status Set Register, and
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* Pipe Status Register
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*/
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#define USBHOST_PSTATUS_DTGL (1 << 0) /* Bit 0: Data toggle sequence */
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#define USBHOST_PSTATUS_CURBK (1 << 2) /* Bit 2: Current bank */
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#define USBHOST_PSTATUS_PFREEZE (1 << 4) /* Bit 4: Pipe freeze */
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#define USBHOST_PSTATUS_BK0RDY (1 << 6) /* Bit 6: Bank 0 ready */
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#define USBHOST_PSTATUS_BK1RDY (1 << 7) /* Bit 7: Bank 1 ready */
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/* Common definitions for Host Pipe Interrupt Flag Register, Host Pipe Interrupt Clear
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* Register, and Host Pipe Interrupt Set Register
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*/
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#define USBHOST_PINTFLAG_TRCPT0 (1 << 0) /* Bit 0: Transfer complete 0 interrupt */
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#define USBHOST_PINTFLAG_TRCPT1 (1 << 1) /* Bit 1: Transfer complete 1 interrupt */
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#define USBHOST_PINTFLAG_TRFAIL (1 << 2) /* Bit 2: Transfer fail interrupt */
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#define USBHOST_PINTFLAG_PERR (1 << 3) /* Bit 3: Pipe error interrupt */
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#define USBHOST_PINTFLAG_TXSTP (1 << 4) /* Bit 4: Transmitted SETUP interrupt */
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#define USBHOST_PINTFLAG_STALL (1 << 5) /* Bit 5: STALL received interrupt */
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/* Host Pipe Descriptor */
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/* Data buffer address (Both banks, 32-bit address) */
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/* Packet size (Both banks) */
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#define USBHOST_PKTSIZE_BCNT_SHIFT (8) /* Bits 8-13: Byte count */
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#define USBHOST_PKTSIZE_BCNT_MASK (0x3f << USBHOST_PKTSIZE_BCNT_SHIFT)
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# define USBHOST_PKTSIZE_BCNT(n) ((uint32_t)(n) << USBHOST_PKTSIZE_BCNT_SHIFT)
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#define USBHOST_PKTSIZE_MPKTSIZE_SHIFT (14) /* Bits 14-27: Multi-packet IN/OUT size */
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#define USBHOST_PKTSIZE_MPKTSIZE_MASK (0x3fff << USBHOST_PKTSIZE_MPKTSIZE_SHIFT)
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# define USBHOST_PKTSIZE_MPKTSIZE(n) ((uint32_t)(n) << USBHOST_PKTSIZE_MPKTSIZE_SHIFT)
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#define USBHOST_PKTSIZE_SIZE_SHIFT (28) /* Bits 28-30: Pipe size */
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#define USBHOST_PKTSIZE_SIZE_MASK (7 << USBHOST_PKTSIZE_SIZE_SHIFT)
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# define USBHOST_PKTSIZE_SIZE_8B (0 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 8 bytes */
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# define USBHOST_PKTSIZE_SIZE_16B (1 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 16 bytes */
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# define USBHOST_PKTSIZE_SIZE_32B (2 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 32 bytes */
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# define USBHOST_PKTSIZE_SIZE_64B (3 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 64 bytes */
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# define USBHOST_PKTSIZE_SIZE_128B (4 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 128 bytes (isoc only) */
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# define USBHOST_PKTSIZE_SIZE_256B (5 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 256 bytes (isoc only) */
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# define USBHOST_PKTSIZE_SIZE_512B (6 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 512 bytes (isoc only) */
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# define USBHOST_PKTSIZE_SIZE_1023B (7 << USBHOST_PKTSIZE_SIZE_SHIFT) /* 1023 bytes (isoc only) */
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#define USBHOST_PKTSIZE_AUTOZLP (1 << 31) /* Bit 31: Automatic zero length packet */
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/* Extended register (Bank 0 only) */
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#define USBHOST_EXTREG_SUBPID_SHIFT (0) /* Bits 0-3: SUBPID */
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#define USBHOST_EXTREG_SUBPID_MASK (15 << USBHOST_EXTREG_SUBPID_SHIFT)
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# define USBHOST_EXTREG_SUBPID(n) ((uint16_t)(n) << USBHOST_EXTREG_SUBPID_SHIFT)
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#define USBHOST_EXTREG_VARIABLE_SHIFT (4) /* Bits 4-14: VARIABLE */
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#define USBHOST_EXTREG_VARIABLE_MASK (0x7ff << USBHOST_EXTREG_VARIABLE_SHIFT)
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# define USBHOST_EXTREG_VARIABLE(n) ((uint16_t)(n) << USBHOST_EXTREG_VARIABLE_SHIFT)
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/* host status bank (Both banks) */
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#define USBHOST_STATUSBK_CRCERR (1 << 0) /* Bit 0: CRC error */
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#define USBHOST_STATUSBK_ERRORFLOW (1 << 1) /* Bit 1: Error flow status */
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/* Host control pipe (Bank 0 only) */
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#define USBHOST_CTRLPIPE_PDADDR_SHIFT (0) /* Bits 0-6: Pipe device address */
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#define USBHOST_CTRLPIPE_PDADDR_MASK (0x7f << USBHOST_CTRLPIPE_PDADDR_SHIFT)
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# define USBHOST_CTRLPIPE_PDADDR(n) ((uint16_t)(n) << USBHOST_CTRLPIPE_PDADDR_SHIFT)
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#define USBHOST_CTRLPIPE_PEPNUM_SHIFT (8) /* Bits 8-11: Pipe endpoint number */
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#define USBHOST_CTRLPIPE_PEPNUM_MASK (15 << USBHOST_CTRLPIPE_PEPNUM_SHIFTxx)
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# define USBHOST_CTRLPIPE_PEPNUM(n) ((uint16_t)(n) << USBHOST_CTRLPIPE_PEPNUM_SHIFTxx)
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#define USBHOST_CTRLPIPE_PEPMAX_SHIFT (12) /* Bitx 12-15: Pipe error max number */
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#define USBHOST_CTRLPIPE_PEPMAX_MASK (15 << USBHOST_CTRLPIPE_PEPMAX_SHIFT)
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# define USBHOST_CTRLPIPE_PEPMAX(n) ((uint16_t)(n) << USBHOST_CTRLPIPE_PEPMAX_SHIFT)
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/* Host status pipe (Both banks) */
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#define USBHOST_STATUSPIPE_DTGLER (1 << 0) /* Bit 0: Data toggle error */
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#define USBHOST_STATUSPIPE_DAPIDER (1 << 1) /* Bit 1: Data PID error */
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#define USBHOST_STATUSPIPE_PIDER (1 << 2) /* Bit 2: PID error */
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#define USBHOST_STATUSPIPE_TOUTER (1 << 3) /* Bit 3: Timeout error */
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#define USBHOST_STATUSPIPE_CRC16ER (1 << 4) /* Bit 4: CRC16 error */
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#define USBHOST_STATUSPIPE_ERCNT_SHIFT (5) /* Bits 5-7: Pipe error counter */
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#define USBHOST_STATUSPIPE_ERCNT_MASK (7 << USBHOST_STATUSPIPE_ERCNT_SHIFT)
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# define USBHOST_STATUSPIPE_ERCNT(n) ((uint16_t)(n) << USBHOST_STATUSPIPE_ERCNT_SHIFT)
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/* Device Endpoint Descriptor */
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/* Device Endpoint Descriptor. See USBDEV_* bit definitions above. */
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struct usbdev_epdesc_s
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{
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@ -358,6 +585,19 @@ struct usbdev_epdesc_s
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uint8_t reserved[5]; /* 0x000b-0x000f: Both banks */
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};
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/* Host Pipe Descriptor. See USBHOST_* bit definitions above */
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struct usbhost_pipedesc_s
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{
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uint32_t addr; /* 0x0000-0x0003: Address of Data buffer (Both banks) */
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uint32_t pktsize; /* 0x0004-0x0007: Packet Size (Both banks) */
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uint16_t extreg; /* 0x0008-0x0009: Extended Register (Bank 0 only) */
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uint8_t stausbk; /* 0x000a-0x000a: Device Status Bank (Both banks) */
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uint8_t reserved; /* 0x000b-0x000b: Both banks */
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uint16_t ctrlpipe; /* 0x000c-0x000d: Host control pipe (Bank 0 only) */
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uint16_t statuspipe; /* 0x000e-0x000f: Host status pipe (Both banks) */
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};
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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