SAMA5: When booting from SDRAM, don't copy vectors to ISRAM. Instread just set the VBAR register to add address of the vectors in SDRAM
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Gregory Nutt
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c9fc03d52f
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048230fb94
@ -7122,3 +7122,10 @@
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* arch/arm/src/sama5/sam_irq.c: After we modify the AXI MATRIX, make
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sure to invalidate all caches and TLBs (probably un-necessary)
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(2014-4-2).
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* arch/arm/src/sama5/sam_irq.c: Set the VBAR register to zero. If
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were started by a bootloader (vs. a RESET), then the VBAR register
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may not be in its reset state (zero, 2014-4-3).
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* arch/arm/src/sama5/sam_boot.c, sam_irq.c, and chip/sama5d3x_memorymap.h:
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When booting from SDRAM, don't relocated vectors to ISRAM. Instead,
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just set the VBAR register to address of the vectors in SDRAM.
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@ -620,21 +620,7 @@
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# error CONFIG_BOOT_SDRAM_DATA not suupported in this configuration
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# endif
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# elif defined(CONFIG_SAMA5_BOOT_SDRAM) && defined(CONFIG_ARCH_LOWVECTORS)
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/* In this case, vectors must lie in ISRAM, followed by the page table,*/
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# define PGTABLE_BASE_PADDR (SAM_ISRAM0_PADDR + 0x00004000)
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# ifndef CONFIG_PAGING
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# define PGTABLE_BASE_VADDR (SAM_ISRAM0_VADDR + 0x00004000)
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# endif
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# define PGTABLE_IN_LOWSRAM 1
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# ifdef CONFIG_BOOT_SDRAM_DATA
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# error CONFIG_BOOT_SDRAM_DATA not suupported in this configuration
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# endif
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# else /* CONFIG_SAMA5_BOOT_SDRAM && CONFIG_ARCH_LOWVECTORS */
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# else /* CONFIG_SAMA5_BOOT_ISRAM && CONFIG_ARCH_LOWVECTORS */
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/* Otherwise, the vectors lie at another location (perhaps in NOR FLASH, perhaps
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* elsewhere in internal SRAM). The page table will then be positioned at
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@ -106,19 +106,6 @@
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# define NEED_SDRAM_REMAPPING 1
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#endif
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/* We need to copy vectors under two conditions:
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*
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* 1. If vectors lie in high memory because CONFIG_ARCH_LOWVECTORS=n, or
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* 2. If vectors lie in low memory and we are executing from SDRAM.
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*/
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#undef NEED_VECTOR_COPY
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#if !defined(CONFIG_ARCH_LOWVECTORS)
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# define NEED_VECTOR_COPY 1
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#elif defined(CONFIG_SAMA5_BOOT_SDRAM)
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# define NEED_VECTOR_COPY 1
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#endif
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -146,28 +133,26 @@ static const struct section_mapping_s section_mapping[] =
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/* SAMA5 Internal Memories */
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/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
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* beginning of the .text region must appear at address zero. There are
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* three ways to accomplish this:
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* beginning of the .text region must appear at address at the address
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* specified in the VBAR. There are three ways to accomplish this:
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*
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* 1. By explicitly mapping the beginning of .text region with a page
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* table entry so that the virtual address zero maps to the beginning
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* of the .text region.
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* of the .text region. VBAR == 0x0000:0000.
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*
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* 2. A second way is to map the use the AXI MATRIX remap register to
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* map physical address zero to the beginning of the text region,
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* either internal SRAM or EBI CS 0. Then we can set an identity
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* mapping to map the boot region at 0x0000:0000 to virtual address
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* 0x0000:00000
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* 0x0000:00000. VBAR == 0x0000:0000.
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*
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* This method is used when booting from NORFLASH. In that case,
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* vectors must lie at the beginning of NOFR FLASH.
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* This method is used when booting from ISRAM or NOR FLASH. In
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& that case, vectors must lie at the beginning of NOFR FLASH.
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*
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* 3. Set the AXI MATRIX remap register so that SRAM appears at address
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* zero, mapping the boot region to address 0, then copying the
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* vectors to address zero.
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* 3. Set the Cortex-A5 VBAR register so that the vector table address
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* is moved to a location other than 0x0000:0000.
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*
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* This is the method used when booting from either SDRAM or
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* SRAM.
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* This is the method used when booting from SDRAM.
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*
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* - When executing from NOR FLASH, the first level bootloader is supposed
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* to provide the AXI MATRIX mapping for us at boot time base on the state
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@ -181,21 +166,16 @@ static const struct section_mapping_s section_mapping[] =
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* probably copied us into ISRAM and set the AXI REMAP bit for us.
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*
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* - If we are executing from external SDRAM, then a secondary bootloader must
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* have loaded us into SDRAM. In this case, we will may the BOOT memory,
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* set the AXI matrix to locate the ISRAM in boot memory, and copy the vector
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* table ISRAM.
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* have loaded us into SDRAM. In this case, simply set the VBAR register
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* to the address of the vector table (not necessary at the beginning
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* or SDRAM).
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*/
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#if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM)
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# if defined(CONFIG_SAMA5_BOOT_SDRAM)
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{ SAM_ISRAM_PSECTION, 0x00000000,
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MMU_ROMFLAGS, 1
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},
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# else
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#if defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_SAMA5_BOOT_ISRAM) && \
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!defined(CONFIG_SAMA5_BOOT_SDRAM)
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{ CONFIG_FLASH_START, 0x00000000,
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MMU_ROMFLAGS, 1
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},
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# endif
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#else
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{ SAM_BOOTMEM_PSECTION, SAM_BOOTMEM_VSECTION,
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SAM_BOOTMEM_MMUFLAGS, SAM_BOOTMEM_NSECTIONS
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@ -512,7 +492,7 @@ static void sam_vectormapping(void)
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*
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****************************************************************************/
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#ifdef NEED_VECTOR_COPY
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#if !defined(CONFIG_ARCH_LOWVECTORS)
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static void sam_copyvectorblock(void)
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{
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uint32_t *src;
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@ -237,7 +237,9 @@ static uint32_t *sam_fiqhandler(int irq, uint32_t *regs)
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void up_irqinitialize(void)
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{
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#if defined(CONFIG_SAMA5_BOOT_ISRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH)
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size_t vectorsize;
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#endif
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int i;
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/* The following operations need to be atomic, but since this function is
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@ -309,7 +311,44 @@ void up_irqinitialize(void)
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putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, SAM_AIC_WPMR);
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#if defined(CONFIG_ARCH_LOWVECTORS)
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/* Set the vector base address register to zero */
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/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
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* beginning of the .text region must appear at address at the address
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* specified in the VBAR. There are three ways to accomplish this:
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*
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* 1. By explicitly mapping the beginning of .text region with a page
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* table entry so that the virtual address zero maps to the beginning
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* of the .text region. VBAR == 0x0000:0000.
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*
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* 2. A second way is to map the use the AXI MATRIX remap register to
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* map physical address zero to the beginning of the text region,
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* either internal SRAM or EBI CS 0. Then we can set an identity
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* mapping to map the boot region at 0x0000:0000 to virtual address
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* 0x0000:00000. VBAR == 0x0000:0000.
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*
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* This method is used when booting from ISRAM or NOR FLASH. In
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& that case, vectors must lie at the beginning of NOFR FLASH.
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*
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* 3. Set the Cortex-A5 VBAR register so that the vector table address
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* is moved to a location other than 0x0000:0000.
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*
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* This is the method used when booting from SDRAM.
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*
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* - When executing from NOR FLASH, the first level bootloader is supposed
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* to provide the AXI MATRIX mapping for us at boot time base on the state
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* of the BMS pin. However, I have found that in the test environments
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* that I use, I cannot always be assured of that physical address mapping.
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*
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* - If we are executing out of ISRAM, then the SAMA5 primary bootloader
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* probably copied us into ISRAM and set the AXI REMAP bit for us.
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*
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* - If we are executing from external SDRAM, then a secondary bootloader
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* must have loaded us into SDRAM. In this case, simply set the VBAR
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* register to the address of the vector table (not necessary at the
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* beginning or SDRAM).
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*/
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#if defined(CONFIG_SAMA5_BOOT_ISRAM) || defined(CONFIG_SAMA5_BOOT_CS0FLASH)
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/* Set the vector base address register to 0x0000:0000 */
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cp15_wrvbar(0);
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@ -338,12 +377,12 @@ void up_irqinitialize(void)
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* address 0x0000:0000 in that case anyway.
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*/
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#if defined(CONFIG_SAMA5_BOOT_ISRAM) || defined(CONFIG_SAMA5_BOOT_SDRAM)
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putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR); /* Enable Cortex-A5 remap */
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#if defined(CONFIG_SAMA5_BOOT_ISRAM)
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putreg32(AXIMX_REMAP_REMAP0, SAM_AXIMX_REMAP); /* Remap SRAM */
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#elif defined(CONFIG_SAMA5_BOOT_CS0FLASH)
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putreg32(MATRIX_MRCR_RCB0, SAM_MATRIX_MRCR); /* Enable Cortex-A5 remap */
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putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap NOR FLASH */
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#else /* elif defined(CONFIG_SAMA5_BOOT_CS0FLASH) */
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putreg32(AXIMX_REMAP_REMAP1, SAM_AXIMX_REMAP); /* Remap NOR FLASH on CS0 */
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#endif
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/* Make sure that there is no trace of any previous mapping */
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@ -359,8 +398,14 @@ void up_irqinitialize(void)
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putreg32(MATRIX_WPMR_WPKEY | MATRIX_WPMR_WPEN, SAM_MATRIX_WPMR);
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#endif
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/* It might be wise to flush the instruction cache here */
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#endif
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#elif defined(CONFIG_SAMA5_BOOT_SDRAM)
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/* Set the VBAR register to the address of the vector table in SDRAM */
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DEBUGASSERT((((uintptr_t)&_vector_start) & ~VBAR_MASK) == 0);
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cp15_wrvbar((uint32_t)&_vector_start);
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#endif /* CONFIG_SAMA5_BOOT_ISRAM || CONFIG_SAMA5_BOOT_CS0FLASH */
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#endif /* CONFIG_ARCH_LOWVECTORS */
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/* currents_regs is non-NULL only while processing an interrupt */
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