Add TIM header file
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arch/hc/src/mc9s12ne64/mc9s12ne64_tim16b4cv1.h
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arch/hc/src/mc9s12ne64/mc9s12ne64_tim16b4cv1.h
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/************************************************************************************
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* arch/hc/src/mc9s12ne64/mc9s12ne64_tim16b4cv1.h
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_TIM_H
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#define __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_TIM_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define HCS12_TIM_TIOS_OFFSET 0x0000 /* Timer Input Capture/Output Compare Select */
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#define HCS12_TIM_CFORC_OFFSET 0x0001 /* Timer Compare Force Register */
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#define HCS12_TIM_OC7M_OFFSET 0x0002 /* Output Compare 7 Mask Register */
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#define HCS12_TIM_OC7D_OFFSET 0x0003 /* Output Compare 7 Data Register */
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#define HCS12_TIM_TCNTHI2_OFFSET 0x0004 /* Timer Count Register */
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#define HCS12_TIM_TCNTLO2_OFFSET 0x0005 /* Timer Count Register */
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#define HCS12_TIM_TSCR1_OFFSET 0x0006 /* Timer System Control Register 1 */
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#define HCS12_TIM_TTOV_OFFSET 0x0007 /* Timer Toggle Overflow Register */
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#define HCS12_TIM_TCTL1_OFFSET 0x0008 /* Timer Control Register1 */
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#define HCS12_TIM_TCTL3_OFFSET 0x000a /* Timer Control Register3 */
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#define HCS12_TIM_TIE_OFFSET 0x000c /* Timer Interrupt Enable Register */
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#define HCS12_TIM_TSCR2_OFFSET 0x000d /* Timer System Control Register 2 */
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#define HCS12_TIM_TFLG1_OFFSET 0x000e /* Main Timer Interrupt Flag 1 */
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#define HCS12_TIM_TFLG2_OFFSET 0x000f /* Main Timer Interrupt Flag 2 */
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#define HCS12_TIM_TC4HI_OFFSET 0x0018 /* Timer Input Capture/Output Compare Register 4 */
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#define HCS12_TIM_TC4LO_OFFSET 0x0019 /* Timer Input Capture/Output Compare Register 4 */
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#define HCS12_TIM_TC5HI_OFFSET 0x001a /* Timer Input Capture/Output Compare Register 5 */
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#define HCS12_TIM_TC5LO_OFFSET 0x001b /* Timer Input Capture/Output Compare Register 5 */
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#define HCS12_TIM_TC6HI_OFFSET 0x001c /* Timer Input Capture/Output Compare Register 6 */
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#define HCS12_TIM_TC6LO_OFFSET 0x001d /* Timer Input Capture/Output Compare Register 6 */
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#define HCS12_TIM_TC7HI_OFFSET 0x001e /* Timer Input Capture/Output Compare Register 7 */
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#define HCS12_TIM_TC7LO_OFFSET 0x001f /* Timer Input Capture/Output Compare Register 7 */
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#define HCS12_TIM_PACTL_OFFSET 0x0020 /* 16-Bit Pulse Accumulator Control Register */
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#define HCS12_TIM_PAFLG_OFFSET 0x0021 /* Pulse Accumulator Flag Register */
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#define HCS12_TIM_PACNTHI_OFFSET 0x0022 /* Pulse Accumulator Count Register */
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#define HCS12_TIM_PACNTLO_OFFSET 0x0023 /* Pulse Accumulator Count Register */
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#define HCS12_TIM_TIMTST2_OFFSET 0x002d /* Timer Test Register */
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/* Register Addresses ***************************************************************/
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#define HCS12_TIM_TIOS (HCS12_TIM_BASE+HCS12_TIM_TIOS_OFFSET)
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#define HCS12_TIM_CFORC (HCS12_TIM_BASE+HCS12_TIM_CFORC_OFFSET)
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#define HCS12_TIM_OC7M (HCS12_TIM_BASE+HCS12_TIM_OC7M_OFFSET)
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#define HCS12_TIM_OC7D (HCS12_TIM_BASE+HCS12_TIM_OC7D_OFFSET)
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#define HCS12_TIM_TCNTHI2 (HCS12_TIM_BASE+HCS12_TIM_TCNTHI2_OFFSET)
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#define HCS12_TIM_TCNTLO2 (HCS12_TIM_BASE+HCS12_TIM_TCNTLO2_OFFSET)
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#define HCS12_TIM_TSCR1 (HCS12_TIM_BASE+HCS12_TIM_TSCR1_OFFSET)
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#define HCS12_TIM_TTOV (HCS12_TIM_BASE+HCS12_TIM_TTOV_OFFSET)
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#define HCS12_TIM_TCTL1 (HCS12_TIM_BASE+HCS12_TIM_TCTL1_OFFSET)
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#define HCS12_TIM_TCTL3 (HCS12_TIM_BASE+HCS12_TIM_TCTL3_OFFSET)
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#define HCS12_TIM_TIE (HCS12_TIM_BASE+HCS12_TIM_TIE_OFFSET)
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#define HCS12_TIM_TSCR2 (HCS12_TIM_BASE+HCS12_TIM_TSCR2_OFFSET)
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#define HCS12_TIM_TFLG1 (HCS12_TIM_BASE+HCS12_TIM_TFLG1_OFFSET)
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#define HCS12_TIM_TFLG2 (HCS12_TIM_BASE+HCS12_TIM_TFLG2_OFFSET)
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#define HCS12_TIM_TC4HI (HCS12_TIM_BASE+HCS12_TIM_TC4HI_OFFSET)
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#define HCS12_TIM_TC4LO (HCS12_TIM_BASE+HCS12_TIM_TC4LO_OFFSET)
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#define HCS12_TIM_TC5HI (HCS12_TIM_BASE+HCS12_TIM_TC5HI_OFFSET)
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#define HCS12_TIM_TC5LO (HCS12_TIM_BASE+HCS12_TIM_TC6HI_OFFSET)
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#define HCS12_TIM_TC6HI (HCS12_TIM_BASE+HCS12_TIM_TC6LO_OFFSET)
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#define HCS12_TIM_TC6LO (HCS12_TIM_BASE+HCS12_TIM_TC7HI_OFFSET)
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#define HCS12_TIM_TC7HI (HCS12_TIM_BASE+HCS12_TIM_TC7LO_OFFSET)
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#define HCS12_TIM_TC7LO (HCS12_TIM_BASE+HCS12_TIM_PACTL_OFFSET)
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#define HCS12_TIM_PACTL (HCS12_TIM_BASE+HCS12_TIM_PAFLG_OFFSET)
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#define HCS12_TIM_PAFLG (HCS12_TIM_BASE+HCS12_TIM_PACNTHI_OFFSET)
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#define HCS12_TIM_PACNTHI (HCS12_TIM_BASE+HCS12_TIM_PACNTLO_OFFSET)
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#define HCS12_TIM_PACNTLO (HCS12_TIM_BASE+HCS12_TIM_TIMTST2_OFFSET)
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#define HCS12_TIM_TIMTST2 (HCS12_TIM_BASE+HCS12_TIM_TIMTST2_OFFSET)
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/* Register Bit-Field Definitions ***************************************************/
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/* Timer Input Capture/Output Compare Select */
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#define TIM_TIOS_
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/* Timer Compare Force Register */
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#define TIM_CFORC_
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/* Output Compare 7 Mask Register */
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#define TIM_OC7M_
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/* Output Compare 7 Data Register */
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#define TIM_OC7D_
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/* Timer Count Register */
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#define TIM_TCNTHI2_
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/* Timer Count Register */
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#define TIM_TCNTLO2_
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/* Timer System Control Register 1 */
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#define TIM_TSCR1_
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/* Timer Toggle Overflow Register */
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#define TIM_TTOV_
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/* Timer Control Register1 */
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#define TIM_TCTL1_
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/* Timer Control Register3 */
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#define TIM_TCTL3_
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/* Timer Interrupt Enable Register */
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#define TIM_TIE_
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/* Timer System Control Register 2 */
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#define TIM_TSCR2_
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/* Main Timer Interrupt Flag 1 */
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#define TIM_TFLG1_
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/* Main Timer Interrupt Flag 2 */
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#define TIM_TFLG2_
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/* Timer Input Capture/Output Compare Register 4 */
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#define TIM_TC4HI_
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/* Timer Input Capture/Output Compare Register 4 */
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#define TIM_TC4LO_
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/* Timer Input Capture/Output Compare Register 5 */
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#define TIM_TC5HI_
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/* Timer Input Capture/Output Compare Register 5 */
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#define TIM_TC5LO_
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/* Timer Input Capture/Output Compare Register 6 */
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#define TIM_TC6HI_
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/* Timer Input Capture/Output Compare Register 6 */
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#define TIM_TC6LO_
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/* Timer Input Capture/Output Compare Register 7 */
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#define TIM_TC7HI_
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/* Timer Input Capture/Output Compare Register 7 */
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#define TIM_TC7LO_
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/* 16-Bit Pulse Accumulator Control Register */
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#define TIM_PACTL_
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/* Pulse Accumulator Flag Register */
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#define TIM_PAFLG_
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/* Pulse Accumulator Count Register */
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#define TIM_PACNTHI_
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/* Pulse Accumulator Count Register */
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#define TIM_PACNTLO_
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/* Timer Test Register */
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#define TIM_TIMTST2_
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_HC_SRC_MC9S12NE64_MC9S12NE64_TIM_H */
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