diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h index 1642f7df8c..6bdd8d9ad2 100644 --- a/arch/arm/src/armv7-m/mpu.h +++ b/arch/arm/src/armv7-m/mpu.h @@ -1,7 +1,7 @@ /***************************************************************************** * arch/arm/src/armv7-m/mpu.h * - * Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2020 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -31,14 +31,14 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************/ + *****************************************************************************/ #ifndef __ARCH_ARM_SRC_ARMV7M_MPU_H #define __ARCH_ARM_SRC_ARMV7M_MPU_H -/**************************************************************************** +/***************************************************************************** * Included Files - ****************************************************************************/ + *****************************************************************************/ #include @@ -52,9 +52,9 @@ # include "up_arch.h" #endif -/**************************************************************************** +/***************************************************************************** * Pre-processor Definitions - ****************************************************************************/ + *****************************************************************************/ /* MPU Register Addresses */ @@ -129,6 +129,14 @@ # define MPU_RASR_S (1 << 18) /* Bit 18: Shareable */ # define MPU_RASR_TEX_SHIFT (19) /* Bits 19-21: TEX Address Permisson */ # define MPU_RASR_TEX_MASK (7 << MPU_RASR_TEX_SHIFT) +# define MPU_RASR_TEX_SO (0 << MPU_RASR_TEX_SHIFT) /* Strongly Ordered */ +# define MPU_RASR_TEX_NOR (1 << MPU_RASR_TEX_SHIFT) /* Normal */ +# define MPU_RASR_TEX_DEV (2 << MPU_RASR_TEX_SHIFT) /* Device */ +# define MPU_RASR_TEX_BB(bb) (4|(bb)) << MPU_RASR_TEX_SHIFT) /* Normal BB AA */ +# define MPU_RASR_CP_NC (0) /* Non-cacheable */ +# define MPU_RASR_CP_WBRA (1) /* Write back, write and Read- Allocate */ +# define MPU_RASR_CP_WT (2) /* Write through, no Write-Allocate */ +# define MPU_RASR_CP_WB (4) /* Write back, no Write-Allocate */ # define MPU_RASR_AP_SHIFT (24) /* Bits 24-26: Access permission */ # define MPU_RASR_AP_MASK (7 << MPU_RASR_AP_SHIFT) # define MPU_RASR_AP_NONO (0 << MPU_RASR_AP_SHIFT) /* P:None U:None */ @@ -139,9 +147,9 @@ # define MPU_RASR_AP_RORO (6 << MPU_RASR_AP_SHIFT) /* P:RO U:RO */ # define MPU_RASR_XN (1 << 28) /* Bit 28: Instruction access disable */ -/**************************************************************************** +/***************************************************************************** * Public Function Prototypes - ****************************************************************************/ + *****************************************************************************/ #ifndef __ASSEMBLY__ #undef EXTERN @@ -153,17 +161,17 @@ extern "C" #define EXTERN extern #endif -/**************************************************************************** +/***************************************************************************** * Name: mpu_allocregion * * Description: * Allocate the next region * - ****************************************************************************/ + *****************************************************************************/ unsigned int mpu_allocregion(void); -/**************************************************************************** +/***************************************************************************** * Name: mpu_log2regionceil * * Description: @@ -172,11 +180,11 @@ unsigned int mpu_allocregion(void); * * size <= (1 << l2size) * - ****************************************************************************/ + *****************************************************************************/ uint8_t mpu_log2regionceil(size_t size); -/**************************************************************************** +/***************************************************************************** * Name: mpu_log2regionfloor * * Description: @@ -185,11 +193,11 @@ uint8_t mpu_log2regionceil(size_t size); * * size >= (1 << l2size) * - ****************************************************************************/ + *****************************************************************************/ uint8_t mpu_log2regionfloor(size_t size); -/**************************************************************************** +/***************************************************************************** * Name: mpu_subregion * * Description: @@ -201,21 +209,21 @@ uint8_t mpu_log2regionfloor(size_t size); * l2size has the same properties as the return value from * mpu_log2regionceil() * - ****************************************************************************/ + *****************************************************************************/ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size); -/**************************************************************************** +/***************************************************************************** * Inline Functions - ****************************************************************************/ + *****************************************************************************/ -/**************************************************************************** +/***************************************************************************** * Name: mpu_showtype * * Description: * Show the characteristics of the MPU * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_showtype(void) { @@ -229,13 +237,13 @@ static inline void mpu_showtype(void) #endif } -/**************************************************************************** +/***************************************************************************** * Name: mpu_control * * Description: * Configure and enable (or disable) the MPU * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena) { @@ -259,15 +267,16 @@ static inline void mpu_control(bool enable, bool hfnmiena, bool privdefena) putreg32(regval, MPU_CTRL); } -/**************************************************************************** - * Name: mpu_priv_stronglyordered +/***************************************************************************** + * Name: mpu_configure_region * * Description: * Configure a region for privileged, strongly ordered memory * - ****************************************************************************/ + *****************************************************************************/ -static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) +static inline void mpu_configure_region(uintptr_t base, size_t size, + uint32_t flags) { unsigned int region = mpu_allocregion(); uint32_t regval; @@ -292,327 +301,197 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) regval = MPU_RASR_ENABLE | /* Enable region */ MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - /* Not Cacheable */ - /* Not Bufferable */ - MPU_RASR_S | /* Shareable */ - MPU_RASR_AP_RWNO; /* P:RW U:None */ + flags; putreg32(regval, MPU_RASR); } -/**************************************************************************** +/***************************************************************************** + * Name: mpu_priv_stronglyordered + * + * Description: + * Configure a region for privileged, strongly ordered memory + * + *****************************************************************************/ + +static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size) +{ + /* The configure the region */ + + mpu_configure_region(base, size, + MPU_RASR_TEX_SO | /* Ordered */ + /* Not Cacheable */ + /* Not Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_AP_RWNO /* P:RW U:None */ + /* Instruction access */); +} + +/***************************************************************************** * Name: mpu_user_flash * * Description: * Configure a region for user program flash * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_user_flash(uintptr_t base, size_t size) { - unsigned int region = mpu_allocregion(); - uint32_t regval; - uint8_t l2size; - uint8_t subregions; - - /* Select the region */ - - putreg32(region, MPU_RNR); - - /* Select the region base address */ - - putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR); - - /* Select the region size and the sub-region map */ - - l2size = mpu_log2regionceil(size); - subregions = mpu_subregion(base, size, l2size); - /* The configure the region */ - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ - ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_AP_RORO; /* P:RO U:RO */ - putreg32(regval, MPU_RASR); + mpu_configure_region(base, size, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + /* Not Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RORO /* P:RO U:RO */ + /* Instruction access */); } -/**************************************************************************** +/***************************************************************************** * Name: mpu_priv_flash * * Description: * Configure a region for privileged program flash * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_priv_flash(uintptr_t base, size_t size) { - unsigned int region = mpu_allocregion(); - uint32_t regval; - uint8_t l2size; - uint8_t subregions; - - /* Select the region */ - - putreg32(region, MPU_RNR); - - /* Select the region base address */ - - putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR); - - /* Select the region size and the sub-region map */ - - l2size = mpu_log2regionceil(size); - subregions = mpu_subregion(base, size, l2size); - /* The configure the region */ - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ - ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_AP_RONO; /* P:RO U:None */ - putreg32(regval, MPU_RASR); +mpu_configure_region(base, size, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + /* Not Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RONO /* P:RO U:None */ + /* Instruction access */); } -/**************************************************************************** +/***************************************************************************** * Name: mpu_user_intsram * * Description: * Configure a region as user internal SRAM * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_user_intsram(uintptr_t base, size_t size) { - unsigned int region = mpu_allocregion(); - uint32_t regval; - uint8_t l2size; - uint8_t subregions; - - /* Select the region */ - - putreg32(region, MPU_RNR); - - /* Select the region base address */ - - putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR); - - /* Select the region size and the sub-region map */ - - l2size = mpu_log2regionceil(size); - subregions = mpu_subregion(base, size, l2size); - /* The configure the region */ - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ - ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - MPU_RASR_S | /* Shareable */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_AP_RWRW; /* P:RW U:RW */ - putreg32(regval, MPU_RASR); + mpu_configure_region(base, size, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + /* Not Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); } -/**************************************************************************** +/***************************************************************************** * Name: mpu_priv_intsram * * Description: * Configure a region as privileged internal SRAM * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_priv_intsram(uintptr_t base, size_t size) { - unsigned int region = mpu_allocregion(); - uint32_t regval; - uint8_t l2size; - uint8_t subregions; - - /* Select the region */ - - putreg32(region, MPU_RNR); - - /* Select the region base address */ - - putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR); - - /* Select the region size and the sub-region map */ - - l2size = mpu_log2regionceil(size); - subregions = mpu_subregion(base, size, l2size); - /* The configure the region */ - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ - ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - MPU_RASR_S | /* Shareable */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_AP_RWNO; /* P:RW U:None */ - putreg32(regval, MPU_RASR); + mpu_configure_region(base, size, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + /* Not Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_AP_RWNO /* P:RW U:None */ + /* Instruction access */); } -/**************************************************************************** +/***************************************************************************** * Name: mpu_user_extsram * * Description: * Configure a region as user external SRAM * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_user_extsram(uintptr_t base, size_t size) { - unsigned int region = mpu_allocregion(); - uint32_t regval; - uint8_t l2size; - uint8_t subregions; - - /* Select the region */ - - putreg32(region, MPU_RNR); - - /* Select the region base address */ - - putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR); - - /* Select the region size and the sub-region map */ - - l2size = mpu_log2regionceil(size); - subregions = mpu_subregion(base, size, l2size); - /* The configure the region */ - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ - ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - MPU_RASR_S | /* Shareable */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable */ - MPU_RASR_AP_RWRW; /* P:RW U:RW */ - putreg32(regval, MPU_RASR); + mpu_configure_region(base, size, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); } -/**************************************************************************** +/***************************************************************************** * Name: mpu_priv_extsram * * Description: * Configure a region as privileged external SRAM * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_priv_extsram(uintptr_t base, size_t size) { - unsigned int region = mpu_allocregion(); - uint32_t regval; - uint8_t l2size; - uint8_t subregions; - - /* Select the region */ - - putreg32(region, MPU_RNR); - - /* Select the region base address */ - - putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR); - - /* Select the region size and the sub-region map */ - - l2size = mpu_log2regionceil(size); - subregions = mpu_subregion(base, size, l2size); - /* The configure the region */ - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ - ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - MPU_RASR_S | /* Shareable */ - MPU_RASR_C | /* Cacheable */ - MPU_RASR_B | /* Bufferable */ - MPU_RASR_AP_RWNO; /* P:RW U:None */ - putreg32(regval, MPU_RASR); + mpu_configure_region(base, size, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_AP_RWNO /* P:RW U:None */ + /* Instruction access */); } -/**************************************************************************** +/***************************************************************************** * Name: mpu_peripheral * * Description: * Configure a region as privileged peripheral address space * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_peripheral(uintptr_t base, size_t size) { - unsigned int region = mpu_allocregion(); - uint32_t regval; - uint8_t l2size; - uint8_t subregions; - - /* Select the region */ - - putreg32(region, MPU_RNR); - - /* Select the region base address */ - - putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR); - - /* Select the region size and the sub-region map */ - - l2size = mpu_log2regionceil(size); - subregions = mpu_subregion(base, size, l2size); - /* Then configure the region */ - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ - ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - MPU_RASR_S | /* Shareable */ - MPU_RASR_B | /* Bufferable */ - MPU_RASR_AP_RWNO | /* P:RW U:None */ - MPU_RASR_XN; /* Instruction access disable */ - - putreg32(regval, MPU_RASR); + mpu_configure_region(base, size, + MPU_RASR_TEX_DEV | /* Device */ + /* Not Cacheable */ + MPU_RASR_B | /* Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_AP_RWNO | /* P:RW U:None */ + MPU_RASR_XN /* No Instruction access */); } -/**************************************************************************** +/***************************************************************************** * Name: mpu_user_peripheral * * Description: * Configure a region as user peripheral address space * - ****************************************************************************/ + *****************************************************************************/ static inline void mpu_user_peripheral(uintptr_t base, size_t size) { - unsigned int region = mpu_allocregion(); - uint32_t regval; - uint8_t l2size; - uint8_t subregions; - - /* Select the region */ - - putreg32(region, MPU_RNR); - - /* Select the region base address */ - - putreg32((base & MPU_RBAR_ADDR_MASK) | region, MPU_RBAR); - - /* Select the region size and the sub-region map */ - - l2size = mpu_log2regionceil(size); - subregions = mpu_subregion(base, size, l2size); - /* Then configure the region */ - regval = MPU_RASR_ENABLE | /* Enable region */ - MPU_RASR_SIZE_LOG2((uint32_t)l2size) | /* Region size */ - ((uint32_t)subregions << MPU_RASR_SRD_SHIFT) | /* Sub-regions */ - MPU_RASR_S | /* Shareable */ - MPU_RASR_B | /* Bufferable */ - MPU_RASR_AP_RWRW | /* P:RW U:RW */ - MPU_RASR_XN; /* Instruction access disable */ - - putreg32(regval, MPU_RASR); + mpu_configure_region(base, size, + MPU_RASR_TEX_DEV | /* Device */ + /* Not Cacheable */ + MPU_RASR_B | /* Bufferable */ + MPU_RASR_S | /* Shareable */ + MPU_RASR_AP_RWRW | /* P:RW U:RW */ + MPU_RASR_XN /* No Instruction access */); } #undef EXTERN diff --git a/arch/arm/src/imxrt/Kconfig b/arch/arm/src/imxrt/Kconfig index 92cb3806f5..50b7f3b6f4 100644 --- a/arch/arm/src/imxrt/Kconfig +++ b/arch/arm/src/imxrt/Kconfig @@ -848,14 +848,14 @@ endmenu # IMXRT_ENET menu "Memory Configuration" config IMXRT_DTCM - bool "Enable DTCM" - default n - depends on !IMXRT_OCRAM_PRIMARY && EXPERIMENTAL + int "FLEXRAM DTCM Size in K" + default 128 + depends on ARMV7M_HAVE_DTCM config IMXRT_ITCM - bool "Enable ITCM" - default n - depends on !IMXRT_OCRAM_PRIMARY && EXPERIMENTAL + int "FLEXRAM ITCM Size in K" + default 128 + depends on ARMV7M_HAVE_ITCM config IMXRT_SEMC_SDRAM bool "External SDRAM installed" @@ -958,6 +958,12 @@ config IMXRT_OCRAM_HEAP ---help--- Select to add the entire OCRAM to the heap +config IMXRT_DTCM_HEAP + bool "Add DTCM to heap" + depends on IMXRT_DTCM > 0 + ---help--- + Select to add the entire DTCM to the heap + config IMXRT_SDRAM_HEAP bool "Add SDRAM to heap" depends on IMXRT_SEMC_SDRAM && !IMXRT_SDRAM_PRIMARY diff --git a/arch/arm/src/imxrt/Make.defs b/arch/arm/src/imxrt/Make.defs index 099f23919a..b208d9a477 100644 --- a/arch/arm/src/imxrt/Make.defs +++ b/arch/arm/src/imxrt/Make.defs @@ -113,6 +113,9 @@ CHIP_CSRCS += imxrt_gpioirq.c endif ifeq ($(CONFIG_ARM_MPU),y) +ifneq ($(CONFIG_BUILD_PROTECTED),y) +CMN_CSRCS += up_mpu.c +endif CHIP_CSRCS += imxrt_mpuinit.c ifeq ($(CONFIG_BUILD_PROTECTED),y) CHIP_CSRCS += imxrt_userspace.c diff --git a/arch/arm/src/imxrt/imxrt_allocateheap.c b/arch/arm/src/imxrt/imxrt_allocateheap.c index 22a0a406d1..c203a02b05 100644 --- a/arch/arm/src/imxrt/imxrt_allocateheap.c +++ b/arch/arm/src/imxrt/imxrt_allocateheap.c @@ -62,7 +62,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Terminology. In the flat build (CONFIG_BUILD_FLAT=y), there is only a * single heap access with the standard allocations (malloc/free). This * heap is referred to as the user heap. In the protected build @@ -81,10 +83,9 @@ * Primary RAM: The Linker script positions the system BLOB's .data and * .bss in some RAM. We refer to that RAM as the primary RAM. It also * holds the IDLE threads stack and any remaining portion of the primary - * RAM is automatically added to the heap. The start and size of the - * primary RAM are provided by CONFIG_RAM_START and CONFIG_RAM_SIZE. The - * linker provided address, ... .sbss, .ebss, .sdat, etc. ... are expected - * to lie in the the region defined by those configuration settings. + * OCRAM is automatically added to the heap. The linker provided address, + * ... .sbss, .ebss, .sdat, etc. ... are expected to lie in the the region + * defined by the OCRAM configuration settings. * * Other RAM regions must be selected use configuration options and the * start and end of those RAM regions must also be provided in the @@ -110,22 +111,29 @@ */ /* There there then several memory configurations with a one primary memory - * region and up to two additional memory regions which may be OCRAM, + * region and up to two additional memory regions which may be OCRAM, DTCM * external SDRAM, or external SRAM. */ #undef IMXRT_OCRAM_ASSIGNED +#undef IMXRT_DCTM_ASSIGNED #undef IMXRT_SDRAM_ASSIGNED #undef IMXRT_SRAM_ASSIGNED -/* REVISIT: Assume that if OCRAM is the primary RAM, then DTCM and ITCM are - * not being used. - * When configured DTCM and ITCM consume OCRAM from the address space +/* When configured DTCM and ITCM consume OCRAM from the address space * labeled IMXRT_OCRAM_BASE that uses the FlexRAM controller to allocate * the function of OCRAM. * * The 1 MB version of the SOC have a second 512Kib of OCRAM that can not * be consumed by the DTCM or ITCM. + * + * If we order the memory with the FlexRAM controller from high to low banks + * as ITCM DTCM OCRAM we can achieve an continuous RAM layout of + * + * High OCRAM-(DTCM Size, ITCM Size) + * Low OCRAM2 + * + * The pieces of the OCRAM used for DTCM and ITCM DTCM and ITCM memory spaces */ #if defined(IMXRT_OCRAM2_BASE) @@ -133,9 +141,34 @@ #else # define _IMXRT_OCRAM_BASE IMXRT_OCRAM_BASE #endif + +#define CONFIG_ITCM_USED 0 +#if defined(CONFIG_IMXRT_ITCM) +# if (CONFIG_IMXRT_ITCM % 32) != 0 +# error IMXRT_ITCM must be divisible by 32 +# endif +# undef CONFIG_ITCM_USED +# define CONFIG_ITCM_USED (CONFIG_IMXRT_ITCM * 1024) +#else +# define CONFIG_IMXRT_ITCM 0 +#endif + +#define CONFIG_DTCM_USED 0 +#if defined(CONFIG_IMXRT_DTCM) +# if (CONFIG_IMXRT_DTCM % 32) != 0 +# error CONFIG_IMXRT_DTCM must be divisible by 32 +# endif +# undef CONFIG_DTCM_USED +# define CONFIG_DTCM_USED (CONFIG_IMXRT_DTCM * 1024) +#else +# define IMXRT_DTCM 0 +#endif + +#define FLEXRAM_REMAINING_K ((IMXRT_OCRAM_SIZE / 1024) - (CONFIG_IMXRT_DTCM + CONFIG_IMXRT_DTCM)) + #if defined(CONFIG_IMXRT_OCRAM_PRIMARY) -# define PRIMARY_RAM_START _IMXRT_OCRAM_BASE /* CONFIG_RAM_START */ -# define PRIMARY_RAM_SIZE IMXRT_OCRAM_SIZE /* CONFIG_RAM_SIZE */ +# define PRIMARY_RAM_START _IMXRT_OCRAM_BASE +# define PRIMARY_RAM_SIZE IMXRT_OCRAM_SIZE - (CONFIG_ITCM_USED + CONFIG_DTCM_USED) # define IMXRT_OCRAM_ASSIGNED 1 #elif defined(CONFIG_IMXRT_SDRAM_PRIMARY) # define PRIMARY_RAM_START CONFIG_IMXRT_SDRAM_START /* CONFIG_RAM_START */ @@ -151,23 +184,13 @@ #define PRIMARY_RAM_END (PRIMARY_RAM_START + PRIMARY_RAM_SIZE) -/* REVISIT: I am not sure how this works. But I am assuming that if DTCM - * is enabled, then ITCM is not and we can just use the DTCM base address to - * access OCRAM. - * - * The FlexRAM controller manages the allocation of DTCM and ITCM from the +/* The FlexRAM controller manages the allocation of DTCM and ITCM from the * OCRAM. The amount allocated it 2^n KiB where n is 2-9 and is configured in * the GPR register space. */ -#ifdef CONFIG_IMXRT_DTCM -# define IMXRT_OCRAM_START IMXRT_DTCM_BASE -#else -# define IMXRT_OCRAM_START _IMXRT_OCRAM_BASE -#endif - #if CONFIG_MM_REGIONS > 1 -/* Pick the first region to add to the heap could be any one of OCRAM, +/* Pick the first region to add to the heap could be any one of OCRAM, DTCM, * SDRAM, or SRAM depending upon which are enabled and which has not * already been assigned as the primary RAM. */ @@ -176,6 +199,10 @@ # define REGION1_RAM_START IMXRT_OCRAM_START # define REGION1_RAM_SIZE IMXRT_OCRAM_SIZE # define IMXRT_OCRAM_ASSIGNED 1 +#elif defined(CONFIG_IMXRT_DTCM_HEAP) && !defined(IMXRT_DCTM_ASSIGNED) +# define REGION1_RAM_START IMXRT_DTCM_BASE +# define REGION1_RAM_SIZE CONFIG_DTCM_USED +# define IMXRT_DCTM_ASSIGNED 1 #elif defined(CONFIG_IMXRT_SDRAM_HEAP) && !defined(IMXRT_SDRAM_ASSIGNED) # define REGION1_RAM_START (CONFIG_IMXRT_SDRAM_START + CONFIG_IMXRT_SDRAM_HEAPOFFSET) # define REGION1_RAM_SIZE (CONFIG_IMXRT_SDRAM_SIZE - CONFIG_IMXRT_SDRAM_HEAPOFFSET) diff --git a/arch/arm/src/imxrt/imxrt_lpspi.c b/arch/arm/src/imxrt/imxrt_lpspi.c index 8c8838662a..efd66b1672 100644 --- a/arch/arm/src/imxrt/imxrt_lpspi.c +++ b/arch/arm/src/imxrt/imxrt_lpspi.c @@ -97,9 +97,9 @@ /***************************************************************************** * Pre-processor Definitions - ****************************************************************************/ + *****************************************************************************/ -/* Configuration ************************************************************/ +/* Configuration *************************************************************/ /* SPI interrupts */ @@ -119,7 +119,7 @@ /***************************************************************************** * Private Types - ****************************************************************************/ + *****************************************************************************/ struct imxrt_lpspidev_s { @@ -144,7 +144,7 @@ enum imxrt_delay_e /***************************************************************************** * Private Function Prototypes - ****************************************************************************/ + *****************************************************************************/ /* Helpers */ @@ -1180,7 +1180,7 @@ static void imxrt_lpspi_setbits(FAR struct spi_dev_s *dev, int nbits) * Zero (OK) if the selected H/W features are enabled; A negated errno * value if any H/W feature is not supportable. * - ****************************************************************************/ + *****************************************************************************/ #ifdef CONFIG_SPI_HWFEATURES static int imxrt_lpspi_hwfeatures(FAR struct spi_dev_s *dev, @@ -1369,7 +1369,7 @@ static void imxrt_lpspi_exchange_nodma(FAR struct spi_dev_s *dev, } #endif /* !CONFIG_IMXRT_LPSPI_DMA || CONFIG_IMXRT_DMACAPABLE */ -/**************************************************************************** +/***************************************************************************** * Name: imxrt_lpspi_sndblock * * Description: @@ -1570,7 +1570,7 @@ static void imxrt_lpspi_bus_initialize(struct imxrt_lpspidev_s *priv) * Returned Value: * Valid SPI device structure reference on success; a NULL on failure * - ****************************************************************************/ + *****************************************************************************/ FAR struct spi_dev_s *imxrt_lpspibus_initialize(int bus) { diff --git a/arch/arm/src/imxrt/imxrt_mpuinit.c b/arch/arm/src/imxrt/imxrt_mpuinit.c index ebfebadca6..d04a239f8f 100644 --- a/arch/arm/src/imxrt/imxrt_mpuinit.c +++ b/arch/arm/src/imxrt/imxrt_mpuinit.c @@ -1,7 +1,7 @@ /**************************************************************************** * arch/arm/src/imxrt/imxrt_mpuinit.c * - * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Copyright (C) 2018, 2020 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -115,6 +115,89 @@ void imxrt_mpu_initialize(void) DEBUGASSERT(dataend >= datastart); mpu_user_intsram(datastart, dataend - datastart); +#else + mpu_configure_region(0xc0000000, 512 * 1024 * 1024, + MPU_RASR_TEX_DEV | /* Device */ + /* Not Cacheable */ + /* Not Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_configure_region(IMXRT_EXTMEM_BASE, 1024 * 1024 * 1024, + MPU_RASR_TEX_DEV | /* Device */ + /* Not Cacheable */ + /* Not Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_configure_region(IMXRT_FLEXCIPHER_BASE, 8 * 1024 * 1024, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RORO /* P:RO U:RO */ + /* Instruction access */); + + mpu_configure_region(0x00000000, 1024 * 1024 * 1024, + MPU_RASR_TEX_DEV | /* Device */ + /* Not Cacheable */ + /* Not Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_configure_region(IMXRT_ITCM_BASE, 128 * 1024, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_configure_region(IMXRT_DTCM_BASE, 128 * 1024, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_configure_region(IMXRT_OCRAM2_BASE, 512 * 1024, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_configure_region(IMXRT_OCRAM_BASE, 512 * 1024, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_configure_region(IMXRT_EXTMEM_BASE, 32 * 1024 * 1024, + MPU_RASR_TEX_SO | /* Ordered */ + MPU_RASR_C | /* Cacheable */ + MPU_RASR_B | /* Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_configure_region(0x81e00000, 2 * 1024 * 1024, + MPU_RASR_TEX_NOR | /* Normal */ + /* Not Cacheable */ + /* Not Bufferable */ + /* Not Shareable */ + MPU_RASR_AP_RWRW /* P:RW U:RW */ + /* Instruction access */); + + mpu_control(true, true, true); + return; #endif /* Then enable the MPU */ diff --git a/arch/arm/src/imxrt/imxrt_serial.c b/arch/arm/src/imxrt/imxrt_serial.c index 9a5ed10d6f..e05afd7e16 100644 --- a/arch/arm/src/imxrt/imxrt_serial.c +++ b/arch/arm/src/imxrt/imxrt_serial.c @@ -258,6 +258,7 @@ * UART 5-8 could be the console. One of UART5-8 has already been * assigned to ttys0, 1, 2, 3, or 4. */ + #if defined(CONFIG_IMXRT_LPUART5) && !defined(UART5_ASSIGNED) # define TTYS5_DEV g_uart5port /* LPUART5 is ttyS5 */ # define UART5_ASSIGNED 1 @@ -541,7 +542,7 @@ static struct uart_dev_s g_uart2port = { .size = CONFIG_LPUART2_TXBUFSIZE, .buffer = g_uart2txbuffer, - }, + }, .ops = &g_uart_ops, .priv = &g_uart2priv, }; @@ -922,11 +923,11 @@ static int imxrt_setup(struct uart_dev_s *dev) { struct imxrt_uart_s *priv = (struct imxrt_uart_s *)dev->priv; #ifndef CONFIG_SUPPRESS_LPUART_CONFIG + int ret; struct uart_config_s config = { 0 }; - int ret; /* Configure the UART */ @@ -1121,6 +1122,7 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) #if defined(CONFIG_SERIAL_TIOCSERGSTRUCT) || defined(CONFIG_SERIAL_TERMIOS) struct inode *inode = filep->f_inode; struct uart_dev_s *dev = inode->i_private; + irqstate_t flags; #endif int ret = OK; @@ -1196,9 +1198,11 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) termiosp->c_cflag |= CS8; break; +#if defined(CS9) case 9: - termiosp->c_cflag |= CS8 /* CS9 */; + termiosp->c_cflag |= CS9; break; +#endif } } break; @@ -1250,7 +1254,8 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) case CS8: nbits = 8; break; -#if 0 + +#if defined(CS9) case CS9: nbits = 9; break; @@ -1295,6 +1300,7 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) * implement TCSADRAIN / TCSAFLUSH */ + flags = spin_lock_irqsave(); imxrt_disableuartint(priv, &ie); ret = imxrt_setup(dev); @@ -1302,6 +1308,7 @@ static int imxrt_ioctl(struct file *filep, int cmd, unsigned long arg) imxrt_restoreuartint(priv, ie); priv->ie = ie; + spin_unlock_irqrestore(flags); } } break; @@ -1552,32 +1559,29 @@ static void up_pm_notify(struct pm_callback_s *cb, int domain, case(PM_NORMAL): { /* Logic for PM_NORMAL goes here */ - } break; case(PM_IDLE): { /* Logic for PM_IDLE goes here */ - } break; case(PM_STANDBY): { /* Logic for PM_STANDBY goes here */ - } break; case(PM_SLEEP): { /* Logic for PM_SLEEP goes here */ - } break; default: + /* Should not get here */ break;