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Merged in ziggurat29/boards/nucleomod-20160325a (pull request #34)

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minor; clocking changes to stm32l4 nucleo to support CLK48 for  RNG functionality (and any others)
This commit is contained in:
Gregory Nutt 2016-03-25 17:54:29 -06:00
commit 04d1b03abf
1 changed files with 9 additions and 4 deletions
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13
configs/nucleo-l476rg/include/nucleo-l476rg.h
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@ -190,8 +190,8 @@
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
#define STM32L4_PLLCFG_PLLP 0
#undef STM32L4_PLLCFG_PLLP_ENABLED
#define STM32L4_PLLCFG_PLLQ 0
#undef STM32L4_PLLCFG_PLLQ_ENABLED
#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
#define STM32L4_PLLCFG_PLLQ_ENABLED
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
#define STM32L4_PLLCFG_PLLR_ENABLED
@ -199,8 +199,8 @@
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(10)
#define STM32L4_PLLSAI1CFG_PLLP 0
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ 0
#undef STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
#define STM32L4_PLLSAI1CFG_PLLR RCC_PLLSAI1CFG_PLLR(2)
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
@ -213,6 +213,11 @@
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
/* CLK48 will come from PLLSAI1 (implicitly Q) */
#define STM32L4_USE_CLK48
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
/* AHB clock (HCLK) is SYSCLK (80MHz) */
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */