EFM32: Correct handling of DMA descriptors; Add initialization of DMA CTRLBASE
This commit is contained in:
Gregory Nutt
parent
ca202adadb
commit
04d732dbab
@ -165,13 +165,12 @@ config EFM32_GPIO_IRQ
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if EFM32_DMA
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config EFM32_DMA_NDESCR
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int "Pre-allocated Control Structures"
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config EFM32_DMA_ALTDSEC
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int "Enable alternate descriptors"
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default 8
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depends on EXPERIMENTAL
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---help---
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DMA transfers require DMA channel control descriptors. These
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descriptors are pre-allocated and this setting provides the number
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of descriptors that will be pre-allocated.
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Enable support for alternate descriptors. Not fully implemented.
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endif
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@ -65,34 +65,27 @@
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/*****************************************************************************
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* Public Types
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*****************************************************************************/
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/* This union allows us to keep free DMA descriptors in in a list */
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union dma_descriptor_u
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{
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sq_entry_t link;
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struct dma_descriptor_s desc;
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};
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/* This structure describes one DMA channel */
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struct dma_channel_s
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{
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uint8_t chan; /* DMA channel number (0-EFM32_DMA_NCHANNELS) */
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bool inuse; /* TRUE: The DMA channel is in use */
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struct dma_descriptor_s *desc; /* DMA descriptor assigned to the channel */
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dma_config_t config; /* Current configuration */
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dma_callback_t callback; /* Callback invoked when the DMA completes */
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void *arg; /* Argument passed to callback function */
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uint8_t chan; /* DMA channel number (0-EFM32_DMA_NCHANNELS) */
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bool inuse; /* TRUE: The DMA channel is in use */
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struct dma_descriptor_s *desc; /* Primary DMA descriptor for channel */
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#ifdef CONFIG_EFM32_DMA_ALTDSEC
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struct dma_descriptor_s *alt; /* Alternate DMA descriptor for channel */
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#endif
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dma_config_t config; /* Current configuration */
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dma_callback_t callback; /* Callback invoked when the DMA completes */
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void *arg; /* Argument passed to callback function */
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};
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/* This structure describes the state of the DMA controller */
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struct dma_controller_s
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{
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sem_t exclsem; /* Protects channel table */
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sem_t chansem; /* Count of free channels */
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sem_t freesem; /* Count of free descriptors */
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sq_queue_t freedesc; /* List of free DMA descriptors */
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sem_t exclsem; /* Protects channel table */
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sem_t chansem; /* Count of free channels */
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};
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/*****************************************************************************
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@ -111,9 +104,14 @@ static struct dma_channel_s g_dmach[EFM32_DMA_NCHANNELS];
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* Each structure must be aligned to the size of the DMA descriptor.
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*/
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static union dma_descriptor_u g_descriptors[CONFIG_EFM32_DMA_NDESCR]
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static struct dma_descriptor_s g_primary_descriptors[EFM32_DMA_NCHANNELS]
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__attribute__((aligned(16)));
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#ifdef CONFIG_EFM32_DMA_ALTDSEC
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static struct dma_descriptor_s g_alt_descriptors[EFM32_DMA_NCHANNELS]
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__attribute__((aligned(16)));
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#endif
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/*****************************************************************************
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* Public Data
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*****************************************************************************/
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@ -122,82 +120,6 @@ static union dma_descriptor_u g_descriptors[CONFIG_EFM32_DMA_NDESCR]
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* Private Functions
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*****************************************************************************/
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/****************************************************************************
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* Name: efm32_alloc_descriptor
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*
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* Description:
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* Allocate one DMA descriptor by removing it from the free list.
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*
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* Returned Value:
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* The allocated DMA descriptor. If no DMA descriptors are available, this
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* function will wait until one is returned to the freelist.
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*
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****************************************************************************/
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static struct dma_descriptor_s *efm32_alloc_descriptor(void)
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{
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struct dma_descriptor_s *desc;
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irqstate_t flags;
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/* Take a count from from the descriptor counting semaphore. We may block
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* if there are no free descriptors. When we get the count, then we can
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* be assured that a DMA descriptor is available in the free list and is
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* reserved for us.
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*/
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flags = irqsave();
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while (sem_wait(&g_dmac.freesem) < 0)
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{
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/* sem_wait should fail only if it is awakened by a a signal */
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DEBUGASSERT(errno == EINTR);
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}
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/* Get our descriptor to the free list. Interrupts mus be disabled here
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* because the free list may also be accessed from the DMA interrupt
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* handler.
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*/
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desc = (struct dma_descriptor_s *)sq_remfirst(&g_dmac.freedesc);
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irqrestore(flags);
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/* And return the descriptor */
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DEBUGASSERT(desc && ((uintptr_t)desc & ~15) == 0);
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return desc;
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}
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/****************************************************************************
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* Name: efm32_free_descriptor
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*
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* Description:
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* Free one DMA descriptor by returning it to the free list.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void efm32_free_descriptor(struct dma_descriptor_s *desc)
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{
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union dma_descriptor_u *udesc = (union dma_descriptor_u *)desc;
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irqstate_t flags;
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/* Return the descriptor to the free list. This may be called from the
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* the DMA completion interrupt handler.
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*/
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flags = irqsave();
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sq_addlast(&udesc->link, &g_dmac.freedesc);
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irqrestore(flags);
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/* Notify any waiters that a new DMA descriptor is available in the free
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* list.
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*/
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sem_post(&g_dmac.freesem);
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}
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/****************************************************************************
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* Name: efm32_set_chctrl
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*
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@ -314,16 +236,6 @@ void weak_function up_dmainitialize(void)
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dmallvdbg("Initialize XDMAC0\n");
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/* Add the pre-allocated DMA descriptors to the free list */
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sq_init(&g_dmac.freedesc);
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sem_init(&g_dmac.freesem, 0, CONFIG_EFM32_DMA_NDESCR);
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for (i = 0; i < CONFIG_EFM32_DMA_NDESCR; i++)
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{
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sq_addlast(&g_descriptors[i].link, &g_dmac.freedesc);
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}
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/* Initialize the channel list */
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sem_init(&g_dmac.exclsem, 0, 1);
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@ -332,6 +244,10 @@ void weak_function up_dmainitialize(void)
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for (i = 0; i < EFM32_DMA_NCHANNELS; i++)
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{
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g_dmach[i].chan = i;
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g_dmach[i].desc = &g_primary_descriptors[i];
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#ifdef CONFIG_EFM32_DMA_ALTDSEC
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g_dmach[i].alt = &g_alt_descriptors[i];
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#endif
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}
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/* Enable clock to the DMA module. DMA is clocked by HFCORECLK. */
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@ -340,6 +256,13 @@ void weak_function up_dmainitialize(void)
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regval |= CMU_HFCORECLKEN0_DMA;
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putreg32(regval, EFM32_CMU_HFCORECLKEN0);
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/* Set the primary and alternate control base addresses */
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putreg32((uint32_t)g_primary_descriptors, EFM32_DMA_CTRLBASE);
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#ifdef CONFIG_EFM32_DMA_ALTDSEC
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putreg32((uint32_t)g_alt_descriptors, EFM32_DMA_ALTCTRLBASE);
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#endif
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/* Attach DMA interrupt vector */
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(void)irq_attach(EFM32_IRQ_DMA, efm32_dmac_interrupt);
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@ -525,10 +448,8 @@ void efm32_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
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nbytes = ALIGN_DOWN(nbytes, mask);
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DEBUGASSERT(nbytes > 0);
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/* Allocate a DMA descriptor for the channel. We may block here. */
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/* Save the configuration (for efm32_dmastart()). */
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desc = efm32_alloc_descriptor();
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dmach->desc = desc;
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dmach->config = config;
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/* Configure for the selected peripheral */
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@ -537,6 +458,7 @@ void efm32_rxdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
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/* Configure the primary channel descriptor */
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desc = dmach->desc;
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desc->srcend = (uint32_t *)paddr;
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desc->dstend = (uint32_t *)(maddr + nbytes - xfersize);
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@ -611,10 +533,8 @@ void efm32_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
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nbytes = ALIGN_DOWN(nbytes, mask);
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DEBUGASSERT(nbytes > 0);
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/* Allocate a DMA descriptor for the channel. We may block here. */
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/* Save the configuration (for efm32_dmastart()). */
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desc = efm32_alloc_descriptor();
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dmach->desc = desc;
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dmach->config = config;
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/* Configure for the selected peripheral */
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@ -623,6 +543,7 @@ void efm32_txdmasetup(DMA_HANDLE handle, uintptr_t paddr, uintptr_t maddr,
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/* Configure the primary channel descriptor */
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desc = dmach->desc;
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desc->srcend = (uint32_t *)(maddr + nbytes - xfersize);
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desc->dstend = (uint32_t *)paddr;
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@ -746,7 +667,7 @@ void efm32_dmastop(DMA_HANDLE handle)
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uint32_t regval;
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uint32_t bit;
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DEBUGASSERT(dmach && dmach->inuse && dmach->desc);
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DEBUGASSERT(dmach && dmach);
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bit = 1 << dmach->chan;
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/* Disable the channel */
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@ -759,15 +680,6 @@ void efm32_dmastop(DMA_HANDLE handle)
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regval = getreg32(EFM32_DMA_IEN);
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regval |= bit;
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putreg32(bit, EFM32_DMA_IEN);
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/* Free any attached DMA descriptor */
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if (dmach->desc)
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{
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efm32_free_descriptor(dmach->desc);
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dmach->desc = NULL;
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}
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irqrestore(flags);
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}
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