LPC43 update
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5001 42af7a65-404d-4744-a932-0658087f49c3
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@ -901,6 +901,16 @@ Where <subdir> is one of the following:
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CONFIG_BOOT_SRAM=y : Executing in SRAM
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CONFIG_LPC32_CODEREDW=y : Code Red under Windows
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To execute from SRAM, you would need to set:
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CONFIG_BOOT_SPIFI=y : Executing from SPIFI
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CONFIG_DRAM_SIZE=(128*1024) : SRAM Bank0 size
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CONFIG_DRAM_START=0x10000000 : SRAM Bank0 base address
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CONFIG_SPIFI_OFFSET=(128*1024) : SPIFI file system offset
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CONFIG_MM_REGIONS should also be increased if you want to other SRAM banks
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to the memory pool.
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This configuration has some special options that can be used to
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create a block device on the SPIFI FLASH. NOTE: CONFIG_LPC43_SPIFI=y
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must also be defined to enable SPIFI setup support:
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@ -923,7 +933,7 @@ Where <subdir> is one of the following:
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CONFIG_SPIFI_READONLY - Define to support only read-only operations.
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CONFIG_SPIFI_LIBRARY - Don't use the LPC43xx ROM routines but, instead,
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use an external library implementation of the SPIFI interface.
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CONFIG_SPIFI_VERIFY - Verify all spi_program() operations by reading
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CONFIG_SPIFI_VERIFY - Verify all spifi_program() operations by reading
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from the SPI address space after each write.
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CONFIG_DEBUG_SPIFI_DUMP - Debug option to dump read/write buffers. You
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probably do not want to enable this unless you want to dig through a
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@ -193,7 +193,7 @@
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#define BOARD_UART1_BASEFREQ BOARD_XTAL_FREQUENCY
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#define BOARD_USART2_CLKSRC BASE_USART2_CLKSEL_XTAL
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#define BOARD_USART3_BASEFREQ BOARD_XTAL_FREQUENCY
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#define BOARD_USART2_BASEFREQ BOARD_XTAL_FREQUENCY
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#define BOARD_USART3_CLKSRC BASE_USART3_CLKSEL_XTAL
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#define BOARD_USART3_BASEFREQ BOARD_XTAL_FREQUENCY
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@ -266,6 +266,14 @@
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#define PINCONF_U1_TXD PINCONF_U1_TXD_1
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#define PINCONF_U1_RXD PINCONF_U1_RXD_1
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#define PINCONF_U2_TXD PINCONF_U2_TXD_1
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#define PINCONF_U2_RXD PINCONF_U2_RXD_1
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#define PINCONF_U2_DIR PINCONF_U2_DIR_1
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#define PINCONF_U3_TXD PINCONF_U3_TXD_2
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#define PINCONF_U3_RXD PINCONF_U3_RXD_2
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#define PINCONF_U3_DIR PINCONF_U3_DIR_2
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/****************************************************************************
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* Public Types
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****************************************************************************/
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@ -104,7 +104,7 @@ ifeq ($(CONFIG_BOOT_SRAM),y)
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LDSCRIPT = ramconfig.ld
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endif
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ifeq ($(CONFIG_BOOT_SPIFI),y)
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LDSCRIPT = spiconfig.ld
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LDSCRIPT = spificonfig.ld
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endif
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ifeq ($(CONFIG_BOOT_FLASHA),y)
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LDSCRIPT = flashaconfig.ld
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@ -696,7 +696,7 @@ CONFIG_MMCSD_HAVECARDDETECT=n
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# CONFIG_SPIFI_READONLY - Define to support only read-only operations.
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# CONFIG_SPIFI_LIBRARY - Don't use the LPC43xx ROM routines but, instead,
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# use an external library implementation of the SPIFI interface.
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# CONFIG_SPIFI_VERIFY - Verify all spi_program() operations by reading
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# CONFIG_SPIFI_VERIFY - Verify all spifi_program() operations by reading
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# from the SPI address space after each write.
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# CONFIG_DEBUG_SPIFI_DUMP - Debug option to dump read/write buffers. You
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# probably do not want to enable this unless you want to dig through a
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@ -104,7 +104,7 @@ ifeq ($(CONFIG_BOOT_SRAM),y)
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LDSCRIPT = ramconfig.ld
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endif
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ifeq ($(CONFIG_BOOT_SPIFI),y)
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LDSCRIPT = spiconfig.ld
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LDSCRIPT = spificonfig.ld
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endif
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ifeq ($(CONFIG_BOOT_FLASHA),y)
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LDSCRIPT = flashaconfig.ld
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@ -1,5 +1,5 @@
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/****************************************************************************
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* configs/lpc4330-xplorer/scripts/spiconfig.ld
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* configs/lpc4330-xplorer/scripts/spificonfig.ld
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -77,7 +77,7 @@ CSRCS += $(SPIFI_LIB)/spifi_rom_api.c
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#CSRCS += $(SPIFI_LIB)/numonyx.c
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CSRCS += $(SPIFI_LIB)/spansion.c
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#CSRCS += $(SPIFI_LIB)/sst.c
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#CSRCS += $(SPIFI_LIB)/winbond.c
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CSRCS += $(SPIFI_LIB)/winbond.c
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endif
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AOBJS = $(ASRCS:.S=$(OBJEXT))
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