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Add few more EHCI definitions

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This commit is contained in:
Gregory Nutt 2013-08-18 13:01:13 -06:00
parent 44dd71de4e
commit 0524688c71
5 changed files with 172 additions and 33 deletions
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90
arch/arm/src/sama5/chip/sam_ehci.h Normal file
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@ -0,0 +1,90 @@
/****************************************************************************
* arch/arm/src/sama5/chip/sam_ehci.h
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/usb/ohci.h>
#include "chip.h"
#include "chip/sam_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The SAMA5 supports 3 root hub ports */
#define SAM_EHCI_NRHPORT 3
/* Registers ****************************************************************/
/* Traditionally, NuttX specifies register locations using individual
* register offsets from a base address. That tradition is broken here and,
* instead, register blocks are represented as structures. This is done here
* because, in principle, EHCI operational register address may not be known
* at compile time; the operational registers lie at an offset specified in
* the 'caplength' byte of the Host Controller Capability Registers.
*
* However, for the case of the SAMA5 EHCI, we know apriori that the value
* of 'caplength' is 0x10. We keep this structure, however, to faciltate
* porting this driver to other environments where, perhaps, such knowledge
* is not availaable.
*/
/* Host Controller Capability Registers */
#define HCCR ((struct ehci_hccr_s *)SAM_UHPEHCI_VSECTION
/* Host Controller Operational Registers */
#define HCOR ((volatile struct ehci_hcor_s *)(SAM_UHPEHCI_VSECTION + 0x10)
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_EHCI_H */

8
arch/arm/src/sama5/chip/sam_ohci.h
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@ -33,8 +33,8 @@
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H
#ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H
#define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H
/****************************************************************************
* Included Files
@ -51,7 +51,7 @@
****************************************************************************/
/* The SAMA5 supports 3 root hub ports */
#define SAM_USBHOST_NRHPORT 3
#define SAM_OHCI_NRHPORT 3
/* Register offsets *********************************************************/
/* See nuttx/usb/ohci.h */
@ -109,4 +109,4 @@
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_USB_H */
#endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_OHCI_H */

24
arch/arm/src/sama5/sam_ohci.c
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@ -161,8 +161,8 @@
* and one for the tail ED for each RHPort:
*/
#define SAMA5_OHCI_NEDS (CONFIG_SAMA5_OHCI_NEDS + SAM_USBHOST_NRHPORT)
#define SAMA5_OHCI_NTDS (CONFIG_SAMA5_OHCI_NTDS + SAM_USBHOST_NRHPORT)
#define SAMA5_OHCI_NEDS (CONFIG_SAMA5_OHCI_NEDS + SAM_OHCI_NRHPORT)
#define SAMA5_OHCI_NTDS (CONFIG_SAMA5_OHCI_NTDS + SAM_OHCI_NRHPORT)
/* TD delay interrupt value */
@ -228,7 +228,7 @@ struct sam_ohci_s
/* Root hub ports */
struct sam_rhport_s rhport[SAM_USBHOST_NRHPORT];
struct sam_rhport_s rhport[SAM_OHCI_NRHPORT];
};
/* The OCHI expects the size of an endpoint descriptor to be 16 bytes.
@ -505,7 +505,7 @@ static void sam_checkreg(uint32_t addr, uint32_t val, bool iswrite)
count = 0;
prevwrite = iswrite;
/* Show the new regisgter access */
/* Show the new register access */
sam_printreg(addr, val, iswrite);
}
@ -930,8 +930,8 @@ static void sam_setinttab(uint32_t value, unsigned int interval, unsigned int of
/* Make sure that the modified table value is flushed to RAM */
cp15_coherent_dcache(&g_hcca.inttbl[i],
&g_hcca.inttbl[i] + sizeof(uint32_t) - 1);
cp15_coherent_dcache((uintptr_t)&g_hcca.inttbl[i],
(uintptr_t)&g_hcca.inttbl[i] + sizeof(uint32_t) - 1);
}
}
#endif
@ -1687,7 +1687,7 @@ static void sam_rhsc_interrupt(void)
/* Handle root hub status change on each root port */
for (rhpndx = 0; rhpndx < SAM_USBHOST_NRHPORT; rhpndx++)
for (rhpndx = 0; rhpndx < SAM_OHCI_NRHPORT; rhpndx++)
{
rhport = &g_ohci.rhport[rhpndx];
@ -2028,7 +2028,7 @@ static int sam_wait(FAR struct usbhost_connection_s *conn,
{
/* Check for a change in the connection state on any root hub port */
for (rhpndx = 0; rhpndx < SAM_USBHOST_NRHPORT; rhpndx++)
for (rhpndx = 0; rhpndx < SAM_OHCI_NRHPORT; rhpndx++)
{
/* Has the connection state changed on the RH port? */
@ -2089,7 +2089,7 @@ static int sam_enumerate(FAR struct usbhost_connection_s *conn, int rhpndx)
uint32_t regaddr;
int ret;
DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_USBHOST_NRHPORT);
DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_OHCI_NRHPORT);
rhport = &g_ohci.rhport[rhpndx];
/* Are we connected to a device? The caller should have called the wait()
@ -2179,7 +2179,7 @@ static int sam_ep0configure(FAR struct usbhost_driver_s *drvr, uint8_t funcaddr,
struct sam_ed_s *edctrl;
DEBUGASSERT(rhport &&
funcaddr >= 0 && funcaddr <= SAM_USBHOST_NRHPORT &&
funcaddr >= 0 && funcaddr <= SAM_OHCI_NRHPORT &&
maxpacketsize < 2048);
edctrl = rhport->ep0.ed;
@ -3072,7 +3072,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
/* Initialize the root hub port structures */
for (i = 0; i < SAM_USBHOST_NRHPORT; i++)
for (i = 0; i < SAM_OHCI_NRHPORT; i++)
{
struct sam_rhport_s *rhport = &g_ohci.rhport[i];
@ -3153,7 +3153,7 @@ FAR struct usbhost_connection_s *sam_ohci_initialize(int controller)
* connected. We need to set the initial connected state accordingly.
*/
for (i = 0; i < SAM_USBHOST_NRHPORT; i++)
for (i = 0; i < SAM_OHCI_NRHPORT; i++)
{
regval = sam_getreg(SAM_USBHOST_RHPORTST(i));
g_ohci.rhport[i].connected = ((regval & OHCI_RHPORTST_CCS) != 0);

4
configs/sama5d3x-ek/src/sam_usb.c
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@ -98,7 +98,7 @@ static struct usbhost_connection_s *g_ehciconn;
#if HAVE_USBHOST
static int usbhost_waiter(struct usbhost_connection_s *dev)
{
bool connected[SAM_USBHOST_NRHPORT] = {false, false, false};
bool connected[SAM_OHCI_NRHPORT] = {false, false, false};
int rhpndx;
uvdbg("Running\n");
@ -107,7 +107,7 @@ static int usbhost_waiter(struct usbhost_connection_s *dev)
/* Wait for the device to change state */
rhpndx = CONN_WAIT(dev, connected);
DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_USBHOST_NRHPORT);
DEBUGASSERT(rhpndx >= 0 && rhpndx < SAM_OHCI_NRHPORT);
connected[rhpndx] = !connected[rhpndx];

79
include/nuttx/usb/ehci.h
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@ -545,7 +545,7 @@
#define QH_HLP_TYP_MASK (3 << QH_HLP_TYP_SHIFT)
# define QH_HLP_TYP_ITD (0 << QH_HLP_TYP_SHIFT) /* Isochronous Transfer Descriptor */
# define QH_HLP_TYP_QH (1 << QH_HLP_TYP_SHIFT) /* Queue Head */
# define QH_HLP_TYP_QH_ (2 << QH_HLP_TYP_SHIFT) /* Split Transaction Isochronous Transfer Descriptor */
# define QH_HLP_TYP_SITD (2 << QH_HLP_TYP_SHIFT) /* Split Transaction Isochronous Transfer Descriptor */
# define QH_HLP_TYP_FSTN (3 << QH_HLP_TYP_SHIFT) /* Frame Span Traversal Node */
/* Bits 3-4: Reserved */
#define QH_HLP_MASK (0xffffffe0) /* Bits 5-31: Queue Head Horizontal Link Pointer */
@ -584,6 +584,11 @@
#define QH_EPCAPS_MULT_SHIFT (30) /* Bit 30-31: High-Bandwidth Pipe Multiplier */
#define QH_EPCAPS_MULT_MASK (3 << QH_EPCAPS_MULT_SHIFT)
/* Current qTD Link Pointer. Table 3-21 */
#define QH_CQP_NTEP_SHIFT (5) /* Bits 5-31: Next Transfer Element Pointer */
#define QH_CQP_NTEP_MASK (0xffffffe0)
/* Transfer Overlay. Paragraph 3.6.3
*
* NOTES:
@ -592,11 +597,6 @@
* additional bitfields.
*/
/* Current qTD Link Pointer. Table 3-21 */
#define QH_CQP_NTEP_SHIFT (5) /* Bits 5-31: Next Transfer Element Pointer */
#define QH_CQP_NTEP_MASK (0xffffffe0)
/* Next qTD Pointer (NOTE 1) */
#define QH_NQP_T (1 << 0) /* Bit 0: Terminate */
@ -689,6 +689,42 @@
/********************************************************************************************
* Public Types
********************************************************************************************/
/* Registers ********************************************************************************/
/* Since the operational registers are not known a compile time, representing register blocks
* with structures is more convenient than using individual register offsets.
*/
/* Host Controller Capability Registers. This register block must be positioned at a well
* known address.
*/
struct ehci_hccr_s
{
uint8_t caplength; /* 0x00: Capability Register Length */
uint8_t reserved;
uint16_t hciversion; /* 0x02: Interface Version Number */
uint32_t hcsparams; /* 0x04: Structural Parameters */
uint32_t hccparams; /* 0x08: Capability Parameters */
uint8_t hcspportrt[8]; /* 0x0c: Companion Port Route Description */
};
/* Host Controller Operational Registers. This register block is positioned at an offset
* of 'caplength' from the beginning of the Host Controller Capability Registers.
*/
struct ehci_hcor_s
{
uint32_t usbcmd; /* 0x00: USB Command */
uint32_t usbsts; /* 0x04: USB Status */
uint32_t usbintr; /* 0x08: USB Interrupt Enable */
uint32_t frindex; /* 0x0c: USB Frame Index */
uint32_t ctrldssegment; /* 0x10: 4G Segment Selector */
uint32_t periodiclistbase; /* 0x14: Frame List Base Address */
uint32_t asynclistaddr; /* 0x18: Next Asynchronous List Address */
uint32_t reserved[9];
uint32_t configflag; /* 0x40: Configured Flag Register */
uint32_t portsc[15]; /* 0x44: Port Status/Control */
};
/* Data Structures **************************************************************************/
/* Paragraph 3 */
@ -707,6 +743,8 @@ struct ehci_itd_s
uint32_t bpl[7]; /* 0x24-0x3c: Buffer Page Pointer List */
};
#define SIZEOF_EHCI_ITD_S (64) /* 16*sizeof(uint32_t) */
/* Split Transaction Isochronous Transfer Descriptor (siTD). Paragraph 3.4 */
struct ehci_sitd_s
@ -719,15 +757,20 @@ struct ehci_sitd_s
uint32_t blp; /* 0x18-0x1b: Back link pointer */
};
#define SIZEOF_EHCI_SITD_S (28) /* 7*sizeof(uint32_t) */
/* Queue Element Transfer Descriptor (qTD). Paragraph 3.5 */
/* 32-bit version. See EHCI Appendix B for the 64-bit version. */
struct ehci_qtd_s
{
uint32_t nqp; /* 0x00-0x03: Next qTD Pointer */
uint32_t anqp; /* 0x04-0x07: Alternate Next qTD Pointer */
uint32_t alt; /* 0x04-0x07: Alternate Next qTD Pointer */
uint32_t token; /* 0x08-0x0b: qTD Token */
uint32_t bpl[5]; /* 0x0c-0x1c: Buffer Page Pointer List */
}
};
#define SIZEOF_EHCI_QTD_S (32) /* 8*sizeof(uint32_t) */
/* Queue Head. Paragraph 3.6
*
@ -737,23 +780,27 @@ struct ehci_qtd_s
* additional bitfields.
*/
struct ehci_overly_s
struct ehci_overlay_s
{
uint32_t cqp; /* 0x00-0x03: Current qTD Pointer */
uint32_t nqp; /* 0x04-0x07: Next qTD Pointer (NOTE 1) */
uint32_t anqp; /* 0x08-0x0b: Alternate Next qTD Pointer (NOTE 2) */
uint32_t token; /* 0x0c-0x0f: qTD Token (NOTE 1) */
uint32_t bpl[5]; /* 0x10-0x23: Buffer Page Pointer List (NOTE 2)*/
uint32_t nqp; /* 0x00-0x03: Next qTD Pointer (NOTE 1) */
uint32_t alt; /* 0x04-0x07: Alternate Next qTD Pointer (NOTE 2) */
uint32_t token; /* 0x08-0x0b: qTD Token (NOTE 1) */
uint32_t bpl[5]; /* 0x0c-0x1c: Buffer Page Pointer List (NOTE 2)*/
};
#define SIZEOF_EHCI_OVERLAY (32) /* 8*sizeof(uint32_t) */
struct ehci_qh_s
{
uint32_t hlp; /* 0x00-0x03: Queue Head Horizontal Link Pointer */
uint32_t epchar; /* 0x04-0x07: Endpoint Characteristics */
uint32_t epcaps; /* 0x08-0x0b: Endpoint Capabilities */
struct ehci_overly_s overlay; /* 0x0c-0x2f: Transfer overlay */
uint32_t cqp; /* 0x0c-0x0f: Current qTD Pointer */
struct ehci_overlay_s overlay; /* 0x10-0x2c: Transfer overlay */
};
#define SIZEOF_EHCI_OVERLAY (48) /* 4*sizeof(uint32_t) + SIZEOF_EHCI_OVERLAY */
/* Periodic Frame Span Traversal Node (STN). Paragrap 3.7 */
struct ehci_fstn_s
@ -762,6 +809,8 @@ struct ehci_fstn_s
uint32_t bpp; /* 0x04-0x07: Back Path Link Pointer */
};
#define SIZEOF_EHCI_FSTN_S (8) /* 2*sizeof(uint32_t) */
/********************************************************************************************
* Public Data
********************************************************************************************/