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Attach mem mgmt fault handle if MPU is enabled

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3471 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2011-04-06 01:51:07 +00:00
parent 3910f865ec
commit 056b895642
20 changed files with 2091 additions and 1970 deletions
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4
arch/arm/include/lm3s/irq.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/lm3s/irq.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -63,7 +63,7 @@
/* Vector 1: Reset (not handler as an IRQ) */
#define LM3S_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LM3S_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LM3S_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */
#define LM3S_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LM3S_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LM3S_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LM3S_IRQ_SVCALL (11) /* Vector 11: SVC call */

2
arch/arm/include/lpc17xx/irq.h
View File

@ -64,7 +64,7 @@
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define LPC17_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define LPC17_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */
#define LPC17_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define LPC17_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define LPC17_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define LPC17_IRQ_SVCALL (11) /* Vector 11: SVC call */

4
arch/arm/include/sam3u/irq.h
View File

@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/include/sam3u/irq.h
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -94,7 +94,7 @@
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM3U_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define SAM3U_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define SAM3U_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */
#define SAM3U_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define SAM3U_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define SAM3U_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define SAM3U_IRQ_SVCALL (11) /* Vector 11: SVC call */

2
arch/arm/include/stm32/irq.h
View File

@ -63,7 +63,7 @@
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define STM32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define STM32_IRQ_MPU (4) /* Vector 4: Memory management (MPU) */
#define STM32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define STM32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define STM32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define STM32_IRQ_SVCALL (11) /* Vector 11: SVC call */

1
arch/arm/src/common/up_internal.h
View File

@ -181,6 +181,7 @@ extern void up_lowputs(const char *str);
extern uint32_t *up_doirq(int irq, uint32_t *regs);
extern int up_svcall(int irq, FAR void *context);
extern int up_hardfault(int irq, FAR void *context);
extern int up_memfault(int irq, FAR void *context);
#else /* CONFIG_ARCH_CORTEXM3 */

110
arch/arm/src/cortexm3/up_memfault.c Normal file
View File

@ -0,0 +1,110 @@
/****************************************************************************
* arch/arm/src/cortexm3/up_memfault.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <debug.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "os_internal.h"
#include "nvic.h"
#include "up_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#undef DEBUG_MEMFAULTS /* Define to debug memory management faults */
#ifdef DEBUG_MEMFAULTS
# define mfdbg(format, arg...) lldbg(format, ##arg)
#else
# define mfdbg(x...)
#endif
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_memfault
*
* Description:
* This is Memory Management Fault exception handler. Normally we get here
* when the Cortex M3 MPU is enabled and an MPU fault is detected. However,
* I understand that there are other error conditions that can also generate
* memory management faults.
*
****************************************************************************/
int up_memfault(int irq, FAR void *context)
{
/* Dump some memory management fault info */
(void)irqsave();
lldbg("PANIC!!! Memory Management Fault:\n");
mfdbg(" IRQ: %d context: %p\n", irq, regs);
lldbg(" CFAULTS: %08x MMFAR: %08x\n",
getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR));
mfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
mfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
mfdbg(" PSR=%08x\n", regs[REG_XPSR]);
PANIC(OSERR_UNEXPECTEDISR);
return OK;
}

4
arch/arm/src/lm3s/Make.defs
View File

@ -1,7 +1,7 @@
############################################################################
# arch/arm/src/lm3s/Make.defs
#
# Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
# Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
#
# Redistribution and use in source and binary forms, with or without
@ -39,7 +39,7 @@ CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \
up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
up_releasepending.c up_releasestack.c up_reprioritizertr.c \
up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
up_usestack.c up_doirq.c up_hardfault.c up_svcall.c

29
arch/arm/src/lm3s/lm3s_irq.c
View File

@ -2,7 +2,7 @@
* arch/arm/src/lm3s/lm3s_irq.c
* arch/arm/src/chip/lm3s_irq.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -128,7 +128,7 @@ static void lm3s_dumpnvic(const char *msg, int irq)
#endif
/****************************************************************************
* Name: lm3s_nmi, lm3s_mpu, lm3s_busfault, lm3s_usagefault, lm3s_pendsv,
* Name: lm3s_nmi, lm3s_busfault, lm3s_usagefault, lm3s_pendsv,
* lm3s_dbgmonitor, lm3s_pendsv, lm3s_reserved
*
* Description:
@ -147,14 +147,6 @@ static int lm3s_nmi(int irq, FAR void *context)
return 0;
}
static int lm3s_mpu(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! MPU interrupt received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int lm3s_busfault(int irq, FAR void *context)
{
(void)irqsave();
@ -234,7 +226,7 @@ static int lm3s_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
else
{
*regaddr = NVIC_SYSHCON;
if (irq == LM3S_IRQ_MPU)
if (irq == LM3S_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
@ -324,11 +316,22 @@ void up_irqinitialize(void)
/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LM3S_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(LM3S_IRQ_NMI, lm3s_nmi);
irq_attach(LM3S_IRQ_MPU, lm3s_mpu);
#ifndef CONFIG_CORTEXM3_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LM3S_IRQ_BUSFAULT, lm3s_busfault);
irq_attach(LM3S_IRQ_USAGEFAULT, lm3s_usagefault);
irq_attach(LM3S_IRQ_PENDSV, lm3s_pendsv);
@ -434,7 +437,7 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= LM3S_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < LM3S_IRQ_INTERRUPTS)
{

3
arch/arm/src/lm3s/lm3s_vectors.S
View File

@ -368,7 +368,7 @@ handlers:
HANDLER lm3s_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER lm3s_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER lm3s_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER lm3s_mpu, LM3S_IRQ_MPU /* Vector 4: Memory management (MPU) */
HANDLER lm3s_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER lm3s_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER lm3s_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER lm3s_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */
@ -546,7 +546,6 @@ handlers:
# error "Vectors not specified for this LM3S chip"
#endif
/* Common IRQ handling logic. On entry here, the stack is like the following:
*
* REG_XPSR

2
arch/arm/src/lpc17xx/Make.defs
View File

@ -41,7 +41,7 @@ HEAD_ASRC = lpc17_vectors.S
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
up_mdelay.c up_udelay.c up_exit.c up_initialize.c \
up_mdelay.c up_udelay.c up_exit.c up_initialize.c up_memfault.c \
up_initialstate.c up_interruptcontext.c up_modifyreg8.c \
up_modifyreg16.c up_modifyreg32.c up_releasepending.c \
up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \

27
arch/arm/src/lpc17xx/lpc17_irq.c
View File

@ -127,7 +127,7 @@ static void lpc17_dumpnvic(const char *msg, int irq)
#endif
/****************************************************************************
* Name: lpc17_nmi, lpc17_mpu, lpc17_busfault, lpc17_usagefault, lpc17_pendsv,
* Name: lpc17_nmi, lpc17_busfault, lpc17_usagefault, lpc17_pendsv,
* lpc17_dbgmonitor, lpc17_pendsv, lpc17_reserved
*
* Description:
@ -146,14 +146,6 @@ static int lpc17_nmi(int irq, FAR void *context)
return 0;
}
static int lpc17_mpu(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! MPU interrupt received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int lpc17_busfault(int irq, FAR void *context)
{
(void)irqsave();
@ -233,7 +225,7 @@ static int lpc17_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
else
{
*regaddr = NVIC_SYSHCON;
if (irq == LPC17_IRQ_MPU)
if (irq == LPC17_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
@ -312,11 +304,22 @@ void up_irqinitialize(void)
/* up_prioritize_irq(LPC17_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LPC17_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(LPC17_IRQ_NMI, lpc17_nmi);
irq_attach(LPC17_IRQ_MPU, lpc17_mpu);
#ifndef CONFIG_CORTEXM3_MPU
irq_attach(LPC17_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LPC17_IRQ_BUSFAULT, lpc17_busfault);
irq_attach(LPC17_IRQ_USAGEFAULT, lpc17_usagefault);
irq_attach(LPC17_IRQ_PENDSV, lpc17_pendsv);
@ -449,7 +452,7 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= LPC17_IRQ_MPU && irq < LPC17_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
DEBUGASSERT(irq >= LPC17_IRQ_MEMFAULT && irq < LPC17_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < LPC17_IRQ_EXTINT)
{

4
arch/arm/src/lpc17xx/lpc17_vectors.S
View File

@ -2,7 +2,7 @@
* arch/arm/src/lpc17xx/lpc17_vectors.S
* arch/arm/src/chip/lpc17_vectors.S
*
* Copyright (C) 2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2010-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -176,7 +176,7 @@ handlers:
HANDLER lpc17_reserved, LPC17_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER lpc17_nmi, LPC17_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER lpc17_hardfault, LPC17_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER lpc17_mpu, LPC17_IRQ_MPU /* Vector 4: Memory management (MPU) */
HANDLER lpc17_mpu, LPC17_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER lpc17_busfault, LPC17_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER lpc17_usagefault, LPC17_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER lpc17_svcall, LPC17_IRQ_SVCALL /* Vector 11: SVC call */

2
arch/arm/src/sam3u/Make.defs
View File

@ -42,7 +42,7 @@ HEAD_ASRC = sam3u_vectors.S
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
up_mdelay.c up_udelay.c up_exit.c up_idle.c up_initialize.c \
up_initialstate.c up_interruptcontext.c up_modifyreg8.c \
up_initialstate.c up_interruptcontext.c up_memfault.c up_modifyreg8.c \
up_modifyreg16.c up_modifyreg32.c up_releasepending.c \
up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
up_sigdeliver.c up_unblocktask.c up_usestack.c up_doirq.c \

29
arch/arm/src/sam3u/sam3u_irq.c
View File

@ -2,7 +2,7 @@
* arch/arm/src/sam3u/sam3u_irq.c
* arch/arm/src/chip/sam3u_irq.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -124,7 +124,7 @@ static void sam3u_dumpnvic(const char *msg, int irq)
#endif
/****************************************************************************
* Name: sam3u_nmi, sam3u_mpu, sam3u_busfault, sam3u_usagefault, sam3u_pendsv,
* Name: sam3u_nmi, sam3u_busfault, sam3u_usagefault, sam3u_pendsv,
* sam3u_dbgmonitor, sam3u_pendsv, sam3u_reserved
*
* Description:
@ -143,14 +143,6 @@ static int sam3u_nmi(int irq, FAR void *context)
return 0;
}
static int sam3u_mpu(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! MPU interrupt received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int sam3u_busfault(int irq, FAR void *context)
{
(void)irqsave();
@ -225,7 +217,7 @@ static int sam3u_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
else
{
*regaddr = NVIC_SYSHCON;
if (irq == SAM3U_IRQ_MPU)
if (irq == SAM3U_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
@ -305,11 +297,22 @@ void up_irqinitialize(void)
/* up_prioritize_irq(SAM3U_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
up_enable_irq(SAM3U_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(SAM3U_IRQ_NMI, sam3u_nmi);
irq_attach(SAM3U_IRQ_MPU, sam3u_mpu);
#ifndef CONFIG_CORTEXM3_MPU
irq_attach(SAM3U_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(SAM3U_IRQ_BUSFAULT, sam3u_busfault);
irq_attach(SAM3U_IRQ_USAGEFAULT, sam3u_usagefault);
irq_attach(SAM3U_IRQ_PENDSV, sam3u_pendsv);
@ -439,7 +442,7 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= SAM3U_IRQ_MPU && irq < SAM3U_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
DEBUGASSERT(irq >= SAM3U_IRQ_MEMFAULT && irq < SAM3U_IRQ_NIRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < SAM3U_IRQ_EXTINT)
{

2
arch/arm/src/sam3u/sam3u_vectors.S
View File

@ -172,7 +172,7 @@ handlers:
HANDLER sam3u_reserved, SAM3U_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER sam3u_nmi, SAM3U_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER sam3u_hardfault, SAM3U_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER sam3u_mpu, SAM3U_IRQ_MPU /* Vector 4: Memory management (MPU) */
HANDLER sam3u_mpu, SAM3U_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER sam3u_busfault, SAM3U_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER sam3u_usagefault, SAM3U_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER sam3u_svcall, SAM3U_IRQ_SVCALL /* Vector 11: SVC call */

2
arch/arm/src/stm32/Make.defs
View File

@ -39,7 +39,7 @@ CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
up_initialize.c up_initialstate.c up_interruptcontext.c \
up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
up_releasepending.c up_releasestack.c up_reprioritizertr.c \
up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
up_usestack.c up_doirq.c up_hardfault.c up_svcall.c

29
arch/arm/src/stm32/stm32_irq.c
View File

@ -2,7 +2,7 @@
* arch/arm/src/stm32/stm32_irq.c
* arch/arm/src/chip/stm32_irq.c
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -134,7 +134,7 @@ static void stm32_dumpnvic(const char *msg, int irq)
#endif
/****************************************************************************
* Name: stm32_nmi, stm32_mpu, stm32_busfault, stm32_usagefault, stm32_pendsv,
* Name: stm32_nmi, stm32_busfault, stm32_usagefault, stm32_pendsv,
* stm32_dbgmonitor, stm32_pendsv, stm32_reserved
*
* Description:
@ -153,14 +153,6 @@ static int stm32_nmi(int irq, FAR void *context)
return 0;
}
static int stm32_mpu(int irq, FAR void *context)
{
(void)irqsave();
dbg("PANIC!!! MPU interrupt received\n");
PANIC(OSERR_UNEXPECTEDISR);
return 0;
}
static int stm32_busfault(int irq, FAR void *context)
{
(void)irqsave();
@ -245,7 +237,7 @@ static int stm32_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
else
{
*regaddr = NVIC_SYSHCON;
if (irq == STM32_IRQ_MPU)
if (irq == STM32_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
@ -339,11 +331,22 @@ void up_irqinitialize(void)
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
* Fault handler.
*/
#ifdef CONFIG_CORTEXM3_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
up_enable_irq(STM32_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(STM32_IRQ_NMI, stm32_nmi);
irq_attach(STM32_IRQ_MPU, stm32_mpu);
#ifndef CONFIG_CORTEXM3_MPU
irq_attach(STM32_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault);
irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault);
irq_attach(STM32_IRQ_PENDSV, stm32_pendsv);
@ -449,7 +452,7 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= STM32_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < STM32_IRQ_INTERRUPTS)
{

5
arch/arm/src/stm32/stm32_vectors.S
View File

@ -2,7 +2,7 @@
* arch/arm/src/stm32/stm32_vectors.S
* arch/arm/src/chip/stm32_vectors.S
*
* Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@ -271,7 +271,7 @@ handlers:
HANDLER stm32_reserved, STM32_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER stm32_nmi, STM32_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER stm32_hardfault, STM32_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER stm32_mpu, STM32_IRQ_MPU /* Vector 4: Memory management (MPU) */
HANDLER stm32_mpu, STM32_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER stm32_busfault, STM32_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER stm32_usagefault, STM32_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER stm32_svcall, STM32_IRQ_SVCALL /* Vector 11: SVC call */
@ -532,3 +532,4 @@ g_heapbase:
.size g_heapbase, .-g_heapbase
.end

2
configs/detron/nsh/defconfig
View File

@ -652,7 +652,7 @@ CONFIG_LPC17_USBDEV_DMAINTMASK=0
# CONFIG_USBHOST_IOBUFSIZE
# Size of one end-user I/O buffer
#
CONFIG_USBHOST_OHCIRAM_SIZE=1536
CONFIG_USBHOST_OHCIRAM_SIZE=2048
CONFIG_USBHOST_NEDS=2
CONFIG_USBHOST_NTDS=2
CONFIG_USBHOST_TDBUFFERS=3

2
fs/fs_opendir.c
View File

@ -137,7 +137,6 @@ static inline int open_mountpoint(FAR struct inode *inode,
*
****************************************************************************/
#ifndef CONFIG_DISABLE_MOUNTPOINT
static void open_pseudodir(FAR struct inode *inode, FAR struct fs_dirent_s *dir)
{
/* We have a valid psuedo-filesystem node. Take two references on the
@ -155,7 +154,6 @@ static void open_pseudodir(FAR struct inode *inode, FAR struct fs_dirent_s *dir)
DIRENT_SETPSUEDONODE(dir->fd_flags);
#endif
}
#endif
/****************************************************************************
* Public Functions