Clean up Kinetics SDHC DMA code (still does not work)
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3909 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
81bb29ecd1
commit
057b237f81
@ -73,10 +73,6 @@
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/* Configuration ************************************************************/
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#if defined(CONFIG_SDIO_DMA) && !defined(CONFIG_KINETIS_DMA)
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# warning "CONFIG_SDIO_DMA support requires CONFIG_KINETIS_DMA"
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#endif
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#ifndef CONFIG_SDIO_DMA
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# warning "Large Non-DMA transfer may result in RX overrun failures"
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#endif
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@ -121,12 +117,10 @@
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# endif
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#endif
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/* Friendly SYSCTRL bit re-definitions ****************************************/
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/* Timing */
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#define SDHC_CMDTIMEOUT (100000)
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#define SDHC_LONGTIMEOUT (0x7fffffff)
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#define SDHC_CMDTIMEOUT (100000)
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#define SDHC_LONGTIMEOUT (0x7fffffff)
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/* Big DVS setting. Range is 0=SDCLK*213 through 14=SDCLK*227 */
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@ -137,13 +131,6 @@
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#define SDHC_MAX_WATERMARK 128
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/* DMA CCR register settings */
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#define SDHC_RXDMA32_CONFIG (CONFIG_KINETIS_SDHC_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
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DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC)
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#define SDHC_TXDMA32_CONFIG (CONFIG_KINETIS_SDHC_DMAPRIO|DMA_CCR_MSIZE_32BITS|\
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DMA_CCR_PSIZE_32BITS|DMA_CCR_MINC|DMA_CCR_DIR)
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/* Data transfer / Event waiting interrupt mask bits */
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#define SDHC_RESPERR_INTS (SDHC_INT_CCE|SDHC_INT_CTOE|SDHC_INT_CEBE|SDHC_INT_CIE)
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@ -159,28 +146,13 @@
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#define SDHC_WAITALL_INTS (SDHC_RESPDONE_INTS|SDHC_XFRDONE_INTS|SDHC_DMADONE_INTS)
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/* Let's wait until we have both SDIO transfer complete and DMA complete. */
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#define SDHC_XFRDONE_FLAG (1)
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#define SDHC_DMADONE_FLAG (2)
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#define SDHC_ALLDONE (3)
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/* Register logging support */
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#ifdef CONFIG_SDIO_XFRDEBUG
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# ifdef CONFIG_SDIO_DMA
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# define SAMPLENDX_BEFORE_SETUP 0
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# define SAMPLENDX_BEFORE_ENABLE 1
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# define SAMPLENDX_AFTER_SETUP 2
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# define SAMPLENDX_DMA_CALLBACK 3
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# define SAMPLENDX_END_TRANSFER 4
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# define DEBUG_NSAMPLES 5
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# else
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# define SAMPLENDX_BEFORE_SETUP 0
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# define SAMPLENDX_AFTER_SETUP 1
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# define SAMPLENDX_END_TRANSFER 2
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# define DEBUG_NSAMPLES 3
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# endif
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# define SAMPLENDX_BEFORE_SETUP 0
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# define SAMPLENDX_AFTER_SETUP 1
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# define SAMPLENDX_END_TRANSFER 2
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# define DEBUG_NSAMPLES 3
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#endif
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/****************************************************************************
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@ -220,8 +192,6 @@ struct kinetis_dev_s
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#ifdef CONFIG_SDIO_DMA
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volatile uint8_t xfrflags; /* Used to synchronize SDIO and DMA completion events */
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bool dmamode; /* true: DMA mode transfer */
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DMA_HANDLE dma; /* Handle for DMA channel */
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#endif
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};
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@ -255,14 +225,6 @@ struct kinetis_sdhcregs_s
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uint32_t mmcboot; /* MMC Boot Register */
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uint32_t hostver; /* Host Controller Version */
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};
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struct kinetis_sampleregs_s
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{
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struct kinetis_sdhcregs_s sdhc;
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#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
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struct kinetis_dmaregs_s dma;
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#endif
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};
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#endif
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/****************************************************************************
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@ -283,9 +245,8 @@ static void kinetis_configxfrints(struct kinetis_dev_s *priv, uint32_t xfrints);
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static void kinetis_sampleinit(void);
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static void kinetis_sdhcsample(struct kinetis_sdhcregs_s *regs);
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static void kinetis_sample(struct kinetis_dev_s *priv, int index);
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static void kinetis_sdhcdump(struct kinetis_sdhcregs_s *regs, const char *msg);
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static void kinetis_dumpsample(struct kinetis_dev_s *priv,
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struct kinetis_sampleregs_s *regs, const char *msg);
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struct kinetis_sdhcregs_s *regs, const char *msg);
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static void kinetis_dumpsamples(struct kinetis_dev_s *priv);
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static void kinetis_showregs(struct kinetis_dev_s *priv, const char *msg);
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#else
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@ -295,18 +256,16 @@ static void kinetis_showregs(struct kinetis_dev_s *priv, const char *msg);
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# define kinetis_showregs(priv,msg)
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#endif
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#ifdef CONFIG_SDIO_DMA
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static void kinetis_dmacallback(DMA_HANDLE handle, uint8_t isr, void *arg);
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#endif
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/* Data Transfer Helpers ****************************************************/
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static void kinetis_dataconfig(struct kinetis_dev_s *priv, bool bwrite,
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unsigned int blocksize, unsigned int nblocks,
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unsigned int timeout);
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static void kinetis_datadisable(void);
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#ifndef CONFIG_SDIO_DMA
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static void kinetis_transmit(struct kinetis_dev_s *priv);
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static void kinetis_receive(struct kinetis_dev_s *priv);
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#endif
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static void kinetis_eventtimeout(int argc, uint32_t arg);
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static void kinetis_endwait(struct kinetis_dev_s *priv, sdio_eventset_t wkupevent);
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static void kinetis_endtransfer(struct kinetis_dev_s *priv, sdio_eventset_t wkupevent);
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@ -339,10 +298,12 @@ static int kinetis_attach(FAR struct sdio_dev_s *dev);
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static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
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uint32_t arg);
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#ifndef CONFIG_SDIO_DMA
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static int kinetis_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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size_t nbytes);
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static int kinetis_sendsetup(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, uint32_t nbytes);
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#endif
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static int kinetis_cancel(FAR struct sdio_dev_s *dev);
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static int kinetis_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd);
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@ -397,8 +358,13 @@ struct kinetis_dev_s g_sdhcdev =
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.clock = kinetis_clock,
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.attach = kinetis_attach,
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.sendcmd = kinetis_sendcmd,
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#ifndef CONFIG_SDIO_DMA
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.recvsetup = kinetis_recvsetup,
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.sendsetup = kinetis_sendsetup,
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#else
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.recvsetup = kinetis_dmarecvsetup,
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.sendsetup = kinetis_dmasendsetup,
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#endif
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.cancel = kinetis_cancel,
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.waitresponse = kinetis_waitresponse,
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.recvR1 = kinetis_recvshortcrc,
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@ -423,7 +389,7 @@ struct kinetis_dev_s g_sdhcdev =
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/* Register logging support */
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#ifdef CONFIG_SDIO_XFRDEBUG
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static struct kinetis_sampleregs_s g_sampleregs[DEBUG_NSAMPLES];
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static struct kinetis_sdhcregs_s g_sampleregs[DEBUG_NSAMPLES];
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#endif
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/****************************************************************************
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@ -541,7 +507,7 @@ static void kinetis_configxfrints(struct kinetis_dev_s *priv, uint32_t xfrints)
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#ifdef CONFIG_SDIO_XFRDEBUG
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static void kinetis_sampleinit(void)
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{
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memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct kinetis_sampleregs_s));
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memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct kinetis_sdhcregs_s));
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}
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#endif
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@ -592,19 +558,12 @@ static void kinetis_sdhcsample(struct kinetis_sdhcregs_s *regs)
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#ifdef CONFIG_SDIO_XFRDEBUG
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static void kinetis_sample(struct kinetis_dev_s *priv, int index)
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{
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struct kinetis_sampleregs_s *regs = &g_sampleregs[index];
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#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
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if (priv->dmamode)
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{
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kinetis_dmasample(priv->dma, ®s->dma);
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}
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#endif
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kinetis_sdhcsample(®s->sdhc);
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kinetis_sdhcsample(&g_sampleregs[index]);
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}
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#endif
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/****************************************************************************
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* Name: kinetis_sdhcdump
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* Name: kinetis_dumpsample
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*
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* Description:
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* Dump one register sample
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@ -612,7 +571,8 @@ static void kinetis_sample(struct kinetis_dev_s *priv, int index)
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****************************************************************************/
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#ifdef CONFIG_SDIO_XFRDEBUG
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static void kinetis_sdhcdump(struct kinetis_sdhcregs_s *regs, const char *msg)
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static void kinetis_dumpsample(struct kinetis_dev_s *priv,
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struct kinetis_sdhcregs_s *regs, const char *msg)
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{
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fdbg("SDHC Registers: %s\n", msg);
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fdbg(" DSADDR[%08x]: %08x\n", KINETIS_SDHC_DSADDR, regs->dsaddr);
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@ -640,28 +600,6 @@ static void kinetis_sdhcdump(struct kinetis_sdhcregs_s *regs, const char *msg)
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}
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#endif
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/****************************************************************************
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* Name: kinetis_dumpsample
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*
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* Description:
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* Dump one register sample
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*
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****************************************************************************/
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#ifdef CONFIG_SDIO_XFRDEBUG
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static void kinetis_dumpsample(struct kinetis_dev_s *priv,
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struct kinetis_sampleregs_s *regs, const char *msg)
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{
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#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
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if (priv->dmamode)
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{
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kinetis_dmadump(priv->dma, ®s->dma, msg);
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}
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#endif
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kinetis_sdhcdump(®s->sdhc, msg);
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}
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#endif
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/****************************************************************************
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* Name: kinetis_dumpsamples
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*
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@ -674,19 +612,7 @@ static void kinetis_dumpsample(struct kinetis_dev_s *priv,
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static void kinetis_dumpsamples(struct kinetis_dev_s *priv)
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{
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kinetis_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup");
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#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
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if (priv->dmamode)
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{
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kinetis_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable");
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}
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#endif
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kinetis_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup");
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#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
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if (priv->dmamode)
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{
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kinetis_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback");
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}
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#endif
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kinetis_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer");
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}
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#endif
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@ -702,51 +628,13 @@ static void kinetis_dumpsamples(struct kinetis_dev_s *priv)
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#ifdef CONFIG_SDIO_XFRDEBUG
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static void kinetis_showregs(struct kinetis_dev_s *priv, const char *msg)
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{
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struct kinetis_sampleregs_s regs;
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struct kinetis_sdhcregs_s regs;
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#if defined(CONFIG_DEBUG_DMA) && defined(CONFIG_SDIO_DMA)
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if (priv->dmamode)
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{
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kinetis_dmasample(priv->dma, ®s.dma);
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}
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#endif
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kinetis_sdhcsample(®s.sdhc);
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kinetis_sdhcsample(®s);
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kinetis_dumpsample(priv, ®s, msg);
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}
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#endif
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/****************************************************************************
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* Name: kinetis_dmacallback
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*
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* Description:
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* Called when SDIO DMA completes
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*
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****************************************************************************/
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#ifdef CONFIG_SDIO_DMA
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static void kinetis_dmacallback(DMA_HANDLE handle, uint8_t isr, void *arg)
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{
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FAR struct kinetis_dev_s *priv = (FAR struct kinetis_dev_s *)arg;
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DEBUGASSERT(priv->dmamode);
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/* The SDIO appears to handle the End-Of-Transfer interrupt first with the
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* End-Of-DMA event occurring significantly later.
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*/
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kinetis_sample((struct kinetis_dev_s*)arg, SAMPLENDX_DMA_CALLBACK);
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/* Then terminate the transfer (we should already have the SDIO transfer
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* done interrupt. If not, the transfer will appropriately time out).
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*/
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priv->xfrflags |= SDHC_DMADONE_FLAG;
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if (priv->xfrflags == SDHC_ALLDONE)
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{
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kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
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}
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}
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#endif
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/****************************************************************************
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* Data Transfer Helpers
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****************************************************************************/
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@ -763,6 +651,7 @@ static void kinetis_dataconfig(struct kinetis_dev_s *priv, bool bwrite,
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unsigned int blocksize, unsigned int nblocks,
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unsigned int timeout)
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{
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unsigned int watermark;
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uint32_t regval = 0;
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/* Set the data timeout value in the SDHC_SYSCTL field to the selected value */
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@ -772,8 +661,8 @@ static void kinetis_dataconfig(struct kinetis_dev_s *priv, bool bwrite,
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regval |= timeout << SDHC_SYSCTL_DVS_SHIFT;
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putreg32(regval, KINETIS_SDHC_SYSCTL);
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/* Set the block size and count in the SDHC_BLKATTR register. The block size
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* is only valid for multiple block transfers.
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/* Set the block size and count in the SDHC_BLKATTR register. The block
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* size is only valid for multiple block transfers.
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*/
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regval = blocksize << SDHC_BLKATTR_SIZE_SHIFT |
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@ -783,41 +672,70 @@ static void kinetis_dataconfig(struct kinetis_dev_s *priv, bool bwrite,
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/* Set the watermark level */
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#ifdef CONFIG_SDIO_DMA
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if (priv->dma)
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/* Set the Read Watermark Level to the blocksize to be read
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* (limited to half of the maximum watermark value). BRR will be
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* set when the number of queued words is greater than or equal
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* to this value.
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*/
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watermark = (blocksize + 3) >> 2;
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if (watermark > (SDHC_MAX_WATERMARK / 2))
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{
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# warning "Missing logic"
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watermark = (SDHC_MAX_WATERMARK / 2);
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}
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else
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#endif
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/* When the watermark level requirement is met in data transfer, and the
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* internal DMA is enabled, the data buffer block sends a DMA request to
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* the crossbar switch interface.
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*/
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if (bwrite)
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{
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/* For now, treat the FIFO as though it had depth = 1. Set the
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* read/write watermarks as follows:
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/* The SDHC will not start data transmission until the number of
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* words set in the WML register can be held in the buffer. If the
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* buffer is empty and the host system does not write data in time,
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* the SDHC will stop the SD_CLK to avoid the data buffer under-run
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* situation.
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*/
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if (bwrite)
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{
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/* Write Watermark Level = 0: BWR will be set when the number of
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* queued words is less than or equal to 0.
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*/
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putreg32(0, KINETIS_SDHC_WML);
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}
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else
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{
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/* Set the Read Watermark Level to the blocksize to be read
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* (limited to half of the maximum watermark value). BRR will be
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* set when the number of queued words is greater than or equal
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* to this value.
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*/
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unsigned int watermark = (blocksize + 3) >> 2;
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if (watermark > (SDHC_MAX_WATERMARK / 2))
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{
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watermark = (SDHC_MAX_WATERMARK / 2);
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}
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putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML);
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}
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putreg32(watermark << SDHC_WML_WR_SHIFT, KINETIS_SDHC_WML);
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}
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else
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{
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/* The SDHC will not start data transmission until the number of
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* words set in the WML register are in the buffer. If the buffer
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* is full and the Host System does not read data in time, the
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* SDHC will stop the SDHC_DCLK to avoid the data buffer over-run
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* situation.
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*/
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putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML);
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}
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#else
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if (bwrite)
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{
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/* Write Watermark Level = 0: BWR will be set when the number of
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* queued words is less than or equal to 0.
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*/
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putreg32(0, KINETIS_SDHC_WML);
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}
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else
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{
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/* Set the Read Watermark Level to the blocksize to be read
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* (limited to half of the maximum watermark value). BRR will be
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* set when the number of queued words is greater than or equal
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* to this value.
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*/
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watermark = (blocksize + 3) >> 2;
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if (watermark > (SDHC_MAX_WATERMARK / 2))
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{
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watermark = (SDHC_MAX_WATERMARK / 2);
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}
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putreg32(watermark << SDHC_WML_RD_SHIFT, KINETIS_SDHC_WML);
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}
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#endif
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}
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/****************************************************************************
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@ -859,6 +777,7 @@ static void kinetis_datadisable(void)
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*
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****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SDIO_DMA
|
||||
static void kinetis_transmit(struct kinetis_dev_s *priv)
|
||||
{
|
||||
union
|
||||
@ -921,6 +840,7 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
|
||||
priv->remaining, getreg32(KINETIS_SDHC_IRQSTAT));
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_receive
|
||||
@ -936,6 +856,7 @@ static void kinetis_transmit(struct kinetis_dev_s *priv)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SDIO_DMA
|
||||
static void kinetis_receive(struct kinetis_dev_s *priv)
|
||||
{
|
||||
unsigned int watermark;
|
||||
@ -1011,6 +932,7 @@ static void kinetis_receive(struct kinetis_dev_s *priv)
|
||||
getreg32(KINETIS_SDHC_WML));
|
||||
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_eventtimeout
|
||||
@ -1108,6 +1030,10 @@ static void kinetis_endwait(struct kinetis_dev_s *priv, sdio_eventset_t wkupeven
|
||||
|
||||
static void kinetis_endtransfer(struct kinetis_dev_s *priv, sdio_eventset_t wkupevent)
|
||||
{
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
uint32_t regval;
|
||||
#endif
|
||||
|
||||
/* Disable all transfer related interrupts */
|
||||
|
||||
kinetis_configxfrints(priv, 0);
|
||||
@ -1119,15 +1045,11 @@ static void kinetis_endtransfer(struct kinetis_dev_s *priv, sdio_eventset_t wkup
|
||||
/* If this was a DMA transfer, make sure that DMA is stopped */
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
if (priv->dmamode)
|
||||
{
|
||||
/* Make sure that the DMA is stopped (it will be stopped automatically
|
||||
* on normal transfers, but not necessarily when the transfer terminates
|
||||
* on an error condition).
|
||||
*/
|
||||
/* Stop the DMA by resetting the data path*/
|
||||
|
||||
kinetis_dmastop(priv->dma);
|
||||
}
|
||||
regval = getreg32(KINETIS_SDHC_SYSCTL);
|
||||
regval |= SDHC_SYSCTL_RSTD;
|
||||
putreg32(regval, KINETIS_SDHC_SYSCTL);
|
||||
#endif
|
||||
|
||||
/* Mark the transfer finished */
|
||||
@ -1193,78 +1115,43 @@ static int kinetis_interrupt(int irq, void *context)
|
||||
|
||||
putreg32(enabled, KINETIS_SDHC_IRQSTAT);
|
||||
|
||||
/* Handle in progress, interrupt driven data transfers ****************/
|
||||
/* Handle in progress, interrupt driven data transfers ********************/
|
||||
|
||||
pending = enabled & priv->xfrints;
|
||||
if (pending != 0)
|
||||
{
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
if (!priv->dmamode)
|
||||
#endif
|
||||
#ifndef CONFIG_SDIO_DMA
|
||||
/* Is the RX buffer read ready? Is so then we must be processing a
|
||||
* non-DMA receive transaction.
|
||||
*/
|
||||
|
||||
if ((pending & SDHC_INT_BRR) != 0)
|
||||
{
|
||||
/* Is the RX buffer read ready? Is so then we must be
|
||||
* processing a receive transaction.
|
||||
*/
|
||||
/* Receive data from the RX buffer */
|
||||
|
||||
if ((pending & SDHC_INT_BRR) != 0)
|
||||
{
|
||||
/* Receive data from the RX buffer */
|
||||
|
||||
kinetis_receive(priv);
|
||||
}
|
||||
|
||||
/* Otherwise, Is the TX buffer write ready? If so we must
|
||||
* be processing a send transaction. NOTE: We can't be
|
||||
* processing both!
|
||||
*/
|
||||
|
||||
else if ((pending & SDHC_INT_BWR) != 0)
|
||||
{
|
||||
/* Send data via the TX FIFO */
|
||||
|
||||
kinetis_transmit(priv);
|
||||
}
|
||||
kinetis_receive(priv);
|
||||
}
|
||||
|
||||
/* Otherwise, Is the TX buffer write ready? If so we must
|
||||
* be processing a non-DMA send transaction. NOTE: We can't be
|
||||
* processing both!
|
||||
*/
|
||||
|
||||
else if ((pending & SDHC_INT_BWR) != 0)
|
||||
{
|
||||
/* Send data via the TX FIFO */
|
||||
|
||||
kinetis_transmit(priv);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Handle transfer complete events */
|
||||
|
||||
if ((pending & SDHC_INT_TC) != 0)
|
||||
{
|
||||
/* Was this transfer performed in DMA mode? */
|
||||
/* Terminate the transfer */
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
if (priv->dmamode)
|
||||
{
|
||||
/* Yes.. Terminate the transfers only if the DMA has also
|
||||
* finished.
|
||||
*/
|
||||
|
||||
priv->xfrflags |= SDHC_XFRDONE_FLAG;
|
||||
if (priv->xfrflags == SDHC_ALLDONE)
|
||||
{
|
||||
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
|
||||
}
|
||||
|
||||
/* Otherwise, just disable futher transfer interrupts and
|
||||
* wait for the DMA complete event.
|
||||
*/
|
||||
|
||||
else
|
||||
{
|
||||
kinetis_configxfrints(priv, 0);
|
||||
}
|
||||
}
|
||||
else
|
||||
#endif
|
||||
{
|
||||
/* Receive any additional data from the RX FIFO */
|
||||
|
||||
kinetis_receive(priv);
|
||||
|
||||
/* Then terminate the transfer */
|
||||
|
||||
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
|
||||
}
|
||||
kinetis_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
|
||||
}
|
||||
|
||||
/* Handle data block send/receive CRC failure */
|
||||
@ -1288,7 +1175,7 @@ static int kinetis_interrupt(int irq, void *context)
|
||||
}
|
||||
}
|
||||
|
||||
/* Handle wait events *************************************************/
|
||||
/* Handle wait events *****************************************************/
|
||||
|
||||
pending = enabled & priv->waitints;
|
||||
if (pending != 0)
|
||||
@ -1425,12 +1312,6 @@ static void kinetis_reset(FAR struct sdio_dev_s *dev)
|
||||
priv->buffer = 0; /* Address of current R/W buffer */
|
||||
priv->remaining = 0; /* Number of bytes remaining in the transfer */
|
||||
priv->xfrints = 0; /* Interrupt enables for data transfer */
|
||||
|
||||
/* DMA data transfer support */
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
priv->dmamode = false; /* true: DMA mode transfer */
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -1858,13 +1739,13 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
|
||||
case MMCSD_NODATAXFR : /* No.. no data transfer */
|
||||
break;
|
||||
|
||||
/* The following two cases are probably missing some setup logic */
|
||||
|
||||
case MMCSD_RDSTREAM : /* Yes.. streaming read data transfer */
|
||||
#warning "Probably some missing setup"
|
||||
regval |= (SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DTDSEL);
|
||||
break;
|
||||
|
||||
case MMCSD_WRSTREAM : /* Yes.. streaming write data transfer */
|
||||
#warning "Probably some missing setup"
|
||||
regval |= SDHC_XFERTYP_DPSEL;
|
||||
break;
|
||||
|
||||
@ -1930,18 +1811,13 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
|
||||
/* Enable DMA */
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
if (priv->dmamode)
|
||||
{
|
||||
/* Internal DMA is used */
|
||||
/* Internal DMA is used */
|
||||
|
||||
regval |= SDHC_XFERTYP_DMAEN;
|
||||
}
|
||||
regval |= SDHC_XFERTYP_DMAEN;
|
||||
#endif
|
||||
|
||||
/* Other bits? What about CMDTYP? */
|
||||
|
||||
#warning "Revisit"
|
||||
|
||||
fvdbg("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval);
|
||||
|
||||
/* The Command Inhibit (CIHB) bit is set in the PRSSTAT bit immediately
|
||||
@ -1997,6 +1873,7 @@ static int kinetis_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t ar
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SDIO_DMA
|
||||
static int kinetis_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
size_t nbytes)
|
||||
{
|
||||
@ -2015,9 +1892,6 @@ static int kinetis_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
|
||||
priv->buffer = (uint32_t*)buffer;
|
||||
priv->remaining = nbytes;
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
priv->dmamode = false;
|
||||
#endif
|
||||
|
||||
/* Then set up the SDIO data path */
|
||||
|
||||
@ -2029,6 +1903,7 @@ static int kinetis_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
kinetis_sample(priv, SAMPLENDX_AFTER_SETUP);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_sendsetup
|
||||
@ -2049,6 +1924,7 @@ static int kinetis_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SDIO_DMA
|
||||
static int kinetis_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer,
|
||||
size_t nbytes)
|
||||
{
|
||||
@ -2067,9 +1943,6 @@ static int kinetis_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buff
|
||||
|
||||
priv->buffer = (uint32_t*)buffer;
|
||||
priv->remaining = nbytes;
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
priv->dmamode = false;
|
||||
#endif
|
||||
|
||||
/* Then set up the SDIO data path */
|
||||
|
||||
@ -2081,6 +1954,7 @@ static int kinetis_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buff
|
||||
kinetis_sample(priv, SAMPLENDX_AFTER_SETUP);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: kinetis_cancel
|
||||
@ -2102,6 +1976,9 @@ static int kinetis_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buff
|
||||
static int kinetis_cancel(FAR struct sdio_dev_s *dev)
|
||||
{
|
||||
struct kinetis_dev_s *priv = (struct kinetis_dev_s*)dev;
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
uint32_t regval;
|
||||
#endif
|
||||
|
||||
/* Disable all transfer- and event- related interrupts */
|
||||
|
||||
@ -2121,15 +1998,11 @@ static int kinetis_cancel(FAR struct sdio_dev_s *dev)
|
||||
/* If this was a DMA transfer, make sure that DMA is stopped */
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
if (priv->dmamode)
|
||||
{
|
||||
/* Make sure that the DMA is stopped (it will be stopped automatically
|
||||
* on normal transfers, but not necessarily when the transfer terminates
|
||||
* on an error condition.
|
||||
*/
|
||||
/* Stop the DMA by resetting the data path*/
|
||||
|
||||
kinetis_dmastop(priv->dma);
|
||||
}
|
||||
regval = getreg32(KINETIS_SDHC_SYSCTL);
|
||||
regval |= SDHC_SYSCTL_RSTD;
|
||||
putreg32(regval, KINETIS_SDHC_SYSCTL);
|
||||
#endif
|
||||
|
||||
/* Mark no transfer in progress */
|
||||
@ -2696,7 +2569,6 @@ static int kinetis_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
size_t buflen)
|
||||
{
|
||||
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev;
|
||||
uint32_t blocksize;
|
||||
|
||||
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
|
||||
DEBUGASSERT(((uint32_t)buffer & 3) == 0);
|
||||
@ -2714,7 +2586,6 @@ static int kinetis_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
|
||||
priv->buffer = (uint32_t*)buffer;
|
||||
priv->remaining = buflen;
|
||||
priv->dmamode = true;
|
||||
|
||||
/* Then set up the SDIO data path */
|
||||
|
||||
@ -2723,15 +2594,10 @@ static int kinetis_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
|
||||
/* Configure the RX DMA */
|
||||
|
||||
kinetis_configxfrints(priv, SDHC_DMADONE_INTS);
|
||||
|
||||
putreg32(1, SDHC_DCTRL_DMAEN_BB);
|
||||
kinetis_dmasetup(priv->dma, KINETIS_SDHC_FIFO, (uint32_t)buffer,
|
||||
(buflen + 3) >> 2, SDHC_RXDMA32_CONFIG);
|
||||
putreg32((uint32_t)buffer, KINETIS_SDHC_DSADDR);
|
||||
|
||||
/* Start the DMA */
|
||||
/* Sample the register state */
|
||||
|
||||
kinetis_sample(priv, SAMPLENDX_BEFORE_ENABLE);
|
||||
kinetis_dmastart(priv->dma, kinetis_dmacallback, priv, false);
|
||||
kinetis_sample(priv, SAMPLENDX_AFTER_SETUP);
|
||||
return OK;
|
||||
}
|
||||
@ -2761,7 +2627,6 @@ static int kinetis_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
FAR const uint8_t *buffer, size_t buflen)
|
||||
{
|
||||
struct kinetis_dev_s *priv = (struct kinetis_dev_s *)dev;
|
||||
uint32_t blocksize;
|
||||
|
||||
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
|
||||
DEBUGASSERT(((uint32_t)buffer & 3) == 0);
|
||||
@ -2779,7 +2644,6 @@ static int kinetis_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
|
||||
priv->buffer = (uint32_t*)buffer;
|
||||
priv->remaining = buflen;
|
||||
priv->dmamode = true;
|
||||
|
||||
/* Then set up the SDIO data path */
|
||||
|
||||
@ -2787,15 +2651,10 @@ static int kinetis_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
|
||||
/* Configure the TX DMA */
|
||||
|
||||
kinetis_dmasetup(priv->dma, KINETIS_SDHC_FIFO, (uint32_t)buffer,
|
||||
(buflen + 3) >> 2, SDHC_TXDMA32_CONFIG);
|
||||
putreg32((uint32_t)buffer, KINETIS_SDHC_DSADDR);
|
||||
|
||||
kinetis_sample(priv, SAMPLENDX_BEFORE_ENABLE);
|
||||
putreg32(1, SDHC_DCTRL_DMAEN_BB);
|
||||
/* Sample the register state */
|
||||
|
||||
/* Start the DMA */
|
||||
|
||||
kinetis_dmastart(priv->dma, kinetis_dmacallback, priv, false);
|
||||
kinetis_sample(priv, SAMPLENDX_AFTER_SETUP);
|
||||
|
||||
/* Enable TX interrrupts */
|
||||
@ -2919,12 +2778,6 @@ FAR struct sdio_dev_s *sdhc_initialize(int slotno)
|
||||
priv->waitwdog = wd_create();
|
||||
DEBUGASSERT(priv->waitwdog);
|
||||
|
||||
/* Allocate a DMA channel */
|
||||
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
priv->dma = kinetis_dmachannel(DMACHAN_SDHC);
|
||||
#endif
|
||||
|
||||
/* Enable clocking to the SDHC module. Clocking is still diabled in
|
||||
* the SYSCTRL register.
|
||||
*/
|
||||
|
||||
@ -109,10 +109,19 @@
|
||||
#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
|
||||
/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) */
|
||||
/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) (with DMA)
|
||||
* SD normal mode (4-bit): 16MHz = 96MHz / (2 * 3) (no DMA)
|
||||
*/
|
||||
|
||||
#define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2)
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2)
|
||||
#else
|
||||
//# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
//# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
|
||||
# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
|
||||
#endif
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
/* The KwikStik-K40 board has no MCU driven, GPIO-based LEDs */
|
||||
|
||||
@ -97,23 +97,32 @@
|
||||
|
||||
/* Identification mode: 400KHz = 96MHz / ( 16 * 15) */
|
||||
|
||||
#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
|
||||
#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
|
||||
#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
|
||||
#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
|
||||
|
||||
/* MMC normal mode: 16MHz = 96MHz / (2 * 3) */
|
||||
|
||||
#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
|
||||
/* SD normal mode (1-bit): 16MHz = 96MHz / (2 * 3) */
|
||||
|
||||
#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
|
||||
/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) */
|
||||
/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) (with DMA)
|
||||
* SD normal mode (4-bit): 16MHz = 96MHz / (2 * 3) (no DMA)
|
||||
*/
|
||||
|
||||
#define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
#define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2)
|
||||
#ifdef CONFIG_SDIO_DMA
|
||||
# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2)
|
||||
#else
|
||||
//# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2
|
||||
//# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3)
|
||||
# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16
|
||||
# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15)
|
||||
#endif
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
/* The TWR-K60N512 has four LEDs:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user