armv7-a/r: NON-primary core should invalidate dacache level1
NON-primary cpu will invalidate cpu0's cache L2, that will caused cpu0's data mismatch, and then system crash Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit is contained in:
ligd
Xiang Xiao
parent
a1ebd499ea
commit
059497d1d1
@ -90,7 +90,7 @@ void arm_enable_smp(int cpu)
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* coherent L2.
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* coherent L2.
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*/
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*/
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cp15_invalidate_dcache_all();
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cp15_dcache_op_level(0, CP15_CACHE_INVALIDATE);
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ARM_DSB();
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ARM_DSB();
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/* Wait for the SCU to be enabled by the primary processor -- should
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/* Wait for the SCU to be enabled by the primary processor -- should
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@ -28,14 +28,6 @@
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#include "cp15_cacheops.h"
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#include "cp15_cacheops.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CP15_CACHE_INVALIDATE 0
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#define CP15_CACHE_CLEAN 1
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#define CP15_CACHE_CLEANINVALIDATE 2
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/****************************************************************************
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/****************************************************************************
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* Private Functions
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* Private Functions
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****************************************************************************/
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****************************************************************************/
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@ -69,70 +61,6 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
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return (1 << ((ccsidr & 0x7) + 2)) * 4;
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return (1 << ((ccsidr & 0x7) + 2)) * 4;
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}
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}
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static void cp15_dcache_op_level(uint32_t level, int op)
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{
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uint32_t sets;
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uint32_t ways;
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uint32_t set;
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uint32_t way;
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uint32_t line;
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uint32_t way_shift;
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uint32_t set_shift;
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uint32_t val = level << 1;
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/* Select by CSSELR */
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CP15_SET(CSSELR, val);
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/* Get cache info */
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line = cp15_cache_get_info(&sets, &ways);
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way_shift = 32 - ilog2(ways);
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set_shift = ilog2(line);
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ARM_DSB();
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/* A: Log2(ways)
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* B: L+S
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* L: Log2(line)
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* S: Log2(sets)
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*
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* The bits are packed as follows:
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* 31 31-A B B-1 L L-1 4 3 1 0
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* |---|-------------|--------|-------|-----|-|
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* |Way| zeros | Set | zeros |level|0|
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* |---|-------------|--------|-------|-----|-|
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*/
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for (way = 0; way < ways; way++)
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{
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for (set = 0; set < sets; set++)
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{
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val = level << 1;
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val |= way << way_shift;
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val |= set << set_shift;
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switch (op)
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{
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case CP15_CACHE_INVALIDATE:
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cp15_invalidate_dcacheline_bysetway(val);
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break;
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case CP15_CACHE_CLEAN:
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cp15_clean_dcache_bysetway(val);
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break;
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case CP15_CACHE_CLEANINVALIDATE:
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cp15_cleaninvalidate_dcacheline(val);
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break;
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default:
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break;
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}
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}
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}
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ARM_ISB();
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}
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static void cp15_dcache_op(int op)
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static void cp15_dcache_op(int op)
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{
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{
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uint32_t clidr = CP15_GET(CLIDR);
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uint32_t clidr = CP15_GET(CLIDR);
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@ -197,6 +125,70 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
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* Public Functions
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* Public Functions
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****************************************************************************/
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****************************************************************************/
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void cp15_dcache_op_level(uint32_t level, int op)
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{
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uint32_t sets;
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uint32_t ways;
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uint32_t set;
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uint32_t way;
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uint32_t line;
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uint32_t way_shift;
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uint32_t set_shift;
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uint32_t val = level << 1;
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/* Select by CSSELR */
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CP15_SET(CSSELR, val);
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/* Get cache info */
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line = cp15_cache_get_info(&sets, &ways);
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way_shift = 32 - ilog2(ways);
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set_shift = ilog2(line);
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ARM_DSB();
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/* A: Log2(ways)
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* B: L+S
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* L: Log2(line)
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* S: Log2(sets)
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*
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* The bits are packed as follows:
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* 31 31-A B B-1 L L-1 4 3 1 0
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* |---|-------------|--------|-------|-----|-|
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* |Way| zeros | Set | zeros |level|0|
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* |---|-------------|--------|-------|-----|-|
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*/
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for (way = 0; way < ways; way++)
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{
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for (set = 0; set < sets; set++)
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{
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val = level << 1;
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val |= way << way_shift;
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val |= set << set_shift;
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switch (op)
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{
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case CP15_CACHE_INVALIDATE:
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cp15_invalidate_dcacheline_bysetway(val);
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break;
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case CP15_CACHE_CLEAN:
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cp15_clean_dcache_bysetway(val);
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break;
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case CP15_CACHE_CLEANINVALIDATE:
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cp15_cleaninvalidate_dcacheline(val);
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break;
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default:
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break;
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}
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}
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}
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ARM_ISB();
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}
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void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
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void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
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{
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{
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cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
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cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
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@ -63,6 +63,10 @@
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/* Cache definitions ********************************************************/
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/* Cache definitions ********************************************************/
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#define CP15_CACHE_INVALIDATE 0
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#define CP15_CACHE_CLEAN 1
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#define CP15_CACHE_CLEANINVALIDATE 2
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/* L1 Memory */
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/* L1 Memory */
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#define CP15_L1_LINESIZE 32
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#define CP15_L1_LINESIZE 32
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@ -898,6 +902,23 @@ extern "C"
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* Public Function Prototypes
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* Public Function Prototypes
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****************************************************************************/
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****************************************************************************/
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/****************************************************************************
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* Name: cp15_dcache_op_level
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*
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* Description:
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* Dcache operation from level
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*
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* Input Parameters:
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* level - cache level
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* op - CP15_CACHE_XX
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void cp15_dcache_op_level(uint32_t level, int op);
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/****************************************************************************
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/****************************************************************************
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* Name: cp15_coherent_dcache
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* Name: cp15_coherent_dcache
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*
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*
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@ -28,14 +28,6 @@
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#include "cp15_cacheops.h"
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#include "cp15_cacheops.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#define CP15_CACHE_INVALIDATE 0
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#define CP15_CACHE_CLEAN 1
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#define CP15_CACHE_CLEANINVALIDATE 2
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/****************************************************************************
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/****************************************************************************
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* Private Functions
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* Private Functions
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****************************************************************************/
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****************************************************************************/
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@ -69,70 +61,6 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
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return (1 << ((ccsidr & 0x7) + 2)) * 4;
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return (1 << ((ccsidr & 0x7) + 2)) * 4;
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}
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}
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static void cp15_dcache_op_level(uint32_t level, int op)
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{
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uint32_t sets;
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uint32_t ways;
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uint32_t set;
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uint32_t way;
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uint32_t line;
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uint32_t way_shift;
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uint32_t set_shift;
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uint32_t val = level << 1;
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/* Select by CSSELR */
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CP15_SET(CSSELR, val);
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/* Get cache info */
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line = cp15_cache_get_info(&sets, &ways);
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way_shift = 32 - ilog2(ways);
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set_shift = ilog2(line);
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ARM_DSB();
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/* A: Log2(ways)
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* B: L+S
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* L: Log2(line)
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* S: Log2(sets)
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*
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* The bits are packed as follows:
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* 31 31-A B B-1 L L-1 4 3 1 0
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* |---|-------------|--------|-------|-----|-|
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* |Way| zeros | Set | zeros |level|0|
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* |---|-------------|--------|-------|-----|-|
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*/
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for (way = 0; way < ways; way++)
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{
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for (set = 0; set < sets; set++)
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{
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val = level << 1;
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val |= way << way_shift;
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val |= set << set_shift;
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switch (op)
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{
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case CP15_CACHE_INVALIDATE:
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cp15_invalidate_dcacheline_bysetway(val);
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break;
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case CP15_CACHE_CLEAN:
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cp15_clean_dcache_bysetway(val);
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break;
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case CP15_CACHE_CLEANINVALIDATE:
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cp15_cleaninvalidate_dcacheline(val);
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break;
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default:
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break;
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}
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}
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}
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ARM_ISB();
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}
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static void cp15_dcache_op(int op)
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static void cp15_dcache_op(int op)
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{
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{
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uint32_t clidr = CP15_GET(CLIDR);
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uint32_t clidr = CP15_GET(CLIDR);
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@ -197,6 +125,70 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
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* Public Functions
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* Public Functions
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****************************************************************************/
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****************************************************************************/
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void cp15_dcache_op_level(uint32_t level, int op)
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{
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uint32_t sets;
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uint32_t ways;
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uint32_t set;
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uint32_t way;
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uint32_t line;
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uint32_t way_shift;
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uint32_t set_shift;
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uint32_t val = level << 1;
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/* Select by CSSELR */
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CP15_SET(CSSELR, val);
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/* Get cache info */
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line = cp15_cache_get_info(&sets, &ways);
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way_shift = 32 - ilog2(ways);
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set_shift = ilog2(line);
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ARM_DSB();
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/* A: Log2(ways)
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* B: L+S
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* L: Log2(line)
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* S: Log2(sets)
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*
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* The bits are packed as follows:
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* 31 31-A B B-1 L L-1 4 3 1 0
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* |---|-------------|--------|-------|-----|-|
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* |Way| zeros | Set | zeros |level|0|
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* |---|-------------|--------|-------|-----|-|
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*/
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for (way = 0; way < ways; way++)
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{
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for (set = 0; set < sets; set++)
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{
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val = level << 1;
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val |= way << way_shift;
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val |= set << set_shift;
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switch (op)
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{
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case CP15_CACHE_INVALIDATE:
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cp15_invalidate_dcacheline_bysetway(val);
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break;
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case CP15_CACHE_CLEAN:
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cp15_clean_dcache_bysetway(val);
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break;
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case CP15_CACHE_CLEANINVALIDATE:
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cp15_cleaninvalidate_dcacheline(val);
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break;
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default:
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break;
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}
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}
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}
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ARM_ISB();
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}
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void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
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void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
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{
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{
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cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
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cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
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@ -61,6 +61,10 @@
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/* Cache definitions ********************************************************/
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/* Cache definitions ********************************************************/
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#define CP15_CACHE_INVALIDATE 0
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#define CP15_CACHE_CLEAN 1
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#define CP15_CACHE_CLEANINVALIDATE 2
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/* L1 Memory */
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/* L1 Memory */
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#define CP15_L1_LINESIZE 32
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#define CP15_L1_LINESIZE 32
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@ -905,6 +909,23 @@ extern "C"
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* Public Function Prototypes
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* Public Function Prototypes
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****************************************************************************/
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****************************************************************************/
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/****************************************************************************
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* Name: cp15_dcache_op_level
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*
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* Description:
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* Dcache operation from level
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*
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* Input Parameters:
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* level - cache level
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* op - CP15_CACHE_XX
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void cp15_dcache_op_level(uint32_t level, int op);
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/****************************************************************************
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/****************************************************************************
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* Name: cp15_coherent_dcache
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* Name: cp15_coherent_dcache
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*
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*
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