sergiotarxz/nuttx
sergiotarxz/nuttx
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merge upstream

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This commit is contained in:
pnb 2015-11-02 21:47:13 +01:00
commit 059fc85201
111 changed files with 3961 additions and 835 deletions
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78
arch/arm/include/lpc43xx/chip.h
View File

@ -78,33 +78,33 @@
/* Get customizations for each supported chip.
*
* SRAM Resources
* --------------------- -------- ------- ------- ------- ------- -------
* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb
* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb
* --------------------- -------- ------- ------- ------- ------- -------
* SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb
* --------------------- -------- ------- ------- ------- ------- -------
* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb
* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1
* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb
* --------------------- -------- ------- ------- ------- ------- -------
* SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb
* --------------------- -------- ------- ------- ------- ------- -------
* TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb
* --------------------- -------- ------- ------- ------- ------- -------
* --------------------- -------- ------- ------- ------- ------- ------- -------
* Local SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK 0 (0x1000 0000) 96Kb 96Kb 128Kb 128Kb 32Kb 32Kb 32Kb
* BANK 1 (0x1008 0000) 40Kb 40Kb 72Kb 72Kb 40Kb 40Kb 40Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* SUBTOTAL 136Kb 136Kb 200Kb 200Kb 72Kb 72Kb 72Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* AHB SRAM LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK 0 (0x2000 0000) 16Kb 48Kb 48Kb 48Kb 48Kb 48Kb 48Kb
* BANK 1 (0x2000 8000) NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1 NOTE 1
* BANK 2 (0x2000 c000) 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb 16Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* SUBTOTAL 32Kb 64Kb 64Kb 64Kb 64Kb 64Kb 64Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* TOTAL 168Kb 200Kb 264Kb 264Kb 136Kb 136Kb 136Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
*
* --------------------- -------- ------- ------- ------- ------- -------
* FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357
* --------------------- -------- ------- ------- ------- ------- -------
* BANK A (0x1a00 0000) 256Kb 512Kb
* BANK B (0x1b00 8000) 256Kb 512Kb
* --------------------- -------- ------- ------- ------- ------- -------
* TOTAL None None None None 512Kb 1024Kb
* --------------------- -------- ------- ------- ------- ------- -------
* --------------------- -------- ------- ------- ------- ------- ------- -------
* FLASH LPC4310 LPC4320 LPC4330 LPC4350 LPC4353 LPC4357 LPC4337
* --------------------- -------- ------- ------- ------- ------- ------- -------
* BANK A (0x1a00 0000) 256Kb 512Kb 512Kb
* BANK B (0x1b00 8000) 256Kb 512Kb 512Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
* TOTAL None None None None 512Kb 1024Kb 1024Kb
* --------------------- -------- ------- ------- ------- ------- ------- -------
*
* NOTE 1: The 64Kb of AHB of SRAM on the LPC4350/30/20 span all AHB SRAM
* banks but are treated as two banks of 48 an 16Kb by the NuttX memory
@ -321,6 +321,32 @@
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
# define LPC43_FLASH_BANKA_SIZE (512*1025) /* 1024Kb FLASH */
# define LPC43_FLASH_BANKB_SIZE (512*1025)
# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM*/
# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
# define LPC43_AHBSRAM_BANK1_SIZE (0)
# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
# define LPC43_NLCD (0) /* Has LCD controller */
# define LPC43_ETHERNET (1) /* One Ethernet controller */
# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
# define LPC43_USB1_ULPI (0) /* Have USB1 (Host, Device) with ULPI I/F */
# define LPC43_MCPWM (1) /* One PWM interface */
# define LPC43_QEI (0) /* One Quadrature Encoder interface */
# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
# define LPC43_NSSP (2) /* Two SSP controllers */
# define LPC43_NTIMERS (4) /* Four Timers */
# define LPC43_NI2C (2) /* Two I2C controllers */
# define LPC43_NI2S (2) /* Two I2S controllers */
# define LPC43_NCAN (2) /* Two CAN controllers */
# define LPC43_NDAC (1) /* One 10-bit DAC */
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)

6
arch/arm/src/arm/up_assert.c
View File

@ -316,9 +316,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -343,7 +343,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/arm/up_doirq.c
View File

@ -74,7 +74,7 @@
void up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -130,5 +130,5 @@ void up_doirq(int irq, uint32_t *regs)
current_regs = NULL;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
}

2
arch/arm/src/arm/up_nommuhead.S
View File

@ -125,7 +125,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
#ifdef CONFIG_STACK_COLORATION

4
arch/arm/src/arm/up_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -132,7 +132,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

6
arch/arm/src/armv6-m/up_assert.c
View File

@ -371,9 +371,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -398,7 +398,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv6-m/up_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

4
arch/arm/src/armv6-m/up_sigdeliver.c
View File

@ -98,7 +98,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -143,7 +143,7 @@ void up_sigdeliver(void)
* execution.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

6
arch/arm/src/armv7-a/arm_assert.c
View File

@ -371,9 +371,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -397,7 +397,7 @@ void up_assert(const uint8_t *filename, int lineno)
#ifdef CONFIG_PRINT_TASKNAME
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv7-a/arm_doirq.c
View File

@ -74,7 +74,7 @@
uint32_t *arm_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -128,6 +128,6 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
current_regs = NULL;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

4
arch/arm/src/armv7-a/arm_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -132,7 +132,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

6
arch/arm/src/armv7-m/up_assert.c
View File

@ -380,9 +380,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -407,7 +407,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/arm/src/armv7-m/up_doirq.c
View File

@ -72,7 +72,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -116,6 +116,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = savestate;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

4
arch/arm/src/armv7-m/up_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -146,7 +146,7 @@ void up_sigdeliver(void)
* execution.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

4
arch/arm/src/common/up_allocateheap.c
View File

@ -142,14 +142,14 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
#else
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

2
arch/arm/src/common/up_createstack.c
View File

@ -227,7 +227,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
up_stack_color(tcb->stack_alloc_ptr, tcb->adj_stack_size);
#endif
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

2
arch/arm/src/common/up_initialize.c
View File

@ -275,5 +275,5 @@ void up_initialize(void)
/* Initialize the L2 cache if present and selected */
up_l2ccinitialize();
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}

2
arch/arm/src/dm320/dm320_allocateheap.c
View File

@ -85,7 +85,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = (DM320_SDRAM_VADDR + CONFIG_RAM_SIZE) - g_idle_topstack;
}

3
arch/arm/src/dm320/dm320_boot.c
View File

@ -225,8 +225,9 @@ void up_boot(void)
/* Set up the board-specific LEDs */
#ifdef CONFIG_ARCH_LEDS
board_led_initialize();
board_autoled_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT

4
arch/arm/src/efm32/efm32_idle.c
View File

@ -61,8 +61,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

2
arch/arm/src/imx/imx_allocateheap.c
View File

@ -85,7 +85,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = (IMX_SDRAM_VSECTION + CONFIG_RAM_SIZE) - g_idle_topstack;
}

3
arch/arm/src/imx/imx_boot.c
View File

@ -216,8 +216,9 @@ void up_boot(void)
/* Set up the board-specific LEDs */
#ifdef CONFIG_ARCH_LEDS
board_led_initialize();
board_autoled_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT

4
arch/arm/src/kinetis/kinetis_allocateheap.c
View File

@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/kinetis/kinetis_idle.c
View File

@ -54,8 +54,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/kl/kl_idle.c
View File

@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/lpc11xx/lpc11_idle.c
View File

@ -53,8 +53,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/lpc17xx/lpc17_allocateheap.c
View File

@ -249,7 +249,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -260,7 +260,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/lpc17xx/lpc17_idle.c
View File

@ -55,8 +55,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

2
arch/arm/src/lpc214x/lpc214x_head.S
View File

@ -592,7 +592,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
/* Then jump to OS entry */

2
arch/arm/src/lpc2378/lpc23xx_head.S
View File

@ -193,7 +193,7 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
/* Then jump to OS entry */

2
arch/arm/src/lpc31xx/lpc31_allocateheap.c
View File

@ -180,7 +180,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = LPC31_HEAP_VEND - g_idle_topstack;
}

8
arch/arm/src/lpc43xx/Kconfig
View File

@ -34,6 +34,9 @@ config ARCH_CHIP_LPC4330FET180
config ARCH_CHIP_LPC4330FET256
bool "LPC4330FET256"
config ARCH_CHIP_LPC4337JBD144
bool "LPC4337JBD144"
config ARCH_CHIP_LPC4350FBD208
bool "LPC4350FBD208"
@ -81,6 +84,11 @@ config ARCH_FAMILY_LPC4330
default y if ARCH_CHIP_LPC4330FBD144 || ARCH_CHIP_LPC4330FET100 || ARCH_CHIP_LPC4330FET180 || ARCH_CHIP_LPC4330FET256
select ARCH_HAVE_TICKLESS
config ARCH_FAMILY_LPC4337
bool
default y if ARCH_CHIP_LPC4337JBD144
select ARCH_HAVE_TICKLESS
config ARCH_FAMILY_LPC4350
bool
default y if ARCH_CHIP_LPC4350FBD208 || ARCH_CHIP_LPC4350FET180 || ARCH_CHIP_LPC4350FET256

4
arch/arm/src/lpc43xx/chip.h
View File

@ -97,6 +97,10 @@
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc4310203050_memorymap.h"
# include "chip/lpc4310203050_pinconfig.h"
#elif defined(CONFIG_ARCH_CHIP_LPC4337JBD144)
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc435357_memorymap.h"
# include "chip/lpc4357fet256_pinconfig.h"
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define ARMV7M_PERIPHERAL_INTERRUPTS 53
# include "chip/lpc4310203050_memorymap.h"

2
arch/arm/src/lpc43xx/lpc43_allocateheap.c
View File

@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
/* Start with the first SRAM region */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

4
arch/arm/src/lpc43xx/lpc43_idle.c
View File

@ -57,8 +57,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/nuc1xx/nuc_idle.c
View File

@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

1
arch/arm/src/sam34/Kconfig
View File

@ -240,6 +240,7 @@ config ARCH_CHIP_SAM3A
config ARCH_CHIP_SAM4CM
bool
default n
select ARCH_HAVE_TICKLESS
config ARCH_CHIP_SAM4L
bool

4
arch/arm/src/sam34/sam_allocateheap.c
View File

@ -230,7 +230,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -241,7 +241,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

4
arch/arm/src/sama5/sam_allocateheap.c
View File

@ -258,7 +258,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
* heap is at the end of BSS through the configured end of SDRAM.
*/
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)&_ebss;
*heap_size = SAMA5_PRIMARY_HEAP_END - (size_t)&_ebss;
@ -267,7 +267,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
* IDLE stack through the configured end of ISRAM.
*/
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SAMA5_PRIMARY_HEAP_END - g_idle_topstack;
#endif

4
arch/arm/src/samdl/sam_idle.c
View File

@ -58,8 +58,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

4
arch/arm/src/samv7/sam_allocateheap.c
View File

@ -237,7 +237,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -248,7 +248,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

22
arch/arm/src/samv7/sam_config.h
View File

@ -109,18 +109,26 @@
#endif
/* USARTs *******************************************************************/
/* If the USART is not being used as a UART, then it really isn't enabled
* for our purposes.
/* If the USART is not being used as a UART or for SPI, then it really isn't
* enabled for our purposes.
*/
#ifndef CONFIG_USART0_ISUART
#if !defined(CONFIG_USART0_ISUART) && !defined(CONFIG_USART0_ISSPI)
# undef CONFIG_SAMV7_USART0
# undef CONFIG_USART0_SERIAL_CONSOLE
# undef CONFIG_USART0_IFLOWCONTROL
#endif
#ifndef CONFIG_USART1_ISUART
#if !defined(CONFIG_USART1_ISUART) && !defined(CONFIG_USART1_ISSPI)
# undef CONFIG_SAMV7_USART1
# undef CONFIG_USART1_SERIAL_CONSOLE
# undef CONFIG_USART1_IFLOWCONTROL
#endif
#ifndef CONFIG_USART2_ISUART
#if !defined(CONFIG_USART2_ISUART) && !defined(CONFIG_USART2_ISSPI)
# undef CONFIG_SAMV7_USART2
# undef CONFIG_USART2_SERIAL_CONSOLE
# undef CONFIG_USART2_IFLOWCONTROL
#endif
/* Don't enable USARTs not supported by the chip. */
@ -153,10 +161,10 @@
#undef CONFIG_UART3_IFLOWCONTROL
#undef CONFIG_UART4_IFLOWCONTROL
/* Hardware flow control requires using DMAC channel (not yet supported) */
/* Hardware flow control requires using a DMAC channel (not yet supported) */
#ifdef CONFIG_SERIAL_IFLOWCONTROL
# warning PDC or DMAC support is required for RTS hardware flow control
# warning XDMAC support is required for RTS hardware flow control
# undef CONFIG_SERIAL_IFLOWCONTROL
# undef CONFIG_USART0_IFLOWCONTROL
# undef CONFIG_USART1_IFLOWCONTROL

90
arch/arm/src/samv7/sam_serial.c
View File

@ -123,13 +123,13 @@
# elif defined(CONFIG_SAMV7_UART4)
# define TTYS0_DEV g_uart4port /* UART4 is ttyS0 */
# define UART4_ASSIGNED 1
# elif defined(CONFIG_SAMV7_USART0)
# elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
# define TTYS0_DEV g_usart0port /* USART0 is ttyS0 */
# define USART0_ASSIGNED 1
# elif defined(CONFIG_SAMV7_USART1)
# elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
# define TTYS0_DEV g_usart1port /* USART1 is ttyS0 */
# define USART1_ASSIGNED 1
# elif defined(CONFIG_SAMV7_USART2)
# elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
# define TTYS0_DEV g_usart2port /* USART2 is ttyS0 */
# define USART2_ASSIGNED 1
# endif
@ -154,13 +154,16 @@
#elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS1_DEV g_uart4port /* UART4 is ttyS1 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS1_DEV g_usart0port /* USART0 is ttyS1 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS1_DEV g_usart1port /* USART1 is ttyS1 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS1_DEV g_usart2port /* USART2 is ttyS1 */
# define USART2_ASSIGNED 1
#endif
@ -182,13 +185,16 @@
#elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS2_DEV g_uart4port /* UART4 is ttyS2 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS2_DEV g_usart0port /* USART0 is ttyS2 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS2_DEV g_usart1port /* USART1 is ttyS2 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS2_DEV g_usart2port /* USART2 is ttyS2 */
# define USART2_ASSIGNED 1
#endif
@ -207,13 +213,16 @@
#elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS3_DEV g_uart4port /* UART4 is ttyS3 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS3_DEV g_usart0port /* USART0 is ttyS3 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS3_DEV g_usart1port /* USART1 is ttyS3 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS3_DEV g_usart2port /* USART2 is ttyS3 */
# define USART2_ASSIGNED 1
#endif
@ -229,13 +238,16 @@
#elif defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS4_DEV g_uart4port /* UART4 is ttyS4 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS4_DEV g_usart0port /* USART0 is ttyS4 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS4_DEV g_usart1port /* USART1 is ttyS4 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS4_DEV g_usart2port /* USART2 is ttyS4 */
# define USART2_ASSIGNED 1
#endif
@ -248,13 +260,16 @@
#if defined(CONFIG_SAMV7_UART4) && !defined(UART4_ASSIGNED)
# define TTYS5_DEV g_uart4port /* UART4 is ttyS5 */
# define UART4_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS5_DEV g_usart0port /* USART0 is ttyS5 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS5_DEV g_usart1port /* USART1 is ttyS5 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS5_DEV g_usart2port /* USART2 is ttyS5 */
# define USART2_ASSIGNED 1
#endif
@ -264,13 +279,16 @@
* One of USART0-2 could also be the console.
*/
#if defined(CONFIG_SAMV7_USART0) && !defined(USART0_ASSIGNED)
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART) && \
!defined(USART0_ASSIGNED)
# define TTYS6_DEV g_usart0port /* USART0 is ttyS6 */
# define USART0_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS6_DEV g_usart1port /* USART1 is ttyS6 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS6_DEV g_usart2port /* USART2 is ttyS6 */
# define USART2_ASSIGNED 1
#endif
@ -280,10 +298,12 @@
* One of of USART1-2 could also be the console.
*/
#if defined(CONFIG_SAMV7_USART1) && !defined(USART1_ASSIGNED)
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART) && \
!defined(USART1_ASSIGNED)
# define TTYS7_DEV g_usart1port /* USART1 is ttyS7 */
# define USART1_ASSIGNED 1
#elif defined(CONFIG_SAMV7_USART2) && !defined(USART2_ASSIGNED)
#elif defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART) && \
!defined(USART2_ASSIGNED)
# define TTYS7_DEV g_usart2port /* USART2 is ttyS7 */
# define USART2_ASSIGNED 1
#endif
@ -349,13 +369,13 @@ static int sam_uart3_interrupt(int irq, void *context);
#ifdef CONFIG_SAMV7_UART4
static int sam_uart4_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_SAMV7_USART0
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
static int sam_usart0_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_SAMV7_USART1
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
static int sam_usart1_interrupt(int irq, void *context);
#endif
#ifdef CONFIG_SAMV7_USART2
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
static int sam_usart2_interrupt(int irq, void *context);
#endif
static int sam_ioctl(struct file *filep, int cmd, unsigned long arg);
@ -412,15 +432,15 @@ static char g_uart3txbuffer[CONFIG_UART3_TXBUFSIZE];
static char g_uart4rxbuffer[CONFIG_UART4_RXBUFSIZE];
static char g_uart4txbuffer[CONFIG_UART4_TXBUFSIZE];
#endif
#ifdef CONFIG_SAMV7_USART0
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
static char g_usart0rxbuffer[CONFIG_USART0_RXBUFSIZE];
static char g_usart0txbuffer[CONFIG_USART0_TXBUFSIZE];
#endif
#ifdef CONFIG_SAMV7_USART1
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
static char g_usart1rxbuffer[CONFIG_USART1_RXBUFSIZE];
static char g_usart1txbuffer[CONFIG_USART1_TXBUFSIZE];
#endif
#ifdef CONFIG_SAMV7_USART2
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
static char g_usart2rxbuffer[CONFIG_USART2_RXBUFSIZE];
static char g_usart2txbuffer[CONFIG_USART2_TXBUFSIZE];
#endif
@ -582,7 +602,7 @@ static uart_dev_t g_uart4port =
/* This describes the state of the USART0 port. */
#ifdef CONFIG_SAMV7_USART0
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
static struct sam_dev_s g_usart0priv =
{
.usartbase = SAM_USART0_BASE,
@ -616,7 +636,7 @@ static uart_dev_t g_usart0port =
/* This describes the state of the USART1 port. */
#ifdef CONFIG_SAMV7_USART1
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
static struct sam_dev_s g_usart1priv =
{
.usartbase = SAM_USART1_BASE,
@ -650,7 +670,7 @@ static uart_dev_t g_usart1port =
/* This describes the state of the USART2 port. */
#ifdef CONFIG_SAMV7_USART2
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
static struct sam_dev_s g_usart2priv =
{
.usartbase = SAM_USART2_BASE,
@ -1095,19 +1115,19 @@ static int sam_uart4_interrupt(int irq, void *context)
*
****************************************************************************/
#ifdef CONFIG_SAMV7_USART0
#if defined(CONFIG_SAMV7_USART0) && defined(CONFIG_USART0_ISUART)
static int sam_usart0_interrupt(int irq, void *context)
{
return sam_interrupt(&g_usart0port);
}
#endif
#ifdef CONFIG_SAMV7_USART1
#if defined(CONFIG_SAMV7_USART1) && defined(CONFIG_USART1_ISUART)
static int sam_usart1_interrupt(int irq, void *context)
{
return sam_interrupt(&g_usart1port);
}
#endif
#ifdef CONFIG_SAMV7_USART2
#if defined(CONFIG_SAMV7_USART2) && defined(CONFIG_USART2_ISUART)
static int sam_usart2_interrupt(int irq, void *context)
{
return sam_interrupt(&g_usart2port);

1610
arch/arm/src/stm32/Kconfig
View File

File diff suppressed because it is too large Load Diff

12
arch/arm/src/stm32/chip/stm32_tim.h
View File

@ -677,8 +677,8 @@
#define ATIM_CCMR1_OC2CE (1 << 15) /* Bit 15: Output Compare 2 Clear Enable */
#ifdef CONFIG_STM32_STM32F30XX
# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
# define ATIM_CCMR1_OC1M (1 << 16) /* Bit 16: Output Compare 1 mode - bit 3 */
# define ATIM_CCMR1_OC2M (1 << 24) /* Bit 24: Output Compare 2 mode - bit 3 */
#endif
/* Common CCMR (unshifted) Capture/Compare Selection bit-field definitions */
@ -698,6 +698,10 @@
#define ATIM_CCMR_MODE_OCREFHI (5) /* 101: OCxREF forced high */
#define ATIM_CCMR_MODE_PWM1 (6) /* 110: PWM mode 1 */
#define ATIM_CCMR_MODE_PWM2 (7) /* 111: PWM mode 2 */
#define ATIM_CCMR_MODE_COMBINED1 (12) /* 1100: Combined PWM mode 1 */
#define ATIM_CCMR_MODE_COMBINED2 (13) /* 1101: Combined PWM mode 2 */
#define ATIM_CCMR_MODE_ASYMMETRIC1 (14) /* 1110: Asymmetric PWM mode 1 */
#define ATIM_CCMR_MODE_ASYMMETRIC2 (15) /* 1111: Asymmetric PWM mode 2 */
/* Capture/compare mode register 1 -- Input capture mode */
@ -764,8 +768,8 @@
#define ATIM_CCMR2_OC4CE (1 << 15) /* Bit 15: Output Compare 4 Clear Enable */
#ifdef CONFIG_STM32_STM32F30XX
# define ATIM_CCMR1_OC3M 1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */
# define ATIM_CCMR1_OC4M 1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */
# define ATIM_CCMR2_OC3M (1 << 16) /* Bit 16: Output Compare 3 mode - bit 3 */
# define ATIM_CCMR2_OC4M (1 << 24) /* Bit 24: Output Compare 4 mode - bit 3 */
#endif
/* Capture/compare mode register 2 - Input Capture Mode */

4
arch/arm/src/stm32/stm32_allocateheap.c
View File

@ -511,7 +511,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -526,7 +526,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;

4
arch/arm/src/stm32/stm32_idle.c
View File

@ -60,8 +60,8 @@
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_led_on(LED_IDLE)
# define END_IDLE() board_led_off(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()

1183
arch/arm/src/stm32/stm32_pwm.c
View File

File diff suppressed because it is too large Load Diff

839
arch/arm/src/stm32/stm32_pwm.h
View File

@ -2,7 +2,9 @@
* arch/arm/src/stm32/stm32_pwm.h
*
* Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Paul Alexander Patience <paul-a.patience@polymtl.ca>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@ -96,6 +98,15 @@
#ifndef CONFIG_STM32_TIM14
# undef CONFIG_STM32_TIM14_PWM
#endif
#ifndef CONFIG_STM32_TIM15
# undef CONFIG_STM32_TIM15_PWM
#endif
#ifndef CONFIG_STM32_TIM16
# undef CONFIG_STM32_TIM16_PWM
#endif
#ifndef CONFIG_STM32_TIM17
# undef CONFIG_STM32_TIM17_PWM
#endif
/* The basic timers (timer 6 and 7) are not capable of generating output pulses */
@ -109,11 +120,597 @@
defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \
defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \
defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM)
defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM) || \
defined(CONFIG_STM32_TIM15_PWM) || defined(CONFIG_STM32_TIM16_PWM) || \
defined(CONFIG_STM32_TIM17_PWM)
#include <arch/board/board.h>
#include "chip/stm32_tim.h"
#ifdef CONFIG_PWM_MULTICHAN
#ifdef CONFIG_STM32_TIM1_CHANNEL1
# ifdef CONFIG_STM32_TIM1_CH1OUT
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# else
# define PWM_TIM1_CH1CFG 0
# endif
# define PWM_TIM1_CHANNEL1 1
#else
# define PWM_TIM1_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM1_CHANNEL2
# ifdef CONFIG_STM32_TIM1_CH2OUT
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# else
# define PWM_TIM1_CH2CFG 0
# endif
# define PWM_TIM1_CHANNEL2 1
#else
# define PWM_TIM1_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM1_CHANNEL3
# ifdef CONFIG_STM32_TIM1_CH3OUT
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# else
# define PWM_TIM1_CH3CFG 0
# endif
# define PWM_TIM1_CHANNEL3 1
#else
# define PWM_TIM1_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM1_CHANNEL4
# ifdef CONFIG_STM32_TIM1_CH4OUT
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# define PWM_TIM1_CH4CFG 0
# endif
# define PWM_TIM1_CHANNEL4 1
#else
# define PWM_TIM1_CHANNEL4 0
#endif
#define PWM_TIM1_NCHANNELS (PWM_TIM1_CHANNEL1 + PWM_TIM1_CHANNEL2 + \
PWM_TIM1_CHANNEL3 + PWM_TIM1_CHANNEL4)
#ifdef CONFIG_STM32_TIM2_CHANNEL1
# ifdef CONFIG_STM32_TIM2_CH1OUT
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# else
# define PWM_TIM2_CH1CFG 0
# endif
# define PWM_TIM2_CHANNEL1 1
#else
# define PWM_TIM2_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM2_CHANNEL2
# ifdef CONFIG_STM32_TIM2_CH2OUT
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# else
# define PWM_TIM2_CH2CFG 0
# endif
# define PWM_TIM2_CHANNEL2 1
#else
# define PWM_TIM2_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM2_CHANNEL3
# ifdef CONFIG_STM32_TIM2_CH3OUT
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# else
# define PWM_TIM2_CH3CFG 0
# endif
# define PWM_TIM2_CHANNEL3 1
#else
# define PWM_TIM2_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM2_CHANNEL4
# ifdef CONFIG_STM32_TIM2_CH4OUT
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# define PWM_TIM2_CH4CFG 0
# endif
# define PWM_TIM2_CHANNEL4 1
#else
# define PWM_TIM2_CHANNEL4 0
#endif
#define PWM_TIM2_NCHANNELS (PWM_TIM2_CHANNEL1 + PWM_TIM2_CHANNEL2 + \
PWM_TIM2_CHANNEL3 + PWM_TIM2_CHANNEL4)
#ifdef CONFIG_STM32_TIM3_CHANNEL1
# ifdef CONFIG_STM32_TIM3_CH1OUT
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# else
# define PWM_TIM3_CH1CFG 0
# endif
# define PWM_TIM3_CHANNEL1 1
#else
# define PWM_TIM3_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM3_CHANNEL2
# ifdef CONFIG_STM32_TIM3_CH2OUT
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# else
# define PWM_TIM3_CH2CFG 0
# endif
# define PWM_TIM3_CHANNEL2 1
#else
# define PWM_TIM3_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM3_CHANNEL3
# ifdef CONFIG_STM32_TIM3_CH3OUT
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# else
# define PWM_TIM3_CH3CFG 0
# endif
# define PWM_TIM3_CHANNEL3 1
#else
# define PWM_TIM3_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM3_CHANNEL4
# ifdef CONFIG_STM32_TIM3_CH4OUT
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# define PWM_TIM3_CH4CFG 0
# endif
# define PWM_TIM3_CHANNEL4 1
#else
# define PWM_TIM3_CHANNEL4 0
#endif
#define PWM_TIM3_NCHANNELS (PWM_TIM3_CHANNEL1 + PWM_TIM3_CHANNEL2 + \
PWM_TIM3_CHANNEL3 + PWM_TIM3_CHANNEL4)
#ifdef CONFIG_STM32_TIM4_CHANNEL1
# ifdef CONFIG_STM32_TIM4_CH1OUT
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
# else
# define PWM_TIM4_CH1CFG 0
# endif
# define PWM_TIM4_CHANNEL1 1
#else
# define PWM_TIM4_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM4_CHANNEL2
# ifdef CONFIG_STM32_TIM4_CH2OUT
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
# else
# define PWM_TIM4_CH2CFG 0
# endif
# define PWM_TIM4_CHANNEL2 1
#else
# define PWM_TIM4_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM4_CHANNEL3
# ifdef CONFIG_STM32_TIM4_CH3OUT
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
# else
# define PWM_TIM4_CH3CFG 0
# endif
# define PWM_TIM4_CHANNEL3 1
#else
# define PWM_TIM4_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM4_CHANNEL4
# ifdef CONFIG_STM32_TIM4_CH4OUT
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
# else
# define PWM_TIM4_CH4CFG 0
# endif
# define PWM_TIM4_CHANNEL4 1
#else
# define PWM_TIM4_CHANNEL4 0
#endif
#define PWM_TIM4_NCHANNELS (PWM_TIM4_CHANNEL1 + PWM_TIM4_CHANNEL2 + \
PWM_TIM4_CHANNEL3 + PWM_TIM4_CHANNEL4)
#ifdef CONFIG_STM32_TIM5_CHANNEL1
# ifdef CONFIG_STM32_TIM5_CH1OUT
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
# else
# define PWM_TIM5_CH1CFG 0
# endif
# define PWM_TIM5_CHANNEL1 1
#else
# define PWM_TIM5_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM5_CHANNEL2
# ifdef CONFIG_STM32_TIM5_CH2OUT
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
# else
# define PWM_TIM5_CH2CFG 0
# endif
# define PWM_TIM5_CHANNEL2 1
#else
# define PWM_TIM5_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM5_CHANNEL3
# ifdef CONFIG_STM32_TIM5_CH3OUT
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
# else
# define PWM_TIM5_CH3CFG 0
# endif
# define PWM_TIM5_CHANNEL3 1
#else
# define PWM_TIM5_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM5_CHANNEL4
# ifdef CONFIG_STM32_TIM5_CH4OUT
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
# else
# define PWM_TIM5_CH4CFG 0
# endif
# define PWM_TIM5_CHANNEL4 1
#else
# define PWM_TIM5_CHANNEL4 0
#endif
#define PWM_TIM5_NCHANNELS (PWM_TIM5_CHANNEL1 + PWM_TIM5_CHANNEL2 + \
PWM_TIM5_CHANNEL3 + PWM_TIM5_CHANNEL4)
#ifdef CONFIG_STM32_TIM8_CHANNEL1
# ifdef CONFIG_STM32_TIM8_CH1OUT
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
# else
# define PWM_TIM8_CH1CFG 0
# endif
# define PWM_TIM8_CHANNEL1 1
#else
# define PWM_TIM8_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM8_CHANNEL2
# ifdef CONFIG_STM32_TIM8_CH2OUT
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
# else
# define PWM_TIM8_CH2CFG 0
# endif
# define PWM_TIM8_CHANNEL2 1
#else
# define PWM_TIM8_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM8_CHANNEL3
# ifdef CONFIG_STM32_TIM8_CH3OUT
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
# else
# define PWM_TIM8_CH3CFG 0
# endif
# define PWM_TIM8_CHANNEL3 1
#else
# define PWM_TIM8_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM8_CHANNEL4
# ifdef CONFIG_STM32_TIM8_CH4OUT
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
# else
# define PWM_TIM8_CH4CFG 0
# endif
# define PWM_TIM8_CHANNEL4 1
#else
# define PWM_TIM8_CHANNEL4 0
#endif
#define PWM_TIM8_NCHANNELS (PWM_TIM8_CHANNEL1 + PWM_TIM8_CHANNEL2 + \
PWM_TIM8_CHANNEL3 + PWM_TIM8_CHANNEL4)
#ifdef CONFIG_STM32_TIM9_CHANNEL1
# ifdef CONFIG_STM32_TIM9_CH1OUT
# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT
# else
# define PWM_TIM9_CH1CFG 0
# endif
# define PWM_TIM9_CHANNEL1 1
#else
# define PWM_TIM9_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM9_CHANNEL2
# ifdef CONFIG_STM32_TIM9_CH2OUT
# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT
# else
# define PWM_TIM9_CH2CFG 0
# endif
# define PWM_TIM9_CHANNEL2 1
#else
# define PWM_TIM9_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM9_CHANNEL3
# ifdef CONFIG_STM32_TIM9_CH3OUT
# define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT
# else
# define PWM_TIM9_CH3CFG 0
# endif
# define PWM_TIM9_CHANNEL3 1
#else
# define PWM_TIM9_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM9_CHANNEL4
# ifdef CONFIG_STM32_TIM9_CH4OUT
# define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT
# else
# define PWM_TIM9_CH4CFG 0
# endif
# define PWM_TIM9_CHANNEL4 1
#else
# define PWM_TIM9_CHANNEL4 0
#endif
#define PWM_TIM9_NCHANNELS (PWM_TIM9_CHANNEL1 + PWM_TIM9_CHANNEL2 + \
PWM_TIM9_CHANNEL3 + PWM_TIM9_CHANNEL4)
#ifdef CONFIG_STM32_TIM10_CHANNEL1
# ifdef CONFIG_STM32_TIM10_CH1OUT
# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT
# else
# define PWM_TIM10_CH1CFG 0
# endif
# define PWM_TIM10_CHANNEL1 1
#else
# define PWM_TIM10_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM10_CHANNEL2
# ifdef CONFIG_STM32_TIM10_CH2OUT
# define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT
# else
# define PWM_TIM10_CH2CFG 0
# endif
# define PWM_TIM10_CHANNEL2 1
#else
# define PWM_TIM10_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM10_CHANNEL3
# ifdef CONFIG_STM32_TIM10_CH3OUT
# define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT
# else
# define PWM_TIM10_CH3CFG 0
# endif
# define PWM_TIM10_CHANNEL3 1
#else
# define PWM_TIM10_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM10_CHANNEL4
# ifdef CONFIG_STM32_TIM10_CH4OUT
# define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT
# else
# define PWM_TIM10_CH4CFG 0
# endif
# define PWM_TIM10_CHANNEL4 1
#else
# define PWM_TIM10_CHANNEL4 0
#endif
#define PWM_TIM10_NCHANNELS (PWM_TIM10_CHANNEL1 + PWM_TIM10_CHANNEL2 + \
PWM_TIM10_CHANNEL3 + PWM_TIM10_CHANNEL4)
#ifdef CONFIG_STM32_TIM11_CHANNEL1
# ifdef CONFIG_STM32_TIM11_CH1OUT
# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT
# else
# define PWM_TIM11_CH1CFG 0
# endif
# define PWM_TIM11_CHANNEL1 1
#else
# define PWM_TIM11_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM11_CHANNEL2
# ifdef CONFIG_STM32_TIM11_CH2OUT
# define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT
# else
# define PWM_TIM11_CH2CFG 0
# endif
# define PWM_TIM11_CHANNEL2 1
#else
# define PWM_TIM11_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM11_CHANNEL3
# ifdef CONFIG_STM32_TIM11_CH3OUT
# define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT
# else
# define PWM_TIM11_CH3CFG 0
# endif
# define PWM_TIM11_CHANNEL3 1
#else
# define PWM_TIM11_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM11_CHANNEL4
# ifdef CONFIG_STM32_TIM11_CH4OUT
# define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT
# else
# define PWM_TIM11_CH4CFG 0
# endif
# define PWM_TIM11_CHANNEL4 1
#else
# define PWM_TIM11_CHANNEL4 0
#endif
#define PWM_TIM11_NCHANNELS (PWM_TIM11_CHANNEL1 + PWM_TIM11_CHANNEL2 + \
PWM_TIM11_CHANNEL3 + PWM_TIM11_CHANNEL4)
#ifdef CONFIG_STM32_TIM12_CHANNEL1
# ifdef CONFIG_STM32_TIM12_CH1OUT
# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
# else
# define PWM_TIM12_CH1CFG 0
# endif
# define PWM_TIM12_CHANNEL1 1
#else
# define PWM_TIM12_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM12_CHANNEL2
# ifdef CONFIG_STM32_TIM12_CH2OUT
# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
# else
# define PWM_TIM12_CH2CFG 0
# endif
# define PWM_TIM12_CHANNEL2 1
#else
# define PWM_TIM12_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM12_CHANNEL3
# ifdef CONFIG_STM32_TIM12_CH3OUT
# define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT
# else
# define PWM_TIM12_CH3CFG 0
# endif
# define PWM_TIM12_CHANNEL3 1
#else
# define PWM_TIM12_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM12_CHANNEL4
# ifdef CONFIG_STM32_TIM12_CH4OUT
# define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT
# else
# define PWM_TIM12_CH4CFG 0
# endif
# define PWM_TIM12_CHANNEL4 1
#else
# define PWM_TIM12_CHANNEL4 0
#endif
#define PWM_TIM12_NCHANNELS (PWM_TIM12_CHANNEL1 + PWM_TIM12_CHANNEL2 + \
PWM_TIM12_CHANNEL3 + PWM_TIM12_CHANNEL4)
#ifdef CONFIG_STM32_TIM13_CHANNEL1
# ifdef CONFIG_STM32_TIM13_CH1OUT
# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
# else
# define PWM_TIM13_CH1CFG 0
# endif
# define PWM_TIM13_CHANNEL1 1
#else
# define PWM_TIM13_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM13_CHANNEL2
# ifdef CONFIG_STM32_TIM13_CH2OUT
# define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT
# else
# define PWM_TIM13_CH2CFG 0
# endif
# define PWM_TIM13_CHANNEL2 1
#else
# define PWM_TIM13_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM13_CHANNEL3
# ifdef CONFIG_STM32_TIM13_CH3OUT
# define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT
# else
# define PWM_TIM13_CH3CFG 0
# endif
# define PWM_TIM13_CHANNEL3 1
#else
# define PWM_TIM13_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM13_CHANNEL4
# ifdef CONFIG_STM32_TIM13_CH4OUT
# define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT
# else
# define PWM_TIM13_CH4CFG 0
# endif
# define PWM_TIM13_CHANNEL4 1
#else
# define PWM_TIM13_CHANNEL4 0
#endif
#define PWM_TIM13_NCHANNELS (PWM_TIM13_CHANNEL1 + PWM_TIM13_CHANNEL2 + \
PWM_TIM13_CHANNEL3 + PWM_TIM13_CHANNEL4)
#ifdef CONFIG_STM32_TIM14_CHANNEL1
# ifdef CONFIG_STM32_TIM14_CH1OUT
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
# else
# define PWM_TIM14_CH1CFG 0
# endif
# define PWM_TIM14_CHANNEL1 1
#else
# define PWM_TIM14_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM14_CHANNEL2
# ifdef CONFIG_STM32_TIM14_CH2OUT
# define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT
# else
# define PWM_TIM14_CH2CFG 0
# endif
# define PWM_TIM14_CHANNEL2 1
#else
# define PWM_TIM14_CHANNEL2 0
#endif
#ifdef CONFIG_STM32_TIM14_CHANNEL3
# ifdef CONFIG_STM32_TIM14_CH3OUT
# define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT
# else
# define PWM_TIM14_CH3CFG 0
# endif
# define PWM_TIM14_CHANNEL3 1
#else
# define PWM_TIM14_CHANNEL3 0
#endif
#ifdef CONFIG_STM32_TIM14_CHANNEL4
# ifdef CONFIG_STM32_TIM14_CH4OUT
# define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT
# else
# define PWM_TIM14_CH4CFG 0
# endif
# define PWM_TIM14_CHANNEL4 1
#else
# define PWM_TIM14_CHANNEL4 0
#endif
#define PWM_TIM14_NCHANNELS (PWM_TIM14_CHANNEL1 + PWM_TIM14_CHANNEL2 + \
PWM_TIM14_CHANNEL3 + PWM_TIM14_CHANNEL4)
#ifdef CONFIG_STM32_TIM15_CHANNEL1
# ifdef CONFIG_STM32_TIM15_CH1OUT
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# else
# define PWM_TIM15_CH1CFG 0
# endif
# define PWM_TIM15_CHANNEL1 1
#else
# define PWM_TIM15_CHANNEL1 0
#endif
#ifdef CONFIG_STM32_TIM15_CHANNEL2
# ifdef CONFIG_STM32_TIM15_CH2OUT
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# define PWM_TIM15_CH2CFG 0
# endif
# define PWM_TIM15_CHANNEL2 1
#else
# define PWM_TIM15_CHANNEL2 0
#endif
#define PWM_TIM15_NCHANNELS (PWM_TIM15_CHANNEL1 + PWM_TIM15_CHANNEL2)
#ifdef CONFIG_STM32_TIM16_CHANNEL1
# ifdef CONFIG_STM32_TIM16_CH1OUT
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# else
# define PWM_TIM16_CH1CFG 0
# endif
# define PWM_TIM16_CHANNEL1 1
#else
# define PWM_TIM16_CHANNEL1 0
#endif
#define PWM_TIM16_NCHANNELS PWM_TIM16_CHANNEL1
#ifdef CONFIG_STM32_TIM17_CHANNEL1
# ifdef CONFIG_STM32_TIM17_CH1OUT
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# else
# define PWM_TIM17_CH1CFG 0
# endif
# define PWM_TIM17_CHANNEL1 1
#else
# define PWM_TIM17_CHANNEL1 0
#endif
#define PWM_TIM17_NCHANNELS PWM_TIM17_CHANNEL1
#define PWM_MAX(a, b) ((a) > (b) ? (a) : (b))
#define PWM_NCHANNELS PWM_MAX(PWM_TIM1_NCHANNELS, \
PWM_MAX(PWM_TIM2_NCHANNELS, \
PWM_MAX(PWM_TIM3_NCHANNELS, \
PWM_MAX(PWM_TIM4_NCHANNELS, \
PWM_MAX(PWM_TIM5_NCHANNELS, \
PWM_MAX(PWM_TIM8_NCHANNELS, \
PWM_MAX(PWM_TIM9_NCHANNELS, \
PWM_MAX(PWM_TIM10_NCHANNELS, \
PWM_MAX(PWM_TIM11_NCHANNELS, \
PWM_MAX(PWM_TIM12_NCHANNELS, \
PWM_MAX(PWM_TIM13_NCHANNELS, \
PWM_MAX(PWM_TIM14_NCHANNELS, \
PWM_MAX(PWM_TIM15_NCHANNELS, \
PWM_MAX(PWM_TIM16_NCHANNELS, \
PWM_TIM17_NCHANNELS))))))))))))))
#else
/* For each timer that is enabled for PWM usage, we need the following additional
* configuration settings:
*
@ -131,13 +728,21 @@
# if !defined(CONFIG_STM32_TIM1_CHANNEL)
# error "CONFIG_STM32_TIM1_CHANNEL must be provided"
# elif CONFIG_STM32_TIM1_CHANNEL == 1
# define PWM_TIM1_PINCFG GPIO_TIM1_CH1OUT
# define CONFIG_STM32_TIM1_CHANNEL1 1
# define CONFIG_STM32_TIM1_CH1MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH1CFG GPIO_TIM1_CH1OUT
# elif CONFIG_STM32_TIM1_CHANNEL == 2
# define PWM_TIM1_PINCFG GPIO_TIM1_CH2OUT
# define CONFIG_STM32_TIM1_CHANNEL2 1
# define CONFIG_STM32_TIM1_CH2MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH2CFG GPIO_TIM1_CH2OUT
# elif CONFIG_STM32_TIM1_CHANNEL == 3
# define PWM_TIM1_PINCFG GPIO_TIM1_CH3OUT
# define CONFIG_STM32_TIM1_CHANNEL3 1
# define CONFIG_STM32_TIM1_CH3MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH3CFG GPIO_TIM1_CH3OUT
# elif CONFIG_STM32_TIM1_CHANNEL == 4
# define PWM_TIM1_PINCFG GPIO_TIM1_CH4OUT
# define CONFIG_STM32_TIM1_CHANNEL4 1
# define CONFIG_STM32_TIM1_CH4MODE CONFIG_STM32_TIM1_CHMODE
# define PWM_TIM1_CH4CFG GPIO_TIM1_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM1_CHANNEL"
# endif
@ -147,13 +752,21 @@
# if !defined(CONFIG_STM32_TIM2_CHANNEL)
# error "CONFIG_STM32_TIM2_CHANNEL must be provided"
# elif CONFIG_STM32_TIM2_CHANNEL == 1
# define PWM_TIM2_PINCFG GPIO_TIM2_CH1OUT
# define CONFIG_STM32_TIM2_CHANNEL1 1
# define CONFIG_STM32_TIM2_CH1MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH1CFG GPIO_TIM2_CH1OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 2
# define PWM_TIM2_PINCFG GPIO_TIM2_CH2OUT
# define CONFIG_STM32_TIM2_CHANNEL2 1
# define CONFIG_STM32_TIM2_CH2MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH2CFG GPIO_TIM2_CH2OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 3
# define PWM_TIM2_PINCFG GPIO_TIM2_CH3OUT
# define CONFIG_STM32_TIM2_CHANNEL3 1
# define CONFIG_STM32_TIM2_CH3MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH3CFG GPIO_TIM2_CH3OUT
# elif CONFIG_STM32_TIM2_CHANNEL == 4
# define PWM_TIM2_PINCFG GPIO_TIM2_CH4OUT
# define CONFIG_STM32_TIM2_CHANNEL4 1
# define CONFIG_STM32_TIM2_CH4MODE CONFIG_STM32_TIM2_CHMODE
# define PWM_TIM2_CH4CFG GPIO_TIM2_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM2_CHANNEL"
# endif
@ -163,13 +776,21 @@
# if !defined(CONFIG_STM32_TIM3_CHANNEL)
# error "CONFIG_STM32_TIM3_CHANNEL must be provided"
# elif CONFIG_STM32_TIM3_CHANNEL == 1
# define PWM_TIM3_PINCFG GPIO_TIM3_CH1OUT
# define CONFIG_STM32_TIM3_CHANNEL1 1
# define CONFIG_STM32_TIM3_CH1MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH1CFG GPIO_TIM3_CH1OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 2
# define PWM_TIM3_PINCFG GPIO_TIM3_CH2OUT
# define CONFIG_STM32_TIM3_CHANNEL2 1
# define CONFIG_STM32_TIM3_CH2MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH2CFG GPIO_TIM3_CH2OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 3
# define PWM_TIM3_PINCFG GPIO_TIM3_CH3OUT
# define CONFIG_STM32_TIM3_CHANNEL3 1
# define CONFIG_STM32_TIM3_CH3MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH3CFG GPIO_TIM3_CH3OUT
# elif CONFIG_STM32_TIM3_CHANNEL == 4
# define PWM_TIM3_PINCFG GPIO_TIM3_CH4OUT
# define CONFIG_STM32_TIM3_CHANNEL4 1
# define CONFIG_STM32_TIM3_CH4MODE CONFIG_STM32_TIM3_CHMODE
# define PWM_TIM3_CH4CFG GPIO_TIM3_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM3_CHANNEL"
# endif
@ -179,13 +800,21 @@
# if !defined(CONFIG_STM32_TIM4_CHANNEL)
# error "CONFIG_STM32_TIM4_CHANNEL must be provided"
# elif CONFIG_STM32_TIM4_CHANNEL == 1
# define PWM_TIM4_PINCFG GPIO_TIM4_CH1OUT
# define CONFIG_STM32_TIM4_CHANNEL1 1
# define CONFIG_STM32_TIM4_CH1MODE CONFIG_STM32_TIM4_CHMODE
# define PWM_TIM4_CH1CFG GPIO_TIM4_CH1OUT
# elif CONFIG_STM32_TIM4_CHANNEL == 2
# define PWM_TIM4_PINCFG GPIO_TIM4_CH2OUT
# define CONFIG_STM32_TIM4_CHANNEL2 1
# define CONFIG_STM32_TIM4_CH2MODE CONFIG_STM32_TIM4_CHMODE
# define PWM_TIM4_CH2CFG GPIO_TIM4_CH2OUT
# elif CONFIG_STM32_TIM4_CHANNEL == 3
# define PWM_TIM4_PINCFG GPIO_TIM4_CH3OUT
# define CONFIG_STM32_TIM4_CHANNEL3 1
# define CONFIG_STM32_TIM4_CH3MODE CONFIG_STM32_TIM4_CHMODE
# define PWM_TIM4_CH3CFG GPIO_TIM4_CH3OUT
# elif CONFIG_STM32_TIM4_CHANNEL == 4
# define PWM_TIM4_PINCFG GPIO_TIM4_CH4OUT
# define CONFIG_STM32_TIM4_CHANNEL4 1
# define CONFIG_STM32_TIM4_CH4MODE CONFIG_STM32_TIM4_CHMODE
# define PWM_TIM4_CH4CFG GPIO_TIM4_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM4_CHANNEL"
# endif
@ -195,13 +824,21 @@
# if !defined(CONFIG_STM32_TIM5_CHANNEL)
# error "CONFIG_STM32_TIM5_CHANNEL must be provided"
# elif CONFIG_STM32_TIM5_CHANNEL == 1
# define PWM_TIM5_PINCFG GPIO_TIM5_CH1OUT
# define CONFIG_STM32_TIM5_CHANNEL1 1
# define CONFIG_STM32_TIM5_CH1MODE CONFIG_STM32_TIM5_CHMODE
# define PWM_TIM5_CH1CFG GPIO_TIM5_CH1OUT
# elif CONFIG_STM32_TIM5_CHANNEL == 2
# define PWM_TIM5_PINCFG GPIO_TIM5_CH2OUT
# define CONFIG_STM32_TIM5_CHANNEL2 1
# define CONFIG_STM32_TIM5_CH2MODE CONFIG_STM32_TIM5_CHMODE
# define PWM_TIM5_CH2CFG GPIO_TIM5_CH2OUT
# elif CONFIG_STM32_TIM5_CHANNEL == 3
# define PWM_TIM5_PINCFG GPIO_TIM5_CH3OUT
# define CONFIG_STM32_TIM5_CHANNEL3 1
# define CONFIG_STM32_TIM5_CH3MODE CONFIG_STM32_TIM5_CHMODE
# define PWM_TIM5_CH3CFG GPIO_TIM5_CH3OUT
# elif CONFIG_STM32_TIM5_CHANNEL == 4
# define PWM_TIM5_PINCFG GPIO_TIM5_CH4OUT
# define CONFIG_STM32_TIM5_CHANNEL4 1
# define CONFIG_STM32_TIM5_CH4MODE CONFIG_STM32_TIM5_CHMODE
# define PWM_TIM5_CH4CFG GPIO_TIM5_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM5_CHANNEL"
# endif
@ -211,13 +848,21 @@
# if !defined(CONFIG_STM32_TIM8_CHANNEL)
# error "CONFIG_STM32_TIM8_CHANNEL must be provided"
# elif CONFIG_STM32_TIM8_CHANNEL == 1
# define PWM_TIM8_PINCFG GPIO_TIM8_CH1OUT
# define CONFIG_STM32_TIM8_CHANNEL1 1
# define CONFIG_STM32_TIM8_CH1MODE CONFIG_STM32_TIM8_CHMODE
# define PWM_TIM8_CH1CFG GPIO_TIM8_CH1OUT
# elif CONFIG_STM32_TIM8_CHANNEL == 2
# define PWM_TIM8_PINCFG GPIO_TIM8_CH2OUT
# define CONFIG_STM32_TIM8_CHANNEL2 1
# define CONFIG_STM32_TIM8_CH2MODE CONFIG_STM32_TIM8_CHMODE
# define PWM_TIM8_CH2CFG GPIO_TIM8_CH2OUT
# elif CONFIG_STM32_TIM8_CHANNEL == 3
# define PWM_TIM8_PINCFG GPIO_TIM8_CH3OUT
# define CONFIG_STM32_TIM8_CHANNEL3 1
# define CONFIG_STM32_TIM8_CH3MODE CONFIG_STM32_TIM8_CHMODE
# define PWM_TIM8_CH3CFG GPIO_TIM8_CH3OUT
# elif CONFIG_STM32_TIM8_CHANNEL == 4
# define PWM_TIM8_PINCFG GPIO_TIM8_CH4OUT
# define CONFIG_STM32_TIM8_CHANNEL4 1
# define CONFIG_STM32_TIM8_CH4MODE CONFIG_STM32_TIM8_CHMODE
# define PWM_TIM8_CH4CFG GPIO_TIM8_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM8_CHANNEL"
# endif
@ -227,13 +872,21 @@
# if !defined(CONFIG_STM32_TIM9_CHANNEL)
# error "CONFIG_STM32_TIM9_CHANNEL must be provided"
# elif CONFIG_STM32_TIM9_CHANNEL == 1
# define PWM_TIM9_PINCFG GPIO_TIM9_CH1OUT
# define CONFIG_STM32_TIM9_CHANNEL1 1
# define CONFIG_STM32_TIM9_CH1MODE CONFIG_STM32_TIM9_CHMODE
# define PWM_TIM9_CH1CFG GPIO_TIM9_CH1OUT
# elif CONFIG_STM32_TIM9_CHANNEL == 2
# define PWM_TIM9_PINCFG GPIO_TIM9_CH2OUT
# define CONFIG_STM32_TIM9_CHANNEL2 1
# define CONFIG_STM32_TIM9_CH2MODE CONFIG_STM32_TIM9_CHMODE
# define PWM_TIM9_CH2CFG GPIO_TIM9_CH2OUT
# elif CONFIG_STM32_TIM9_CHANNEL == 3
# define PWM_TIM9_PINCFG GPIO_TIM9_CH3OUT
# define CONFIG_STM32_TIM9_CHANNEL3 1
# define CONFIG_STM32_TIM9_CH3MODE CONFIG_STM32_TIM9_CHMODE
# define PWM_TIM9_CH3CFG GPIO_TIM9_CH3OUT
# elif CONFIG_STM32_TIM9_CHANNEL == 4
# define PWM_TIM9_PINCFG GPIO_TIM9_CH4OUT
# define CONFIG_STM32_TIM9_CHANNEL4 1
# define CONFIG_STM32_TIM9_CH4MODE CONFIG_STM32_TIM9_CHMODE
# define PWM_TIM9_CH4CFG GPIO_TIM9_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM9_CHANNEL"
# endif
@ -243,13 +896,21 @@
# if !defined(CONFIG_STM32_TIM10_CHANNEL)
# error "CONFIG_STM32_TIM10_CHANNEL must be provided"
# elif CONFIG_STM32_TIM10_CHANNEL == 1
# define PWM_TIM10_PINCFG GPIO_TIM10_CH1OUT
# define CONFIG_STM32_TIM10_CHANNEL1 1
# define CONFIG_STM32_TIM10_CH1MODE CONFIG_STM32_TIM10_CHMODE
# define PWM_TIM10_CH1CFG GPIO_TIM10_CH1OUT
# elif CONFIG_STM32_TIM10_CHANNEL == 2
# define PWM_TIM10_PINCFG GPIO_TIM10_CH2OUT
# define CONFIG_STM32_TIM10_CHANNEL2 1
# define CONFIG_STM32_TIM10_CH2MODE CONFIG_STM32_TIM10_CHMODE
# define PWM_TIM10_CH2CFG GPIO_TIM10_CH2OUT
# elif CONFIG_STM32_TIM10_CHANNEL == 3
# define PWM_TIM10_PINCFG GPIO_TIM10_CH3OUT
# define CONFIG_STM32_TIM10_CHANNEL3 1
# define CONFIG_STM32_TIM10_CH3MODE CONFIG_STM32_TIM10_CHMODE
# define PWM_TIM10_CH3CFG GPIO_TIM10_CH3OUT
# elif CONFIG_STM32_TIM10_CHANNEL == 4
# define PWM_TIM10_PINCFG GPIO_TIM10_CH4OUT
# define CONFIG_STM32_TIM10_CHANNEL4 1
# define CONFIG_STM32_TIM10_CH4MODE CONFIG_STM32_TIM10_CHMODE
# define PWM_TIM10_CH4CFG GPIO_TIM10_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM10_CHANNEL"
# endif
@ -259,13 +920,21 @@
# if !defined(CONFIG_STM32_TIM11_CHANNEL)
# error "CONFIG_STM32_TIM11_CHANNEL must be provided"
# elif CONFIG_STM32_TIM11_CHANNEL == 1
# define PWM_TIM11_PINCFG GPIO_TIM11_CH1OUT
# define CONFIG_STM32_TIM11_CHANNEL1 1
# define CONFIG_STM32_TIM11_CH1MODE CONFIG_STM32_TIM11_CHMODE
# define PWM_TIM11_CH1CFG GPIO_TIM11_CH1OUT
# elif CONFIG_STM32_TIM11_CHANNEL == 2
# define PWM_TIM11_PINCFG GPIO_TIM11_CH2OUT
# define CONFIG_STM32_TIM11_CHANNEL2 1
# define CONFIG_STM32_TIM11_CH2MODE CONFIG_STM32_TIM11_CHMODE
# define PWM_TIM11_CH2CFG GPIO_TIM11_CH2OUT
# elif CONFIG_STM32_TIM11_CHANNEL == 3
# define PWM_TIM11_PINCFG GPIO_TIM11_CH3OUT
# define CONFIG_STM32_TIM11_CHANNEL3 1
# define CONFIG_STM32_TIM11_CH3MODE CONFIG_STM32_TIM11_CHMODE
# define PWM_TIM11_CH3CFG GPIO_TIM11_CH3OUT
# elif CONFIG_STM32_TIM11_CHANNEL == 4
# define PWM_TIM11_PINCFG GPIO_TIM11_CH4OUT
# define CONFIG_STM32_TIM11_CHANNEL4 1
# define CONFIG_STM32_TIM11_CH4MODE CONFIG_STM32_TIM11_CHMODE
# define PWM_TIM11_CH4CFG GPIO_TIM11_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM11_CHANNEL"
# endif
@ -275,13 +944,21 @@
# if !defined(CONFIG_STM32_TIM12_CHANNEL)
# error "CONFIG_STM32_TIM12_CHANNEL must be provided"
# elif CONFIG_STM32_TIM12_CHANNEL == 1
# define PWM_TIM12_PINCFG GPIO_TIM12_CH1OUT
# define CONFIG_STM32_TIM12_CHANNEL1 1
# define CONFIG_STM32_TIM12_CH1MODE CONFIG_STM32_TIM12_CHMODE
# define PWM_TIM12_CH1CFG GPIO_TIM12_CH1OUT
# elif CONFIG_STM32_TIM12_CHANNEL == 2
# define PWM_TIM12_PINCFG GPIO_TIM12_CH2OUT
# define CONFIG_STM32_TIM12_CHANNEL2 1
# define CONFIG_STM32_TIM12_CH2MODE CONFIG_STM32_TIM12_CHMODE
# define PWM_TIM12_CH2CFG GPIO_TIM12_CH2OUT
# elif CONFIG_STM32_TIM12_CHANNEL == 3
# define PWM_TIM12_PINCFG GPIO_TIM12_CH3OUT
# define CONFIG_STM32_TIM12_CHANNEL3 1
# define CONFIG_STM32_TIM12_CH3MODE CONFIG_STM32_TIM12_CHMODE
# define PWM_TIM12_CH3CFG GPIO_TIM12_CH3OUT
# elif CONFIG_STM32_TIM12_CHANNEL == 4
# define PWM_TIM12_PINCFG GPIO_TIM12_CH4OUT
# define CONFIG_STM32_TIM12_CHANNEL4 1
# define CONFIG_STM32_TIM12_CH4MODE CONFIG_STM32_TIM12_CHMODE
# define PWM_TIM12_CH4CFG GPIO_TIM12_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM12_CHANNEL"
# endif
@ -291,13 +968,21 @@
# if !defined(CONFIG_STM32_TIM13_CHANNEL)
# error "CONFIG_STM32_TIM13_CHANNEL must be provided"
# elif CONFIG_STM32_TIM13_CHANNEL == 1
# define PWM_TIM13_PINCFG GPIO_TIM13_CH1OUT
# define CONFIG_STM32_TIM13_CHANNEL1 1
# define CONFIG_STM32_TIM13_CH1MODE CONFIG_STM32_TIM13_CHMODE
# define PWM_TIM13_CH1CFG GPIO_TIM13_CH1OUT
# elif CONFIG_STM32_TIM13_CHANNEL == 2
# define PWM_TIM13_PINCFG GPIO_TIM13_CH2OUT
# define CONFIG_STM32_TIM13_CHANNEL2 1
# define CONFIG_STM32_TIM13_CH2MODE CONFIG_STM32_TIM13_CHMODE
# define PWM_TIM13_CH2CFG GPIO_TIM13_CH2OUT
# elif CONFIG_STM32_TIM13_CHANNEL == 3
# define PWM_TIM13_PINCFG GPIO_TIM13_CH3OUT
# define CONFIG_STM32_TIM13_CHANNEL3 1
# define CONFIG_STM32_TIM13_CH3MODE CONFIG_STM32_TIM13_CHMODE
# define PWM_TIM13_CH3CFG GPIO_TIM13_CH3OUT
# elif CONFIG_STM32_TIM13_CHANNEL == 4
# define PWM_TIM13_PINCFG GPIO_TIM13_CH4OUT
# define CONFIG_STM32_TIM13_CHANNEL4 1
# define CONFIG_STM32_TIM13_CH4MODE CONFIG_STM32_TIM13_CHMODE
# define PWM_TIM13_CH4CFG GPIO_TIM13_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM13_CHANNEL"
# endif
@ -307,18 +992,70 @@
# if !defined(CONFIG_STM32_TIM14_CHANNEL)
# error "CONFIG_STM32_TIM14_CHANNEL must be provided"
# elif CONFIG_STM32_TIM14_CHANNEL == 1
# define PWM_TIM14_PINCFG GPIO_TIM14_CH1OUT
# define CONFIG_STM32_TIM14_CHANNEL1 1
# define CONFIG_STM32_TIM14_CH1MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH1CFG GPIO_TIM14_CH1OUT
# elif CONFIG_STM32_TIM14_CHANNEL == 2
# define PWM_TIM14_PINCFG GPIO_TIM14_CH2OUT
# define CONFIG_STM32_TIM14_CHANNEL2 1
# define CONFIG_STM32_TIM14_CH2MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH2CFG GPIO_TIM14_CH2OUT
# elif CONFIG_STM32_TIM14_CHANNEL == 3
# define PWM_TIM14_PINCFG GPIO_TIM14_CH3OUT
# define CONFIG_STM32_TIM14_CHANNEL3 1
# define CONFIG_STM32_TIM14_CH3MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH3CFG GPIO_TIM14_CH3OUT
# elif CONFIG_STM32_TIM14_CHANNEL == 4
# define PWM_TIM14_PINCFG GPIO_TIM14_CH4OUT
# define CONFIG_STM32_TIM14_CHANNEL4 1
# define CONFIG_STM32_TIM14_CH4MODE CONFIG_STM32_TIM14_CHMODE
# define PWM_TIM14_CH4CFG GPIO_TIM14_CH4OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM14_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32_TIM15_PWM
# if !defined(CONFIG_STM32_TIM15_CHANNEL)
# error "CONFIG_STM32_TIM15_CHANNEL must be provided"
# elif CONFIG_STM32_TIM15_CHANNEL == 1
# define CONFIG_STM32_TIM15_CHANNEL1 1
# define CONFIG_STM32_TIM15_CH1MODE CONFIG_STM32_TIM15_CHMODE
# define PWM_TIM15_CH1CFG GPIO_TIM15_CH1OUT
# elif CONFIG_STM32_TIM15_CHANNEL == 2
# define CONFIG_STM32_TIM15_CHANNEL2 1
# define CONFIG_STM32_TIM15_CH2MODE CONFIG_STM32_TIM15_CHMODE
# define PWM_TIM15_CH2CFG GPIO_TIM15_CH2OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM15_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32_TIM16_PWM
# if !defined(CONFIG_STM32_TIM16_CHANNEL)
# error "CONFIG_STM32_TIM16_CHANNEL must be provided"
# elif CONFIG_STM32_TIM16_CHANNEL == 1
# define CONFIG_STM32_TIM16_CHANNEL1 1
# define CONFIG_STM32_TIM16_CH1MODE CONFIG_STM32_TIM16_CHMODE
# define PWM_TIM16_CH1CFG GPIO_TIM16_CH1OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM16_CHANNEL"
# endif
#endif
#ifdef CONFIG_STM32_TIM17_PWM
# if !defined(CONFIG_STM32_TIM17_CHANNEL)
# error "CONFIG_STM32_TIM17_CHANNEL must be provided"
# elif CONFIG_STM32_TIM17_CHANNEL == 1
# define CONFIG_STM32_TIM17_CHANNEL1 1
# define CONFIG_STM32_TIM17_CH1MODE CONFIG_STM32_TIM17_CHMODE
# define PWM_TIM17_CH1CFG GPIO_TIM17_CH1OUT
# else
# error "Unsupported value of CONFIG_STM32_TIM17_CHANNEL"
# endif
#endif
#define PWM_NCHANNELS 1
#endif
/************************************************************************************
* Public Types
************************************************************************************/
@ -351,7 +1088,7 @@ extern "C"
* Input Parameters:
* timer - A number identifying the timer use. The number of valid timer
* IDs varies with the STM32 MCU and MCU family but is somewhere in
* the range of {1,..,14}.
* the range of {1,..,17}.
*
* Returned Value:
* On success, a pointer to the STM32 lower half PWM driver is returned.

4
arch/arm/src/stm32f7/stm32_allocateheap.c
View File

@ -240,7 +240,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -255,7 +255,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = SRAM1_END - g_idle_topstack;

6
arch/arm/src/str71x/str71x_decodeirq.c
View File

@ -90,7 +90,7 @@
void up_decodeirq(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
lowsyslog(LOG_ERR, "Unexpected IRQ\n");
current_regs = regs;
PANIC();
@ -101,7 +101,7 @@ void up_decodeirq(uint32_t *regs)
* info from CIC register without the setup).
*/
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
irq = getreg32(STR71X_EIC_IVR);
/* Verify that the resulting IRQ number is valid */
@ -138,6 +138,6 @@ void up_decodeirq(uint32_t *regs)
PANIC(); /* Normally never happens */
}
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
#endif
}

229
arch/arm/src/str71x/str71x_head.S
View File

@ -37,11 +37,11 @@
* Included Files
*****************************************************************************/
#include <nuttx/config.h> /* NuttX configuration settings */
#include <nuttx/config.h> /* NuttX configuration settings */
#include <arch/board/board.h> /* Board-specific settings */
#include "arm.h" /* ARM-specific settings */
#include "chip.h" /* Chip-specific settings */
#include "arm.h" /* ARM-specific settings */
#include "chip.h" /* Chip-specific settings */
#include "up_internal.h"
#include "up_arch.h"
@ -59,18 +59,18 @@
* External references
*****************************************************************************/
.globl str71x_prccuinit /* Clock initialization */
.globl up_lowsetup /* Early initialization of UART */
.globl str71x_prccuinit /* Clock initialization */
.globl up_lowsetup /* Early initialization of UART */
#ifdef USE_EARLYSERIALINIT
.globl up_earlyserialinit /* Early initialization of serial driver */
.globl up_earlyserialinit /* Early initialization of serial driver */
#endif
#ifdef CONFIG_ARCH_LEDS
.globl board_led_initialize /* Boot LED setup */
.globl board_autoled_initialize /* Boot LED setup */
#endif
#ifdef CONFIG_DEBUG
.globl up_lowputc /* Low-level debug output */
.globl up_lowputc /* Low-level debug output */
#endif
.globl os_start /* NuttX entry point */
.globl os_start /* NuttX entry point */
/*****************************************************************************
* Macros
@ -87,8 +87,8 @@
.macro showprogress, code
#ifdef CONFIG_DEBUG
mov r0, #\code
bl up_lowputc
mov r0, #\code
bl up_lowputc
#endif
.endm
@ -107,32 +107,32 @@
/* In order to use the external memory, certain GPIO pins must be
* configured in the alternate function:
*
* GPIO ALT Description
* GPIO ALT Description
* P2.0-3 CS.0-3 External memory chip select for banks 0,1,3,4
* P2.4-7 A.20-23 External memory extended address bus (needed for
* address space > 1Mb)
*/
#ifdef CONFIG_STR71X_BIGEXTMEM
# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */
# define EXTMEM_GPIO_BITSET 0x000000ff /* P2.0-7 */
#else
# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */
# define EXTMEM_GPIO_BITSET 0x0000000f /* P2.0-3 */
#endif
ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode
ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC0_OFFSET]
ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC1_OFFSET]
ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC2_OFFSET]
ldr \base, =STR71X_GPIO_BASE ; Configure P2.0 to P2.3/7 in AF_PP mode
ldr \value, [\base, #STR71X_GPIO_PC0_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC0_OFFSET]
ldr \value, [\base, #STR71X_GPIO_PC1_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC1_OFFSET]
ldr \value, [\base, #STR71X_GPIO_PC2_OFFSET]
orr \value, \value, #EXTMEM_GPIO_BITSET
str \value, [\base, #STR71X_GPIO_PC2_OFFSET]
/* Enable bank 0 */
ldr \base, =STR71X_EMI_BASE
ldr \base, =STR71X_EMI_BASE
#ifdef CONFIG_STR71X_BANK0
@ -156,11 +156,11 @@
# define EXTMEM_BANK0_WAITSTATES (CONFIG_STR71X_BANK0_WAITSTATES << 2)
# endif
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE)
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK0_WAITSTATES|EXTMEM_BANK0_SIZE)
#else
mov \value, #0
mov \value, #0
#endif
str \value, [\base, #STR71X_EMI_BCON0_OFFSET]
str \value, [\base, #STR71X_EMI_BCON0_OFFSET]
/* Enable bank 1 */
@ -186,11 +186,11 @@
# define EXTMEM_BANK1_WAITSTATES (CONFIG_STR71X_BANK1_WAITSTATES << 2)
# endif
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE)
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK1_WAITSTATES|EXTMEM_BANK1_SIZE)
#else
mov \value, #0
mov \value, #0
#endif
str \value, [\base, #STR71X_EMI_BCON1_OFFSET]
str \value, [\base, #STR71X_EMI_BCON1_OFFSET]
/* Enable bank 2 */
@ -216,11 +216,11 @@
# define EXTMEM_BANK2_WAITSTATES (CONFIG_STR71X_BANK2_WAITSTATES << 2)
# endif
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE)
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK2_WAITSTATES|EXTMEM_BANK2_SIZE)
#else
mov \value, #0
mov \value, #0
#endif
str \value, [\base, #STR71X_EMI_BCON2_OFFSET]
str \value, [\base, #STR71X_EMI_BCON2_OFFSET]
/* Enable bank 3 */
@ -246,11 +246,11 @@
# define EXTMEM_BANK3_WAITSTATES (CONFIG_STR71X_BANK3_WAITSTATES << 2)
# endif
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE)
ldr \value, =(STR71X_EMIBCON_ENABLE|EXTMEM_BANK3_WAITSTATES|EXTMEM_BANK3_SIZE)
#else
mov \value, #0
mov \value, #0
#endif
str \value, [\base, #STR71X_EMI_BCON3_OFFSET]
str \value, [\base, #STR71X_EMI_BCON3_OFFSET]
#endif
.endm
@ -277,42 +277,42 @@
.macro eicinit, eicbase, value, irqno, offset
/* Disable and clear all interrupts */
ldr \eicbase, =STR71X_EIC_BASE
ldr \eicbase, =STR71X_EIC_BASE
/* Disable FIQ and IRQ */
mov \value, #0
str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET]
mov \value, #0
str \value, [\eicbase, #STR71X_EIC_ICR_OFFSET]
/* Disable all channel interrupts */
str \value, [\eicbase, #STR71X_EIC_IER_OFFSET]
str \value, [\eicbase, #STR71X_EIC_IER_OFFSET]
/* Clear all pending IRQs */
ldr \value, =0xffffffff
str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET]
ldr \value, =0xffffffff
str \value, [\eicbase, #STR71X_EIC_IPR_OFFSET]
/* Disable FIQ channels/clear pending FIQs */
mov \value, #0x0c
str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET]
mov \value, #0x0c
str \value, [\eicbase, #STR71X_EIC_FIR_OFFSET]
/* Reset the current priority register */
mov \value, #0
str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET]
mov \value, #0
str \value, [\eicbase, #STR71X_EIC_CIPR_OFFSET]
/* Zero IVR 31:16 */
str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET]
str \value, [\eicbase, #STR71X_EIC_IVR_OFFSET]
/* Set up the loop to initialize each SIR register. Start
* with IRQ number 0 and SIR0
*/
mov \irqno, #0
ldr \offset, =STR71X_EIC_SIR_OFFSET
mov \irqno, #0
ldr \offset, =STR71X_EIC_SIR_OFFSET
/* Then loop for each EIC channel */
eicloop:
@ -325,22 +325,22 @@ eicloop:
* are all disabled.
*/
mov \value, \irqno, lsl #16
str \value, [\eicbase, \offset]
mov \value, \irqno, lsl #16
str \value, [\eicbase, \offset]
/* Increment the offset to the next SIR register and inrement
* the IRQ number.
*/
add \offset, \offset, #4
add \irqno, \irqno, #1
add \offset, \offset, #4
add \irqno, \irqno, #1
/* Continue to loop until all of the SIR registers have been
* initializeed.
*/
cmp \irqno, #STR71X_EIC_NCHANNELS
blt eicloop
cmp \irqno, #STR71X_EIC_NCHANNELS
blt eicloop
.endm
/*****************************************************************************
@ -355,25 +355,26 @@ eicloop:
#ifndef CONFIG_STR71X_DISABLE_PERIPHINIT
/* Set up APB1 and APB2 addresses */
ldr \base1, =STR71X_APB1_BASE
ldr \base2, =STR71X_APB2_BASE
ldr \base1, =STR71X_APB1_BASE
ldr \base2, =STR71X_APB2_BASE
/* Disable all APB1 peripherals */
ldr \value, =STR71X_APB1_APB1ALL
ldr \value, =STR71X_APB1_APB1ALL
strh \value, [\base1, #STR71X_APB_CKDIS_OFFSET]
/* Disable all(or most) APB2 peripherals */
ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC)
ldr \value, =(STR71X_APB2_APB2ALL & ~STR71X_APB2_EIC)
strh \value, [\base2, #STR71X_APB_CKDIS_OFFSET]
/* Allow EMI and USB */
ldr \base1, =STR71X_RCCU_BASE
ldr \base1, =STR71X_RCCU_BASE
#ifdef CONFIG_STR71X_USB
ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL)
ldr \value, =(STR71X_RCCUPER_EMI|STR71X_RCCUPER_USBKERNEL)
#else
ldr \value, =STR71X_RCCUPER_EMI
ldr \value, =STR71X_RCCUPER_EMI
#endif
strh \value, [\base1, #STR71X_RCCU_PER_OFFSET]
#endif
@ -391,15 +392,16 @@ eicloop:
*****************************************************************************/
.macro remap, base, value
/* Read the PCU BOOTCR register */
ldr \base, =STR71X_PCU_BASE
ldr \base, =STR71X_PCU_BASE
ldrh \value, [\base, #STR71X_PCU_BOOTCR_OFFSET]
/* Mask out the old boot mode bits and set the boot mode to FLASH */
bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK
orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH
bic \value, \value, #STR71X_PCUBOOTCR_BOOTMASK
orr \value, \value, #STR71X_PCUBOOTCR_BMFLASH
/* Save the modified BOOTCR register */
@ -426,16 +428,16 @@ eicloop:
.globl _vector_table
.type _vector_table, %function
_vector_table:
ldr pc, .Lresethandler /* 0x00: Reset */
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
ldr pc, .Lswihandler /* 0x08: Software interrupt */
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
.long 0 /* 0x14: Reserved vector */
ldr pc, .Lirqhandler /* 0x18: IRQ */
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
ldr pc, .Lresethandler /* 0x00: Reset */
ldr pc, .Lundefinedhandler /* 0x04: Undefined instruction */
ldr pc, .Lswihandler /* 0x08: Software interrupt */
ldr pc, .Lprefetchaborthandler /* 0x0c: Prefetch abort */
ldr pc, .Ldataaborthandler /* 0x10: Data abort */
.long 0 /* 0x14: Reserved vector */
ldr pc, .Lirqhandler /* 0x18: IRQ */
ldr pc, .Lfiqhandler /* 0x1c: FIQ */
.globl __start
.globl __start
.globl up_vectorundefinsn
.globl up_vectorswi
.globl up_vectorprefetch
@ -444,7 +446,7 @@ _vector_table:
.globl up_vectorfiq
.Lresethandler:
.long __start
.long __start
.Lundefinedhandler:
.long up_vectorundefinsn
.Lswihandler:
@ -478,16 +480,16 @@ __start:
* the aliased copy
*/
ldr pc, =__flashstart
ldr pc, =__flashstart
__flashstart:
.rept 9
nop /* Wait for OSC stabilization*/
nop /* Wait for OSC stabilization */
.endr
/* Setup the initial processor mode */
mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
mov r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
msr cpsr, r0
/* Initialize the external memory interface (EMI) */
@ -499,7 +501,7 @@ __flashstart:
/* Disable all peripherals except EIC */
periphinit r0, r1, r2
periphinit r0, r1, r2
/* Map memory appropriately for configuration */
@ -507,42 +509,42 @@ __flashstart:
/* Setup system stack (and get the BSS range) */
adr r0, LC0
ldmia r0, {r4, r5, sp}
adr r0, LC0
ldmia r0, {r4, r5, sp}
/* Clear system BSS section */
mov r0, #0
1: cmp r4, r5
mov r0, #0
1: cmp r4, r5
strcc r0, [r4], #4
bcc 1b
bcc 1b
/* Copy system .data sections from FLASH to new home in RAM. */
adr r3, LC2
adr r3, LC2
ldmia r3, {r0, r1, r2}
2: ldmia r0!, {r3 - r10}
stmia r1!, {r3 - r10}
cmp r1, r2
blt 2b
cmp r1, r2
blt 2b
/* Initialize clocking */
bl str71x_prccuinit
bl str71x_prccuinit
/* Configure the uart so that we can get debug output as soon
* as possible.
*/
bl up_lowsetup
bl up_lowsetup
showprogress 'A'
/* Perform early serial initialization */
mov fp, #0
mov fp, #0
#ifdef USE_EARLYSERIALINIT
bl up_earlyserialinit
bl up_earlyserialinit
#endif
showprogress 'B'
@ -550,17 +552,17 @@ __flashstart:
/* Call C++ constructors */
#ifdef CONFIG_CPLUSPLUS
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ldr r0, =__ctors_start__
ldr r1, =__ctors_end__
ctor_loop:
cmp r0, r1
beq ctor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r1}
mov lr, pc
mov pc, r2
ldmfd sp!, {r0-r1}
b ctor_loop
cmp r0, r1
beq ctor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r1}
mov lr, pc
mov pc, r2
ldmfd sp!, {r0-r1}
b ctor_loop
ctor_end:
showprogress 'C'
@ -570,27 +572,27 @@ ctor_end:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
bl board_led_initialize
bl board_autoled_initialize
#endif
/* Then jump to OS entry */
b os_start
b os_start
/* Call destructors -- never get here */
#if 0 /* CONFIG_CPLUSPLUS */
ldr r0, =__dtors_start__
ldr r1, =__dtors_end__
ldr r0, =__dtors_start__
ldr r1, =__dtors_end__
dtor_loop:
cmp r0, r1
beq dtor_end
ldr r2, [r0], #4
cmp r0, r1
beq dtor_end
ldr r2, [r0], #4
stmfd sp!, {r0-r1}
mov lr, pc
mov pc, r2
mov lr, pc
mov pc, r2
ldmfd sp!, {r0-r1}
b dtor_loop
b dtor_loop
dtor_end:
#endif
@ -626,4 +628,3 @@ g_idle_topstack:
.size g_idle_topstack, .-g_idle_topstack
.end

4
arch/arm/src/tiva/tiva_allocateheap.c
View File

@ -131,7 +131,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the user-space heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)ubase;
*heap_size = usize;
@ -142,7 +142,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Return the heap settings */
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
#endif

2
arch/avr/src/avr/up_createstack.c
View File

@ -160,7 +160,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (FAR void *)top_of_stack;
tcb->adj_stack_size = stack_size;
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

4
arch/avr/src/avr/up_doirq.c
View File

@ -72,7 +72,7 @@
uint8_t *up_doirq(uint8_t irq, uint8_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -112,7 +112,7 @@ uint8_t *up_doirq(uint8_t irq, uint8_t *regs)
current_regs = savestate;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

4
arch/avr/src/avr/up_sigdeliver.c
View File

@ -92,7 +92,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -147,7 +147,7 @@ void up_sigdeliver(void)
* to the size of register save structure size will protect its contents.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

2
arch/avr/src/avr32/up_createstack.c
View File

@ -186,7 +186,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (FAR void *)top_of_stack;
tcb->adj_stack_size = size_of_stack;
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

4
arch/avr/src/avr32/up_doirq.c
View File

@ -74,7 +74,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -133,7 +133,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
current_regs = NULL;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

4
arch/avr/src/avr32/up_sigdeliver.c
View File

@ -96,7 +96,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -150,7 +150,7 @@ void up_sigdeliver(void)
* to the size of register save structure size will protect its contents.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

2
arch/avr/src/common/up_allocateheap.c
View File

@ -82,7 +82,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

6
arch/avr/src/common/up_assert.c
View File

@ -111,9 +111,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -163,7 +163,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

2
arch/avr/src/common/up_initialize.c
View File

@ -286,6 +286,6 @@ void up_initialize(void)
up_usbinitialize();
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}

2
arch/hc/src/common/up_allocateheap.c
View File

@ -81,7 +81,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

2
arch/hc/src/common/up_createstack.c
View File

@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

4
arch/hc/src/common/up_doirq.c
View File

@ -74,7 +74,7 @@
uint8_t *up_doirq(int irq, uint8_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -133,6 +133,6 @@ uint8_t *up_doirq(int irq, uint8_t *regs)
current_regs = NULL;
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

2
arch/hc/src/common/up_initialize.c
View File

@ -210,5 +210,5 @@ void up_initialize(void)
up_usbinitialize();
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}

6
arch/hc/src/m9s12/m9s12_assert.c
View File

@ -299,9 +299,9 @@ static void _up_assert(int errorcode)
for (;;)
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -326,7 +326,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

2
arch/mips/src/common/up_allocateheap.c
View File

@ -82,7 +82,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void *)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

2
arch/mips/src/common/up_createstack.c
View File

@ -206,7 +206,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (FAR uint32_t *)top_of_stack;
tcb->adj_stack_size = size_of_stack;
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

2
arch/mips/src/common/up_initialize.c
View File

@ -211,5 +211,5 @@ void up_initialize(void)
/* Initialize USB -- device and/or host */
up_usbinitialize();
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}

6
arch/mips/src/mips32/up_assert.c
View File

@ -111,9 +111,9 @@ static void _up_assert(int errorcode)
for (; ; )
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -163,7 +163,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s *)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

4
arch/mips/src/mips32/up_doirq.c
View File

@ -74,7 +74,7 @@
uint32_t *up_doirq(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -143,6 +143,6 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
up_enable_irq(irq);
#endif
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return regs;
}

4
arch/mips/src/mips32/up_sigdeliver.c
View File

@ -94,7 +94,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -136,7 +136,7 @@ void up_sigdeliver(void)
* execution.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
/* up_fullcontextrestore() should not return but could if the software

6
arch/mips/src/pic32mx/pic32mx-decodeirq.c
View File

@ -97,7 +97,7 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
* processing an interrupt.
*/
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
/* Save the current value of current_regs (to support nested interrupt
* handling). Then set current_regs to regs, indicating that this is
@ -189,11 +189,11 @@ uint32_t *pic32mx_decodeirq(uint32_t *regs)
current_regs = savestate;
if (current_regs == NULL)
{
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
}
#else
current_regs = NULL;
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
#endif
return regs;

2
arch/mips/src/pic32mx/pic32mx-exception.c
View File

@ -94,7 +94,7 @@ uint32_t *pic32mx_exception(uint32_t *regs)
* processing an interrupt.
*/
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_DEBUG
/* Get the cause of the exception from the CAUSE register */

6
arch/mips/src/pic32mz/pic32mz-decodeirq.c
View File

@ -97,7 +97,7 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
* processing an interrupt.
*/
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
/* Save the current value of current_regs (to support nested interrupt
* handling). Then set current_regs to regs, indicating that this is
@ -189,11 +189,11 @@ uint32_t *pic32mz_decodeirq(uint32_t *regs)
current_regs = savestate;
if (current_regs == NULL)
{
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
}
#else
current_regs = NULL;
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
#endif
return regs;

2
arch/mips/src/pic32mz/pic32mz-exception.c
View File

@ -94,7 +94,7 @@ uint32_t *pic32mz_exception(uint32_t *regs)
* processing an interrupt.
*/
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_DEBUG
/* Get the cause of the exception from the CAUSE register */

2
arch/sh/src/common/up_allocateheap.c
View File

@ -81,7 +81,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

6
arch/sh/src/common/up_assert.c
View File

@ -99,9 +99,9 @@ static void _up_assert(int errorcode)
for (;;)
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -151,7 +151,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#if CONFIG_TASK_NAME_SIZE > 0
lldbg("Assertion failed at file:%s line: %d task: %s\n",

2
arch/sh/src/common/up_createstack.c
View File

@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

4
arch/sh/src/common/up_doirq.c
View File

@ -73,7 +73,7 @@
uint32_t *up_doirq(int irq, uint32_t* regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -133,7 +133,7 @@ uint32_t *up_doirq(int irq, uint32_t* regs)
current_regs = NULL;
}
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
#endif
return regs;
}

2
arch/sh/src/common/up_initialize.c
View File

@ -200,5 +200,5 @@ void up_initialize(void)
up_usbinitialize();
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}

72
arch/sh/src/m16c/m16c_head.S
View File

@ -60,8 +60,8 @@
.macro showprogress, code
#ifdef CONFIG_DEBUG
.globl _up_lowputc
mov.b r#\code1l /* Character to print */
jsr.a _up_lowputc /* Print it */
mov.b r#\code1l /* Character to print */
jsr.a _up_lowputc /* Print it */
#endif
.endm
@ -71,11 +71,11 @@
/* The near RAM memory map is as follows:
*
* 0x00400 - DATA Size: Determined by linker
* BSS Size: Determined by linker
* 0x00400 - DATA Size: Determined by linker
* BSS Size: Determined by linker
* Interrupt stack Size: CONFIG_ARCH_INTERRUPTSTACK
* Idle stack Size: CONFIG_IDLETHREAD_STACKSIZE
* Heap Size: Everything remaining
* Idle stack Size: CONFIG_IDLETHREAD_STACKSIZE
* Heap Size: Everything remaining
* 0x00bff - (end+1)
*/
@ -174,48 +174,48 @@ __start:
/* Set the interrupt and user stack pointers */
mov.w #_enbss, R0
ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */
ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */
add.w #CONFIG_IDLETHREAD_STACKSIZE, R0
fset U /* Set bit 7 (U) to select the user stack pointer */
ldc R0, sp /* Set the user stack pointer */
fset U /* Set bit 7 (U) to select the user stack pointer */
ldc R0, sp /* Set the user stack pointer */
/* Set BCLK speed. At reset, the processor clock (BLCK) defaults to a divisor of 8.
* This sets clock to F1 (divide by 1) on XIN: BCLK = XIN frequency.
*/
mov.b #0x01, M16C_PRCR /* Unprotect CM0 to change clock setting */
mov.b #0x08, M16C_CM0 /* enable CM17 and CM16 to set BCLK to F1
* CM17 & CM16 defaults to 0 after reset and
* so we only need to reset CM06 to 0 */
mov.b #0x00,M16C_PRCR /* protect CM0 */
mov.b #0x01, M16C_PRCR /* Unprotect CM0 to change clock setting */
mov.b #0x08, M16C_CM0 /* enable CM17 and CM16 to set BCLK to F1
* CM17 & CM16 defaults to 0 after reset and
* so we only need to reset CM06 to 0 */
mov.b #0x00,M16C_PRCR /* protect CM0 */
/* The two MS bits of the interrupt cause select register must be set to
* enable the use of INT4 and INT5
*/
mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */
ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */
mov.b #0xc0, M16C_IFSR /* Set b7 & b6 if application will use INT4 & INT5 */
ldc #M16C_IRAM_BASE, sb /* Set sb register (to what?) */
/* Set up INTB to point to location of variable vector table */
mov.w _g_svarvect, r0 /* R0 = lower 16-bits */
mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */
ldc r1, intbh
ldc r0, intbl
mov.w _g_svarvect, r0 /* R0 = lower 16-bits */
mov.w _g_svarvect+2, r1 /* R1 = upper 4-bits */
ldc r1, intbh
ldc r0, intbl
/* Configure the uart so that we can get debug output as soon as possible. */
.globl _up_lowsetup /* Early initialization of UART */
.globl _up_lowsetup /* Early initialization of UART */
jsr.a _up_lowsetup
showprogress 'A'
/* Clear near .bss sections */
mov.b #0x00, r0l /* r0l: 0 */
mov.w _g_snbss, a1 /* a1: start of near .bss */
mov.w _g_enbss, r3 /* r3: end of near .bss */
sub.w a1, r3 /* r3: size of near .bss */
sstr.b /* Clear near .bss */
mov.b #0x00, r0l /* r0l: 0 */
mov.w _g_snbss, a1 /* a1: start of near .bss */
mov.w _g_enbss, r3 /* r3: end of near .bss */
sub.w a1, r3 /* r3: size of near .bss */
sstr.b /* Clear near .bss */
/* Clear far .bss sections */
@ -227,12 +227,12 @@ __start:
/* Initialize near .data sections (.rodata is not moved) */
mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */
mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */
mov.w _g_sndata, a1 /* a1: start of near .data */
mov.w _g_endata, r3 /* r3: end of near .data */
sub.w a1, r3 /* r3: size of near .data */
smovf.b /* Copy source to near .data */
mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */
mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */
mov.w _g_sndata, a1 /* a1: start of near .data */
mov.w _g_endata, r3 /* r3: end of near .data */
sub.w a1, r3 /* r3: size of near .data */
smovf.b /* Copy source to near .data */
/* Initialize far .data sections (.rodata is not moved) */
@ -245,8 +245,8 @@ __start:
/* Perform early console initialization */
#ifdef USE_EARLYSERIALINIT
.globl _up_earlyconsoleinit /* Early initialization of console driver */
jsr.a _up_earlyconsoleinit /* Call it */
.globl _up_earlyconsoleinit /* Early initialization of console driver */
jsr.a _up_earlyconsoleinit /* Call it */
showprogress 'D'
#endif
@ -260,8 +260,8 @@ __start:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
.globl _board_led_initialize /* Boot LED setup */
jsr.a _board_led_initialize /* Call it */
.globl _board_autoled_initialize /* Boot LED setup */
jsr.a _board_autoled_initialize /* Call it */
#endif
showprogress '\n'

4
arch/sh/src/m16c/m16c_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -136,7 +136,7 @@ void up_sigdeliver(void)
* execution.
*/
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
#endif
}

288
arch/sh/src/sh1/sh1_head.S
View File

@ -60,31 +60,32 @@
/* Called functions */
.globl _up_lowsetup /* Early initialization of UART */
.globl _up_lowsetup /* Early initialization of UART */
#ifdef USE_EARLYSERIALINIT
.globl _up_earlyconsoleinit /* Early initialization of console driver */
.globl _up_earlyconsoleinit /* Early initialization of console driver */
#endif
#ifdef CONFIG_ARCH_LEDS
.globl _board_led_initialize /* Boot LED setup */
.globl _board_autoled_initialize /* Boot LED setup */
#endif
#ifdef CONFIG_DEBUG
.globl _up_lowputc /* Low-level debug output */
.globl _up_lowputc /* Low-level debug output */
#endif
.globl _os_start /* NuttX entry point */
.globl _os_start /* NuttX entry point */
/* Variables set up by the linker script */
.globl _sbss /* Start of BSS */
.globl _ebss /* End of BSS */
.globl _svect /* Start of the new vector location */
.globl _sbss /* Start of BSS */
.globl _ebss /* End of BSS */
.globl _svect /* Start of the new vector location */
#ifdef CONFIG_BOOT_RUNFROMFLASH
.globl _eronly /* Where .data defaults are stored in FLASH */
.global _sdata /* Start of .data in RAM */
.globl _edata /* End of .data in RAM */
.globl _eronly /* Where .data defaults are stored in FLASH */
.global _sdata /* Start of .data in RAM */
.globl _edata /* End of .data in RAM */
#endif
/* Interrupt handlers */
.globl _up_invalid_handler
#ifdef CONFIG_SH1_DMAC0
.globl _up_dmac0_handler
@ -161,9 +162,9 @@
.macro showprogress, code
#ifdef CONFIG_DEBUG
mov.l .Llowputc, r0 /* Address of up_earlyconsoleinit */
jsr @r0 /* Call it */
mov #\code, r4 /* Delay slot */
mov.l .Llowputc, r0 /* Address of up_earlyconsoleinit */
jsr @r0 /* Call it */
mov #\code, r4 /* Delay slot */
#endif
.endm
@ -191,128 +192,128 @@ __vector_table:
* vectors.
*/
.long __start /* 0-1: Power-on reset (hard, NMI high) PC & SP */
.long __start /* 0-1: Power-on reset (hard, NMI high) PC & SP */
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
.long __start /* 2-3: Manual reset (soft, NMI low) PC & SP */
.long __start /* 2-3: Manual reset (soft, NMI low) PC & SP */
.long _ebss+CONFIG_IDLETHREAD_STACKSIZE-4
.rept SH1_NCMN_VECTORS-4
.rept SH1_NCMN_VECTORS-4
.long _up_invalid_handler
.endr
/* The remaining vectors are unique to the SH-1 703x family */
#ifdef CONFIG_SH1_DMAC0
.long _up_dmac0_handler /* 72: DMAC0 DEI0 */
.long _up_dmac0_handler /* 72: DMAC0 DEI0 */
#else
.long _up_invalid_handler /* 72: DMAC0 DEI0 */
.long _up_invalid_handler /* 72: DMAC0 DEI0 */
#endif
.long _up_invalid_handler /* 73: Reserved */
.long _up_invalid_handler /* 73: Reserved */
#ifdef CONFIG_SH1_DMAC1
.long _up_dmac1_handler /* 74: DMAC1 DEI1 */
.long _up_dmac1_handler /* 74: DMAC1 DEI1 */
#else
.long _up_invalid_handler /* 74: DMAC1 DEI1 */
.long _up_invalid_handler /* 74: DMAC1 DEI1 */
#endif
.long _up_invalid_handler /* 75: Reserved */
.long _up_invalid_handler /* 75: Reserved */
#ifdef CONFIG_SH1_DMAC2
.long _up_dmac2_handler /* 76: DMAC2 DEI2 */
.long _up_dmac2_handler /* 76: DMAC2 DEI2 */
#else
.long _up_invalid_handler /* 76: DMAC2 DEI2 */
.long _up_invalid_handler /* 76: DMAC2 DEI2 */
#endif
.long _up_invalid_handler /* 77: Reserved */
.long _up_invalid_handler /* 77: Reserved */
#ifdef CONFIG_SH1_DMAC3
.long _up_dmac3_handler /* 78: DMAC3 DEI3 */
.long _up_dmac3_handler /* 78: DMAC3 DEI3 */
#else
.long _up_invalid_handler /* 78: DMAC3 DEI3 */
.long _up_invalid_handler /* 78: DMAC3 DEI3 */
#endif
.long _up_invalid_handler /* 79: Reserved */
.long _up_imia0_handler /* 80: ITU0 IMIA0 */
.long _up_imib0_handler /* 81: IMIB0 */
.long _up_ovi0_handler /* 82: OVI0 */
.long _up_invalid_handler /* 83: Reserved */
.long _up_invalid_handler /* 79: Reserved */
.long _up_imia0_handler /* 80: ITU0 IMIA0 */
.long _up_imib0_handler /* 81: IMIB0 */
.long _up_ovi0_handler /* 82: OVI0 */
.long _up_invalid_handler /* 83: Reserved */
#ifdef CONFIG_SH1_ITU1
.long _up_imia1_handler /* 84: ITU1 IMIA1 */
.long _up_imib1_handler /* 85: IMIB1 */
.long _up_ovi1_handler /* 86: OVI1 */
.long _up_imia1_handler /* 84: ITU1 IMIA1 */
.long _up_imib1_handler /* 85: IMIB1 */
.long _up_ovi1_handler /* 86: OVI1 */
#else
.long _up_invalid_handler /* 84: ITU1 IMIA1 */
.long _up_invalid_handler /* 85: IMIB1 */
.long _up_invalid_handler /* 86: OVI1 */
.long _up_invalid_handler /* 84: ITU1 IMIA1 */
.long _up_invalid_handler /* 85: IMIB1 */
.long _up_invalid_handler /* 86: OVI1 */
#endif
.long _up_invalid_handler /* 87: Reserved */
.long _up_invalid_handler /* 87: Reserved */
#ifdef CONFIG_SH1_ITU2
.long _up_imia2_handler /* 88: ITU2 IMIA2 */
.long _up_imib2_handler /* 89: IMIB2 */
.long _up_ovi2_handler /* 90: OVI2 */
.long _up_imia2_handler /* 88: ITU2 IMIA2 */
.long _up_imib2_handler /* 89: IMIB2 */
.long _up_ovi2_handler /* 90: OVI2 */
#else
.long _up_invalid_handler /* 88: ITU2 IMIA2 */
.long _up_invalid_handler /* 89: IMIB2 */
.long _up_invalid_handler /* 90: OVI2 */
.long _up_invalid_handler /* 88: ITU2 IMIA2 */
.long _up_invalid_handler /* 89: IMIB2 */
.long _up_invalid_handler /* 90: OVI2 */
#endif
.long _up_invalid_handler /* 91: Reserved */
.long _up_invalid_handler /* 91: Reserved */
#ifdef CONFIG_SH1_ITU3
.long _up_imia3_handler /* 92: ITU3 IMIA3 */
.long _up_imib3_handler /* 93: IMIB3 */
.long _up_ovi3_handler /* 94: OVI3 */
.long _up_imia3_handler /* 92: ITU3 IMIA3 */
.long _up_imib3_handler /* 93: IMIB3 */
.long _up_ovi3_handler /* 94: OVI3 */
#else
.long _up_invalid_handler /* 92: ITU3 IMIA3 */
.long _up_invalid_handler /* 93: IMIB3 */
.long _up_invalid_handler /* 94: OVI3 */
.long _up_invalid_handler /* 92: ITU3 IMIA3 */
.long _up_invalid_handler /* 93: IMIB3 */
.long _up_invalid_handler /* 94: OVI3 */
#endif
.long _up_invalid_handler /* 95: Reserved */
.long _up_invalid_handler /* 95: Reserved */
#ifdef CONFIG_SH1_ITU4
.long _up_imia4_handler /* 96: ITU4 IMIA4 */
.long _up_imib4_handler /* 97: IMIB4 */
.long _up_ovi4_handler /* 98: OVI4 */
.long _up_imia4_handler /* 96: ITU4 IMIA4 */
.long _up_imib4_handler /* 97: IMIB4 */
.long _up_ovi4_handler /* 98: OVI4 */
#else
.long _up_invalid_handler /* 96: ITU4 IMIA4 */
.long _up_invalid_handler /* 97: IMIB4 */
.long _up_invalid_handler /* 98: OVI4 */
.long _up_invalid_handler /* 96: ITU4 IMIA4 */
.long _up_invalid_handler /* 97: IMIB4 */
.long _up_invalid_handler /* 98: OVI4 */
#endif
.long _up_invalid_handler /* 99: Reserved */
.long _up_invalid_handler /* 99: Reserved */
#ifdef CONFIG_SH1_SCI0
.long _up_eri0_handler /* 100: SCI0 ERI0 */
.long _up_rxi0_handler /* 101: RxI0 */
.long _up_txi0_handler /* 102: TxI0 */
.long _up_tei0_handler /* 103: TEI0 */
.long _up_eri0_handler /* 100: SCI0 ERI0 */
.long _up_rxi0_handler /* 101: RxI0 */
.long _up_txi0_handler /* 102: TxI0 */
.long _up_tei0_handler /* 103: TEI0 */
#else
.long _up_invalid_handler /* 100: SCI0 ERI0 */
.long _up_invalid_handler /* 101: RxI0 */
.long _up_invalid_handler /* 102: TxI0 */
.long _up_invalid_handler /* 103: TEI0 */
.long _up_invalid_handler /* 100: SCI0 ERI0 */
.long _up_invalid_handler /* 101: RxI0 */
.long _up_invalid_handler /* 102: TxI0 */
.long _up_invalid_handler /* 103: TEI0 */
#endif
#ifdef CONFIG_SH1_SCI1
.long _up_eri1_handler /* 104: SCI1 ERI1 */
.long _up_rxi1_handler /* 105: RxI1 */
.long _up_txi1_handler /* 106: TxI1 */
.long _up_tei1_handler /* 107: TEI1 */
.long _up_eri1_handler /* 104: SCI1 ERI1 */
.long _up_rxi1_handler /* 105: RxI1 */
.long _up_txi1_handler /* 106: TxI1 */
.long _up_tei1_handler /* 107: TEI1 */
#else
.long _up_invalid_handler /* 104: SCI1 ERI1 */
.long _up_invalid_handler /* 105: RxI1 */
.long _up_invalid_handler /* 106: TxI1 */
.long _up_invalid_handler /* 107: TEI1 */
.long _up_invalid_handler /* 104: SCI1 ERI1 */
.long _up_invalid_handler /* 105: RxI1 */
.long _up_invalid_handler /* 106: TxI1 */
.long _up_invalid_handler /* 107: TEI1 */
#endif
#ifdef CONFIG_SH1_PCU
.long _up_pei_handler /* 108: Parity control unit PEI */
.long _up_pei_handler /* 108: Parity control unit PEI */
#else
.long _up_invalid_handler /* 108: Parity control unit PEI */
.long _up_invalid_handler /* 108: Parity control unit PEI */
#endif
#ifdef CONFIG_SH1_AD
.long _up_aditi_handler /* 109: A/D ITI */
.long _up_aditi_handler /* 109: A/D ITI */
#else
.long _up_invalid_handler /* 109: A/D ITI */
.long _up_invalid_handler /* 109: A/D ITI */
#endif
.long _up_invalid_handler /* 110: Reserved */
.long _up_invalid_handler /* 111: Reserved */
.long _up_invalid_handler /* 110: Reserved */
.long _up_invalid_handler /* 111: Reserved */
#ifdef CONFIG_SH1_WDT
.long _up_wdt_handler /* 112: WDT ITI */
.long _up_wdt_handler /* 112: WDT ITI */
#else
.long _up_invalid_handler /* 112: WDT ITI */
.long _up_invalid_handler /* 112: WDT ITI */
#endif
#ifdef CONFIG_SH1_CMI
.long _up_cmi_handler /* 113: REF CMI */
.long _up_cmi_handler /* 113: REF CMI */
#else
.long _up_invalid_handler /* 113: REF CMI */
.long _up_invalid_handler /* 113: REF CMI */
#endif
.rept (SH1_LAST_VNDX-SH1_CMI_VNDX) /* 114-255: Reserved */
.long _up_invalid_handler
@ -346,15 +347,15 @@ __start:
/* set up the bus controller for the EVB */
mov.l .Lwcr1, r0
sub r1,r1
sub r1,r1
mov.w r1, @r0
/* Configure the BSR to use /LBS, /HBS, /WR */
mov.l .Lbcr, r0
mov.w .Lbas, r1
bra __start0
mov.w r1, @r0
mov.l .Lbcr, r0
mov.w .Lbas, r1
bra __start0
mov.w r1, @r0
.align 2
.Lstack:
@ -369,67 +370,67 @@ __start:
__start0:
/* Copy the monitor vectors to a002000-a00211f */
mov #0, r0 /* R0: Monitor vector table at address 0 in PROM */
mov.l .Lsvect, r1 /* R1: Redirected vector table in SRAM */
mov.l .Lvectend, r3 /* R3: Copy only up to external interrupts */
mov #0, r0 /* R0: Monitor vector table at address 0 in PROM */
mov.l .Lsvect, r1 /* R1: Redirected vector table in SRAM */
mov.l .Lvectend, r3 /* R3: Copy only up to external interrupts */
1:
mov.l @r0, r2 /* R2: Value from mnitor monitor vector table */
mov.l r2, @r1 /* Write into SRAM vector table */
add #4, r0 /* R0: Address of next vector to read from monitor vector table */
add #4, r1 /* R1: Address of next vector to write to SRAM vector table */
cmp/gt r0, r3 /* Copy only only up to external interrupts at */
bt 1b /* Continue looping until all copied */
nop /* Delay slot */
mov.l @r0, r2 /* R2: Value from mnitor monitor vector table */
mov.l r2, @r1 /* Write into SRAM vector table */
add #4, r0 /* R0: Address of next vector to read from monitor vector table */
add #4, r1 /* R1: Address of next vector to write to SRAM vector table */
cmp/gt r0, r3 /* Copy only only up to external interrupts at */
bt 1b /* Continue looping until all copied */
nop /* Delay slot */
/* Update the VBR to show new adddress of vector table */
mov.l .Lsvect, r0 /* R0: Address of SRAM vector table */
ldc r0, vbr /* Set VBR to start of SRAM vector table */
mov.l .Lsvect, r0 /* R0: Address of SRAM vector table */
ldc r0, vbr /* Set VBR to start of SRAM vector table */
/* Initialize data segement */
#ifdef CONFIG_BOOT_RUNFROMFLASH
mov.l .Lsdata, r0 /* R0: Start of .data segment */
mov.l .Ledata, r1 /* R1: End+1 of .data segment */
mov.l .Leronly, r2 /* R2: Start of FLASH .data segment copy */
mov.l .Lsdata, r0 /* R0: Start of .data segment */
mov.l .Ledata, r1 /* R1: End+1 of .data segment */
mov.l .Leronly, r2 /* R2: Start of FLASH .data segment copy */
2:
mov.l @r2, r3 /* R3: Next byte from FLASH copy */
mov.l r3, @r0 /* Copy to .data */
add #4, r2 /* R2: Address of next byte to read from FLASH */
add #4, r0 /* R0: Address to write next byte to .data */
cmp/gt r0, r1 /* End of .data? */
bt 2b /* Loop until end of data */
nop /* Delay slot */
mov.l @r2, r3 /* R3: Next byte from FLASH copy */
mov.l r3, @r0 /* Copy to .data */
add #4, r2 /* R2: Address of next byte to read from FLASH */
add #4, r0 /* R0: Address to write next byte to .data */
cmp/gt r0, r1 /* End of .data? */
bt 2b /* Loop until end of data */
nop /* Delay slot */
#endif
/* Clear BSS */
mov.l .Lsbss, r0 /* R0: Start of BSS segment */
mov.l .Lebss, r1 /* R1: End+1 of BSS segment */
mov #0, r2 /* R2: Value = 0 */
mov.l .Lsbss, r0 /* R0: Start of BSS segment */
mov.l .Lebss, r1 /* R1: End+1 of BSS segment */
mov #0, r2 /* R2: Value = 0 */
3:
mov.l r2, @r0 /* Clear the next word in BSS */
add #4, r0 /* R0: Address of next byte to clear in BSS */
cmp/ge r0, r1 /* End of BSS? */
bt 3b /* Loop until the end of BSS */
nop /* Delay slot */
mov.l r2, @r0 /* Clear the next word in BSS */
add #4, r0 /* R0: Address of next byte to clear in BSS */
cmp/ge r0, r1 /* End of BSS? */
bt 3b /* Loop until the end of BSS */
nop /* Delay slot */
/* Configure the uart so that we can get debug output as soon
* as possible.
*/
mov.l .Llowsetup, r0 /* Address of up_lowsetup */
jsr @r0 /* Call it */
or r0, r0 /* Delay slot */
mov.l .Llowsetup, r0 /* Address of up_lowsetup */
jsr @r0 /* Call it */
or r0, r0 /* Delay slot */
showprogress 'A'
/* Perform early console initialization */
#ifdef USE_EARLYSERIALINIT
mov.l .Learlyconsole, r0 /* Address of up_earlyconsoleinit */
jsr @r0 /* Call it */
or r0, r0 /* Delay slot */
mov.l .Learlyconsole, r0 /* Address of up_earlyconsoleinit */
jsr @r0 /* Call it */
or r0, r0 /* Delay slot */
#endif
showprogress 'B'
@ -445,16 +446,16 @@ __start0:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
mov.l .Lledinit, r0 /* Address of board_led_initialize */
jsr @r0 /* Call it */
or r0, r0 /* Delay slot */
mov.l .Lledinit, r0 /* Address of board_autoled_initialize */
jsr @r0 /* Call it */
or r0, r0 /* Delay slot */
#endif
/* Then jump to NuttX entry */
mov.l .Losstart,r0
jsr @r0
or r0, r0
mov.l .Losstart,r0
jsr @r0
or r0, r0
/* Shouldn't get here */
@ -471,16 +472,16 @@ __start0:
.align 2
#ifdef CONFIG_BOOT_RUNFROMFLASH
.Leronly:
.long _eronly
.long _eronly
.Lsdata:
.long _sdata
.long _sdata
.Ledata:
.long _edata
.long _edata
#endif
.Lsbss:
.long _sbss
.long _sbss
.Lebss:
.long _ebss
.long _ebss
#ifdef USE_EARLYSERIALINIT
.Learlyconsole:
.long _up_earlyconsoleinit
@ -492,13 +493,13 @@ __start0:
.long _up_lowputc
#endif
.Lledinit:
.long _board_led_initialize
.long _board_autoled_initialize
.Losstart:
.long _os_start
.long _os_start
.Lsvect:
.long _svect
.long _svect
.Lvectend:
.long ((4*SH1_NCMN_VECTORS)-1)
.long ((4*SH1_NCMN_VECTORS)-1)
.size __start, .-__start
/*****************************************************************************
@ -521,4 +522,3 @@ _g_idle_topstack:
.size _g_idle_topstack, .-_g_idle_topstack
.end

4
arch/sh/src/sh1/sh1_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -133,7 +133,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
#endif
}

2
arch/x86/src/common/up_allocateheap.c
View File

@ -82,7 +82,7 @@
void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (FAR void*)g_idle_topstack;
*heap_size = CONFIG_RAM_END - g_idle_topstack;
}

6
arch/x86/src/common/up_assert.c
View File

@ -261,9 +261,9 @@ static void _up_assert(int errorcode)
for (;;)
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -288,7 +288,7 @@ void up_assert(const uint8_t *filename, int lineno)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_PRINT_TASKNAME
lldbg("Assertion failed at file:%s line: %d task: %s\n",

2
arch/x86/src/common/up_initialize.c
View File

@ -211,5 +211,5 @@ void up_initialize(void)
/* Initialize USB -- device and/or host */
up_usbinitialize();
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}

2
arch/x86/src/i486/up_createstack.c
View File

@ -185,7 +185,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

4
arch/x86/src/i486/up_sigdeliver.c
View File

@ -93,7 +93,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -132,7 +132,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
up_fullcontextrestore(regs);
}

14
arch/x86/src/qemu/qemu_handlers.c
View File

@ -88,7 +88,7 @@ static void idt_outb(uint8_t val, uint16_t addr)
#ifndef CONFIG_SUPPRESS_INTERRUPTS
static uint32_t *common_handler(int irq, uint32_t *regs)
{
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
/* Current regs non-zero indicates that we are processing an interrupt;
* current_regs is also used to manage interrupt level context switches.
@ -163,7 +163,7 @@ static uint32_t *common_handler(int irq, uint32_t *regs)
uint32_t *isr_handler(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
PANIC(); /* Doesn't return */
return regs; /* To keep the compiler happy */
#else
@ -171,9 +171,9 @@ uint32_t *isr_handler(uint32_t *regs)
/* Dispatch the interrupt */
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
ret = common_handler((int)regs[REG_IRQNO], regs);
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return ret;
#endif
}
@ -189,14 +189,14 @@ uint32_t *isr_handler(uint32_t *regs)
uint32_t *irq_handler(uint32_t *regs)
{
#ifdef CONFIG_SUPPRESS_INTERRUPTS
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
PANIC(); /* Doesn't return */
return regs; /* To keep the compiler happy */
#else
uint32_t *ret;
int irq;
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
/* Get the IRQ number */
@ -220,7 +220,7 @@ uint32_t *irq_handler(uint32_t *regs)
/* Dispatch the interrupt */
ret = common_handler(irq, regs);
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
return ret;
#endif
}

2
arch/z16/src/common/up_allocateheap.c
View File

@ -92,7 +92,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
{
*heap_start = (FAR void*)CONFIG_HEAP1_BASE;
*heap_size = CONFIG_HEAP1_END - CONFIG_HEAP1_BASE;
board_led_on(LED_HEAPALLOCATE);
board_autoled_on(LED_HEAPALLOCATE);
}
/****************************************************************************

6
arch/z16/src/common/up_assert.c
View File

@ -98,9 +98,9 @@ static void _up_assert(int errorcode) /* noreturn_function */
for (;;)
{
#ifdef CONFIG_ARCH_LEDS
board_led_on(LED_PANIC);
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_led_off(LED_PANIC);
board_autoled_off(LED_PANIC);
up_mdelay(250);
#endif
}
@ -154,7 +154,7 @@ void up_assert(void)
struct tcb_s *rtcb = (struct tcb_s*)g_readytorun.head;
#endif
board_led_on(LED_ASSERTION);
board_autoled_on(LED_ASSERTION);
#ifdef CONFIG_HAVE_FILENAME
#if CONFIG_TASK_NAME_SIZE > 0

2
arch/z16/src/common/up_createstack.c
View File

@ -166,7 +166,7 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
tcb->adj_stack_ptr = (uint32_t*)top_of_stack;
tcb->adj_stack_size = size_of_stack;
board_led_on(LED_STACKCREATED);
board_autoled_on(LED_STACKCREATED);
return OK;
}

4
arch/z16/src/common/up_doirq.c
View File

@ -82,7 +82,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs)
{
FAR chipreg_t *ret = regs;
board_led_on(LED_INIRQ);
board_autoled_on(LED_INIRQ);
#ifdef CONFIG_SUPPRESS_INTERRUPTS
PANIC();
#else
@ -124,7 +124,7 @@ FAR chipreg_t *up_doirq(int irq, FAR chipreg_t *regs)
current_regs = savestate;
}
board_led_off(LED_INIRQ);
board_autoled_off(LED_INIRQ);
#endif
return ret;

4
arch/z16/src/common/up_idle.c
View File

@ -88,11 +88,11 @@ void up_idle(void)
g_ledtoggle++;
if (g_ledtoggle == 0x80)
{
board_led_on(LED_IDLE);
board_autoled_on(LED_IDLE);
}
else if (g_ledtoggle == 0x00)
{
board_led_off(LED_IDLE);
board_autoled_off(LED_IDLE);
}
#endif

2
arch/z16/src/common/up_initialize.c
View File

@ -212,5 +212,5 @@ void up_initialize(void)
(void)tun_initialize();
#endif
board_led_on(LED_IRQSENABLED);
board_autoled_on(LED_IRQSENABLED);
}

4
arch/z16/src/common/up_sigdeliver.c
View File

@ -94,7 +94,7 @@ void up_sigdeliver(void)
int saved_errno = rtcb->pterrno;
board_led_on(LED_SIGNAL);
board_autoled_on(LED_SIGNAL);
sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
@ -137,7 +137,7 @@ void up_sigdeliver(void)
/* Then restore the correct state for this thread of execution. */
board_led_off(LED_SIGNAL);
board_autoled_off(LED_SIGNAL);
SIGNAL_RETURN(regs);
#endif
}

4
arch/z16/src/z16f/z16f_head.S
View File

@ -54,7 +54,7 @@
xref _z16f_clkinit:EROM
xref _z16f_lowinit:EROM
#ifdef CONFIG_ARCH_LEDS
xref _board_led_initialize:EROM
xref _board_autoled_initialize:EROM
#endif
#if defined(USE_LOWUARTINIT)
xref _z16f_lowuartinit:EROM
@ -158,7 +158,7 @@ _z16f_reset:
/* Initialize onboard LEDs */
#ifdef CONFIG_ARCH_LEDS
call _board_led_initialize
call _board_autoled_initialize
#endif
/* Perform VERY early UART initialization so that we can use it here */

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