xtensa/esp32s2: Add driver for I2C peripheral in Master mode
Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
This commit is contained in:
Gustavo Henrique Nihei
Petro Karashchenko
parent
31cddc922c
commit
0657621848
@ -15,6 +15,7 @@ config ARCH_CHIP_ESP32S2WROVER
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bool "ESP32-S2-WROVER"
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select ESP32S2_FLASH_4M
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select ESP32S2_PSRAM_2M
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select ARCH_HAVE_I2CRESET
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---help---
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Generic module with an embedded ESP32-S2
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@ -232,6 +233,10 @@ config ESP32S2_UART
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bool
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default n
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config ESP32S2_I2C
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bool
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default n
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config ESP32S2_TIMER
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bool
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default n
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@ -320,6 +325,18 @@ config ESP32S2_UART1
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select UART1_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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config ESP32S2_I2C0
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bool "I2C 0"
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default n
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select ESP32S2_I2C
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select I2C
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config ESP32S2_I2C1
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bool "I2C 1"
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default n
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select ESP32S2_I2C
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select I2C
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config ESP32S2_RT_TIMER
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bool "Real-time Timer"
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select ESP32S2_TIMER
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@ -401,6 +418,47 @@ endif # ESP32S2_UART1
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endmenu # UART Configuration
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menu "I2C Configuration"
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depends on ESP32S2_I2C
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if ESP32S2_I2C0
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config ESP32S2_I2C0_SCLPIN
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int "I2C0 SCL Pin"
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default 19
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range 0 46
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config ESP32S2_I2C0_SDAPIN
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int "I2C0 SDA Pin"
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default 18
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range 0 46
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endif # ESP32S2_I2C0
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if ESP32S2_I2C1
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config ESP32S2_I2C1_SCLPIN
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int "I2C1 SCL Pin"
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default 6
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range 0 46
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config ESP32S2_I2C1_SDAPIN
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int "I2C1 SDA Pin"
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default 7
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range 0 46
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endif # ESP32S2_I2C1
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config ESP32S2_I2CTIMEOSEC
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int "Timeout seconds"
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default 0
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config ESP32S2_I2CTIMEOMS
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int "Timeout milliseconds"
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default 500
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endmenu # I2C Configuration
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menu "SPI Flash Configuration"
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depends on ESP32S2_SPIFLASH
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@ -84,6 +84,10 @@ ifeq ($(CONFIG_ESP32S2_RNG),y)
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CHIP_CSRCS += esp32s2_rng.c
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endif
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ifeq ($(CONFIG_ESP32S2_I2C),y)
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CHIP_CSRCS += esp32s2_i2c.c
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endif
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ifeq ($(CONFIG_ESP32S2_TIMER),y)
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CHIP_CSRCS += esp32s2_tim.c
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ifeq ($(CONFIG_TIMER),y)
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1702
arch/xtensa/src/esp32s2/esp32s2_i2c.c
Normal file
1702
arch/xtensa/src/esp32s2/esp32s2_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
91
arch/xtensa/src/esp32s2/esp32s2_i2c.h
Normal file
91
arch/xtensa/src/esp32s2/esp32s2_i2c.h
Normal file
@ -0,0 +1,91 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s2/esp32s2_i2c.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_I2C_H
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#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_I2C_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/i2c/i2c_master.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_ESP32S2_I2C0
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# define ESP32S2_I2C0 0
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#endif
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#ifdef CONFIG_ESP32S2_I2C1
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# define ESP32S2_I2C1 1
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: esp32s2_i2cbus_initialize
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*
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* Description:
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* Initialize the selected I2C port. And return a unique instance of struct
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* struct i2c_master_s. This function may be called to obtain multiple
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* instances of the interface, each of which may be set up with a
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* different frequency and slave address.
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*
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* Input Parameters:
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* Port number (for hardware that has multiple I2C interfaces)
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*
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* Returned Value:
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* Valid I2C device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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struct i2c_master_s *esp32s2_i2cbus_initialize(int port);
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/****************************************************************************
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* Name: esp32s2_i2cbus_uninitialize
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*
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* Description:
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* De-initialize the selected I2C port, and power down the device.
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*
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* Input Parameters:
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* Device structure as returned by the esp32s2_i2cbus_initialize()
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*
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* Returned Value:
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* OK on success, ERROR when internal reference count mismatch or dev
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* points to invalid hardware device.
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*
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****************************************************************************/
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int esp32s2_i2cbus_uninitialize(struct i2c_master_s *dev);
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_I2C_H */
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1992
arch/xtensa/src/esp32s2/hardware/esp32s2_i2c.h
Normal file
1992
arch/xtensa/src/esp32s2/hardware/esp32s2_i2c.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -190,7 +190,7 @@
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/* Helper to place a value in a field */
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#define VALUE_TO_FIELD(_value, _field) ((_value << (_field##_S)) & (_field##_M))
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#define VALUE_TO_FIELD(_value, _field) (((_value) << (_field##_S)) & (_field##_M))
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/* Periheral Clock */
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@ -80,9 +80,9 @@
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* This field is used to force on clock gate of internal SRAM.
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*/
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#define SYSTEM_SRAM_FO 0x003FFFFF
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#define SYSTEM_SRAM_FO 0x003fffff
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#define SYSTEM_SRAM_FO_M (SYSTEM_SRAM_FO_V << SYSTEM_SRAM_FO_S)
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#define SYSTEM_SRAM_FO_V 0x003FFFFF
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#define SYSTEM_SRAM_FO_V 0x003fffff
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#define SYSTEM_SRAM_FO_S 0
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/* SYSTEM_SRAM_CTRL_1_REG register
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@ -95,9 +95,9 @@
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* This field is used to power down internal SRAM.
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*/
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#define SYSTEM_SRAM_FORCE_PD 0x003FFFFF
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#define SYSTEM_SRAM_FORCE_PD 0x003fffff
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#define SYSTEM_SRAM_FORCE_PD_M (SYSTEM_SRAM_FORCE_PD_V << SYSTEM_SRAM_FORCE_PD_S)
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#define SYSTEM_SRAM_FORCE_PD_V 0x003FFFFF
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#define SYSTEM_SRAM_FORCE_PD_V 0x003fffff
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#define SYSTEM_SRAM_FORCE_PD_S 0
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/* SYSTEM_CPU_PERI_CLK_EN_REG register
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@ -135,16 +135,15 @@
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*/
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#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x18)
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#define DPORT_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x018) /* old name */
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/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W; bitpos: [7:4]; default: 0;
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* Sets the number of delay cycles to enter CPU wait mode after a WAITI
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* instruction.
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*/
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#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F
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#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000f
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#define SYSTEM_CPU_WAITI_DELAY_NUM_M (SYSTEM_CPU_WAITI_DELAY_NUM_V << SYSTEM_CPU_WAITI_DELAY_NUM_S)
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#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000F
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#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0x0000000f
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#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4
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/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W; bitpos: [3]; default: 1;
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@ -188,9 +187,9 @@
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* temporary disable of eFuse to JTAG.
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*/
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0
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/* SYSTEM_JTAG_CTRL_1_REG register
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@ -205,9 +204,9 @@
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* temporary disable of eFuse to JTAG.
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*/
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0
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/* SYSTEM_JTAG_CTRL_2_REG register
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@ -222,9 +221,9 @@
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* temporary disable of eFuse to JTAG.
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*/
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0
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/* SYSTEM_JTAG_CTRL_3_REG register
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@ -239,9 +238,9 @@
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* temporary disable of eFuse to JTAG.
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*/
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0
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/* SYSTEM_JTAG_CTRL_4_REG register
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@ -256,9 +255,9 @@
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* temporary disable of eFuse to JTAG.
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*/
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0
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/* SYSTEM_JTAG_CTRL_5_REG register
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@ -273,9 +272,9 @@
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* temporary disable of eFuse to JTAG.
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*/
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0
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/* SYSTEM_JTAG_CTRL_6_REG register
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@ -290,9 +289,9 @@
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* temporary disable of eFuse to JTAG.
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*/
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0
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/* SYSTEM_JTAG_CTRL_7_REG register
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@ -307,9 +306,9 @@
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* temporary disable of eFuse to JTAG.
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*/
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V << SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xffffffff
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#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0
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/* SYSTEM_MEM_PD_MASK_REG register
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@ -1043,12 +1042,12 @@
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#define SYSTEM_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x50)
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/* SYSTEM_LPCK_DIV_NUM : R/W; bitpos: [11:0]; default: 255;
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* This register is used to set the integer number of divider.
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* This field is used to set the integer number of the divider value.
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*/
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#define SYSTEM_LPCK_DIV_NUM 0x00000FFF
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#define SYSTEM_LPCK_DIV_NUM 0x00000fff
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#define SYSTEM_LPCK_DIV_NUM_M (SYSTEM_LPCK_DIV_NUM_V << SYSTEM_LPCK_DIV_NUM_S)
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#define SYSTEM_LPCK_DIV_NUM_V 0x00000FFF
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#define SYSTEM_LPCK_DIV_NUM_V 0x00000fff
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#define SYSTEM_LPCK_DIV_NUM_S 0
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/* SYSTEM_BT_LPCK_DIV_FRAC_REG register
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@ -1313,18 +1312,18 @@
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* address.
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*/
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#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF
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#define SYSTEM_RTC_MEM_CRC_LEN 0x000007ff
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#define SYSTEM_RTC_MEM_CRC_LEN_M (SYSTEM_RTC_MEM_CRC_LEN_V << SYSTEM_RTC_MEM_CRC_LEN_S)
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#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007FF
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#define SYSTEM_RTC_MEM_CRC_LEN_V 0x000007ff
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#define SYSTEM_RTC_MEM_CRC_LEN_S 20
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/* SYSTEM_RTC_MEM_CRC_ADDR : R/W; bitpos: [19:9]; default: 0;
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* This field is used to set address of RTC memory for CRC.
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*/
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#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF
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#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007ff
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#define SYSTEM_RTC_MEM_CRC_ADDR_M (SYSTEM_RTC_MEM_CRC_ADDR_V << SYSTEM_RTC_MEM_CRC_ADDR_S)
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#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007FF
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#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x000007ff
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#define SYSTEM_RTC_MEM_CRC_ADDR_S 9
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/* SYSTEM_RTC_MEM_CRC_START : R/W; bitpos: [8]; default: 0;
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@ -1346,9 +1345,9 @@
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* This field stores the CRC result of RTC memory.
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*/
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#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF
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#define SYSTEM_RTC_MEM_CRC_RES 0xffffffff
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#define SYSTEM_RTC_MEM_CRC_RES_M (SYSTEM_RTC_MEM_CRC_RES_V << SYSTEM_RTC_MEM_CRC_RES_S)
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#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF
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#define SYSTEM_RTC_MEM_CRC_RES_V 0xffffffff
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#define SYSTEM_RTC_MEM_CRC_RES_S 0
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/* SYSTEM_Redundant_ECO_Ctrl_REG register
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||||
@ -1400,9 +1399,9 @@
|
||||
* This field is used to power up internal SRAM.
|
||||
*/
|
||||
|
||||
#define SYSTEM_SRAM_FORCE_PU 0x003FFFFF
|
||||
#define SYSTEM_SRAM_FORCE_PU 0x003fffff
|
||||
#define SYSTEM_SRAM_FORCE_PU_M (SYSTEM_SRAM_FORCE_PU_V << SYSTEM_SRAM_FORCE_PU_S)
|
||||
#define SYSTEM_SRAM_FORCE_PU_V 0x003FFFFF
|
||||
#define SYSTEM_SRAM_FORCE_PU_V 0x003fffff
|
||||
#define SYSTEM_SRAM_FORCE_PU_S 0
|
||||
|
||||
/* SYSTEM_SYSCLK_CONF_REG register
|
||||
@ -1424,9 +1423,9 @@
|
||||
* This field is used to read XTAL frequency in MHz.
|
||||
*/
|
||||
|
||||
#define SYSTEM_CLK_XTAL_FREQ 0x0000007F
|
||||
#define SYSTEM_CLK_XTAL_FREQ 0x0000007f
|
||||
#define SYSTEM_CLK_XTAL_FREQ_M (SYSTEM_CLK_XTAL_FREQ_V << SYSTEM_CLK_XTAL_FREQ_S)
|
||||
#define SYSTEM_CLK_XTAL_FREQ_V 0x0000007F
|
||||
#define SYSTEM_CLK_XTAL_FREQ_V 0x0000007f
|
||||
#define SYSTEM_CLK_XTAL_FREQ_S 12
|
||||
|
||||
/* SYSTEM_SOC_CLK_SEL : R/W; bitpos: [11:10]; default: 0;
|
||||
@ -1442,24 +1441,24 @@
|
||||
* This field is used to set the count of prescaler of XTAL\_CLK.
|
||||
*/
|
||||
|
||||
#define SYSTEM_PRE_DIV_CNT 0x000003FF
|
||||
#define SYSTEM_PRE_DIV_CNT 0x000003ff
|
||||
#define SYSTEM_PRE_DIV_CNT_M (SYSTEM_PRE_DIV_CNT_V << SYSTEM_PRE_DIV_CNT_S)
|
||||
#define SYSTEM_PRE_DIV_CNT_V 0x000003FF
|
||||
#define SYSTEM_PRE_DIV_CNT_V 0x000003ff
|
||||
#define SYSTEM_PRE_DIV_CNT_S 0
|
||||
|
||||
/* SYSTEM_REG_DATE_REG register
|
||||
/* SYSTEM_DATE_REG register
|
||||
* Version control register
|
||||
*/
|
||||
|
||||
#define SYSTEM_REG_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
|
||||
#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xffc)
|
||||
|
||||
/* SYSTEM_SYSTEM_REG_DATE : R/W; bitpos: [27:0]; default: 26247200;
|
||||
* This is the date version register.
|
||||
/* SYSTEM_DATE : R/W; bitpos: [27:0]; default: 26247200;
|
||||
* Version control register.
|
||||
*/
|
||||
|
||||
#define SYSTEM_SYSTEM_REG_DATE 0x0FFFFFFF
|
||||
#define SYSTEM_SYSTEM_REG_DATE_M (SYSTEM_SYSTEM_REG_DATE_V << SYSTEM_SYSTEM_REG_DATE_S)
|
||||
#define SYSTEM_SYSTEM_REG_DATE_V 0x0FFFFFFF
|
||||
#define SYSTEM_SYSTEM_REG_DATE_S 0
|
||||
#define SYSTEM_DATE 0x0fffffff
|
||||
#define SYSTEM_DATE_M (SYSTEM_DATE_V << SYSTEM_DATE_S)
|
||||
#define SYSTEM_DATE_V 0x0fffffff
|
||||
#define SYSTEM_DATE_S 0
|
||||
|
||||
#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_SYSTEM_H */
|
||||
|
||||
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Reference in New Issue
Block a user