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Clean ESP32S2 Xtensa files

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This commit is contained in:
Alan C. Assis 2021-05-30 19:13:36 -03:00 committed by Alin Jerpelea
parent 8347a56bc0
commit 06795a221a
11 changed files with 50 additions and 1209 deletions
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2
arch/xtensa/include/esp32s2/core-isa.h
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@ -396,7 +396,7 @@
#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ #define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels #define XCHAL_INT_NLEVELS 6 /* number of interrupt levels
* (not including level zero) * (not including level zero)
*/ */
#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */

74
arch/xtensa/src/esp32s2/Kconfig
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@ -5,20 +5,20 @@
if ARCH_CHIP_ESP32S2 if ARCH_CHIP_ESP32S2
comment "ESP32S2 Configuration Options" comment "ESP32-S2 Configuration Options"
choice choice
prompt "ESP32S2 Chip Selection" prompt "ESP32-S2 Chip Selection"
default ARCH_CHIP_ESP32S2WROVER default ARCH_CHIP_ESP32S2WROVER
depends on ARCH_CHIP_ESP32S2 depends on ARCH_CHIP_ESP32S2
config ARCH_CHIP_ESP32S2WROVER config ARCH_CHIP_ESP32S2WROVER
bool "ESP32S2-WROVER" bool "ESP32-S2-WROVER"
select ESP32S2_ESP32S2DXWDXX select ESP32S2_ESP32S2DXWDXX
select ESP32S2_FLASH_4M select ESP32S2_FLASH_4M
select ESP32S2_PSRAM_8M select ESP32S2_PSRAM_8M
---help--- ---help---
Generic module with an embedded ESP32S2 Generic module with an embedded ESP32-S2
endchoice # ESP32S2 Chip Selection endchoice # ESP32S2 Chip Selection
@ -84,7 +84,7 @@ config ESP32S2_FLASH_16M
config ESP32S2_FLASH_DETECT config ESP32S2_FLASH_DETECT
bool "Auto-detect FLASH size" bool "Auto-detect FLASH size"
default y default y
help ---help---
Auto detect flash size when flashing. Auto detect flash size when flashing.
config ESP32S2_PSRAM_8M config ESP32S2_PSRAM_8M
@ -100,57 +100,57 @@ config ESP32S2_ESP32S2SXWDXX
choice ESP32S2_FLASH_MODE choice ESP32S2_FLASH_MODE
prompt "SPI FLASH mode" prompt "SPI FLASH mode"
default ESP32S2_FLASH_MODE_DIO default ESP32S2_FLASH_MODE_DIO
help ---help---
These options control how many I/O pins are used for communication These options control how many I/O pins are used for communication
with the attached SPI flash chip. with the attached SPI flash chip.
The option selected here is then used by esptool when flashing. The option selected here is then used by esptool when flashing.
config ESP32S2_FLASH_MODE_DIO config ESP32S2_FLASH_MODE_DIO
bool "Dual IO (DIO)" bool "Dual IO (DIO)"
config ESP32S2_FLASH_MODE_DOUT config ESP32S2_FLASH_MODE_DOUT
bool "Dual Output (DOUT)" bool "Dual Output (DOUT)"
config ESP32S2_FLASH_MODE_QIO config ESP32S2_FLASH_MODE_QIO
bool "Quad IO (QIO)" bool "Quad IO (QIO)"
config ESP32S2_FLASH_MODE_QOUT config ESP32S2_FLASH_MODE_QOUT
bool "Quad Output (QOUT)" bool "Quad Output (QOUT)"
endchoice # ESP32S2_FLASH_MODE endchoice # ESP32S2_FLASH_MODE
choice ESP32S2_FLASH_FREQ choice ESP32S2_FLASH_FREQ
prompt "SPI FLASH frequency" prompt "SPI FLASH frequency"
default ESP32S2_FLASH_FREQ_40M default ESP32S2_FLASH_FREQ_40M
help ---help---
SPI FLASH frequency SPI FLASH frequency
config ESP32S2_FLASH_FREQ_80M config ESP32S2_FLASH_FREQ_80M
bool "80 MHz" bool "80 MHz"
config ESP32S2_FLASH_FREQ_40M config ESP32S2_FLASH_FREQ_40M
bool "40 MHz" bool "40 MHz"
config ESP32S2_FLASH_FREQ_26M config ESP32S2_FLASH_FREQ_26M
bool "26 MHz" bool "26 MHz"
config ESP32S2_FLASH_FREQ_20M config ESP32S2_FLASH_FREQ_20M
bool "20 MHz" bool "20 MHz"
endchoice # ESP32S2_FLASH_FREQ endchoice # ESP32S2_FLASH_FREQ
choice ESP32S2_DEFAULT_CPU_FREQ choice ESP32S2_DEFAULT_CPU_FREQ
prompt "CPU frequency" prompt "CPU frequency"
default ESP32S2_DEFAULT_CPU_FREQ_240 default ESP32S2_DEFAULT_CPU_FREQ_240
help ---help---
CPU frequency to be set on application startup. CPU frequency to be set on application startup.
config ESP32S2_DEFAULT_CPU_FREQ_80 config ESP32S2_DEFAULT_CPU_FREQ_80
bool "80 MHz" bool "80 MHz"
config ESP32S2_DEFAULT_CPU_FREQ_160 config ESP32S2_DEFAULT_CPU_FREQ_160
bool "160 MHz" bool "160 MHz"
config ESP32S2_DEFAULT_CPU_FREQ_240 config ESP32S2_DEFAULT_CPU_FREQ_240
bool "240 MHz" bool "240 MHz"
endchoice # CPU frequency endchoice # CPU frequency
config ESP32S2_DEFAULT_CPU_FREQ_MHZ config ESP32S2_DEFAULT_CPU_FREQ_MHZ
@ -190,7 +190,7 @@ config ESP32S2_RUN_IRAM
This loads all of NuttX inside IRAM. Used to test somewhat small This loads all of NuttX inside IRAM. Used to test somewhat small
images that can fit entirely in IRAM. images that can fit entirely in IRAM.
menu "ESP32S2 Peripheral Selection" menu "ESP32-S2 Peripheral Selection"
config ESP32S2_UART config ESP32S2_UART
bool bool
@ -292,13 +292,13 @@ if ESP32S2_SPIRAM && SMP
choice choice
prompt "How does SPIRAM share cache?" prompt "How does SPIRAM share cache?"
default ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD default ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD
help ---help---
Selects the cache mode to CPU access the external memory. Selects the cache mode to CPU access the external memory.
config ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD config ESP32S2_MEMMAP_SPIRAM_CACHE_EVENODD
bool "Pro CPU uses even 32 byte ranges, App uses odd ones" bool "Pro CPU uses even 32 byte ranges, App uses odd ones"
config ESP32S2_MEMMAP_SPIRAM_CACHE_LOWHIGH config ESP32S2_MEMMAP_SPIRAM_CACHE_LOWHIGH
bool "Pro CPU uses low 2MB ranges, App uses high ones" bool "Pro CPU uses low 2MB ranges, App uses high ones"
endchoice # CPU frequency endchoice # CPU frequency
endif endif
@ -650,20 +650,20 @@ menu "SPI Flash configuration"
config ESP32S2_MTD_OFFSET config ESP32S2_MTD_OFFSET
hex "MTD base address in SPI Flash" hex "MTD base address in SPI Flash"
default 0x180000 default 0x180000
help ---help---
MTD base address in SPI Flash. MTD base address in SPI Flash.
config ESP32S2_MTD_SIZE config ESP32S2_MTD_SIZE
hex "MTD size in SPI Flash" hex "MTD size in SPI Flash"
default 0x100000 default 0x100000
help ---help---
MTD size in SPI Flash. MTD size in SPI Flash.
config ESP32S2_SPIFLASH_DEBUG config ESP32S2_SPIFLASH_DEBUG
bool "Debug SPI Flash" bool "Debug SPI Flash"
default n default n
depends on DEBUG_FS_INFO depends on DEBUG_FS_INFO
help ---help---
Enable this option, read and write of SPI Flash Enable this option, read and write of SPI Flash
will show input arguments and result. will show input arguments and result.
@ -696,7 +696,7 @@ config ESP32S2_SPIRAM_SIZE
choice ESP32S2_SPIRAM_SPEED choice ESP32S2_SPIRAM_SPEED
prompt "Set RAM clock speed" prompt "Set RAM clock speed"
default ESP32S2_SPIRAM_SPEED_40M default ESP32S2_SPIRAM_SPEED_40M
help ---help---
Select the speed for the SPI RAM chip. Select the speed for the SPI RAM chip.
config ESP32S2_SPIRAM_SPEED_40M config ESP32S2_SPIRAM_SPEED_40M
@ -711,7 +711,7 @@ config ESP32S2_SPIRAM_BOOT_INIT
bool "Initialize SPI RAM during startup" bool "Initialize SPI RAM during startup"
depends on ESP32S2_SPIRAM depends on ESP32S2_SPIRAM
default "y" default "y"
help ---help---
If this is enabled, the SPI RAM will be enabled during initial If this is enabled, the SPI RAM will be enabled during initial
boot. Unless you have specific requirements, you'll want to leave boot. Unless you have specific requirements, you'll want to leave
this enabled so memory allocated during boot-up can also be this enabled so memory allocated during boot-up can also be
@ -721,7 +721,7 @@ config ESP32S2_SPIRAM_IGNORE_NOTFOUND
bool "Ignore PSRAM when not found" bool "Ignore PSRAM when not found"
default "n" default "n"
depends on ESP32S2_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA depends on ESP32S2_SPIRAM_BOOT_INIT && !BOOT_SDRAM_DATA
help ---help---
Normally, if psram initialization is enabled during compile time Normally, if psram initialization is enabled during compile time
but not found at runtime, it is seen as an error making the CPU but not found at runtime, it is seen as an error making the CPU
panic. If this is enabled, booting will complete but no PSRAM panic. If this is enabled, booting will complete but no PSRAM
@ -731,7 +731,7 @@ config ESP32S2_SPIRAM_2T_MODE
bool "Enable SPI PSRAM 2T mode" bool "Enable SPI PSRAM 2T mode"
depends on ESP32S2_SPIRAM depends on ESP32S2_SPIRAM
default "n" default "n"
help ---help---
Enable this option to fix single bit errors inside 64Mbit PSRAM. Enable this option to fix single bit errors inside 64Mbit PSRAM.
Some 64Mbit PSRAM chips have a hardware issue in the RAM which Some 64Mbit PSRAM chips have a hardware issue in the RAM which
causes bit errors at multiple fixed bit positions. causes bit errors at multiple fixed bit positions.
@ -743,7 +743,7 @@ config ESP32S2_SPIRAM_2T_MODE
config ESP32S2_SPIRAM_BANKSWITCH_ENABLE config ESP32S2_SPIRAM_BANKSWITCH_ENABLE
bool "Enable bank switching for >4MiB external RAM" bool "Enable bank switching for >4MiB external RAM"
default y default y
help ---help---
The ESP32S2 only supports 4MiB of external RAM in its address The ESP32S2 only supports 4MiB of external RAM in its address
space. The hardware does support larger memories, but these space. The hardware does support larger memories, but these
have to be bank-switched in and out of this address space. have to be bank-switched in and out of this address space.
@ -762,7 +762,7 @@ config SPIRAM_BANKSWITCH_RESERVE
depends on ESP32S2_SPIRAM_BANKSWITCH_ENABLE depends on ESP32S2_SPIRAM_BANKSWITCH_ENABLE
default 8 default 8
range 1 62 range 1 62
help ---help---
Select the amount of banks reserved for bank switching. Note Select the amount of banks reserved for bank switching. Note
that the amount of RAM allocatable with malloc will decrease that the amount of RAM allocatable with malloc will decrease
by 32K for each page reserved here. by 32K for each page reserved here.
@ -777,7 +777,7 @@ menu "WiFi configuration"
depends on ESP32S2_WIRELESS depends on ESP32S2_WIRELESS
choice choice
prompt "ESP32S2 WiFi mode" prompt "ESP32-S2 WiFi mode"
default ESP32S2_WIFI_STATION default ESP32S2_WIFI_STATION
config ESP32S2_WIFI_STATION config ESP32S2_WIFI_STATION
@ -822,19 +822,19 @@ config ESP32S2_WLAN_PKTBUF_NUM
config ESP32S2_WIFI_CONNECT_TIMEOUT config ESP32S2_WIFI_CONNECT_TIMEOUT
int "Connect timeout by second" int "Connect timeout by second"
default 10 default 10
help ---help---
Max waiting time of connecting to AP. Max waiting time of connecting to AP.
config ESP32S2_WIFI_SCAN_RESULT_SIZE config ESP32S2_WIFI_SCAN_RESULT_SIZE
int "Scan result buffer" int "Scan result buffer"
default 4096 default 4096
help ---help---
Maximum scan result buffer size. Maximum scan result buffer size.
config ESP32S2_WIFI_SAVE_PARAM config ESP32S2_WIFI_SAVE_PARAM
bool "Save WiFi Parameters" bool "Save WiFi Parameters"
default n default n
help ---help---
If you enable this option, WiFi adapter parameters will be saved If you enable this option, WiFi adapter parameters will be saved
into the file system instead of computing them each time. into the file system instead of computing them each time.
@ -851,7 +851,7 @@ config ESP32S2_WIFI_FS_MOUNTPT
string "Save WiFi Parameters" string "Save WiFi Parameters"
default "/mnt/esp/wifi" default "/mnt/esp/wifi"
depends on ESP32S2_WIFI_SAVE_PARAM depends on ESP32S2_WIFI_SAVE_PARAM
help ---help---
Mount point of WiFi storage file system. Mount point of WiFi storage file system.
endmenu # ESP32S2_WIRELESS endmenu # ESP32S2_WIRELESS

3
arch/xtensa/src/esp32s2/Make.defs
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@ -71,8 +71,7 @@ endif
CHIP_CSRCS = esp32s2_allocateheap.c esp32s2_clockconfig.c esp32s2_cpuint.c CHIP_CSRCS = esp32s2_allocateheap.c esp32s2_clockconfig.c esp32s2_cpuint.c
CHIP_CSRCS += esp32s2_gpio.c esp32s2_intdecode.c esp32s2_irq.c esp32s2_region.c CHIP_CSRCS += esp32s2_gpio.c esp32s2_intdecode.c esp32s2_irq.c esp32s2_region.c
CHIP_CSRCS += esp32s2_timerisr.c esp32s2_user.c esp32s2_rtc.c CHIP_CSRCS += esp32s2_timerisr.c esp32s2_user.c esp32s2_lowputc.c
CHIP_CSRCS += esp32s2_lowputc.c
# Configuration-dependent ESP32S2 files # Configuration-dependent ESP32S2 files

1
arch/xtensa/src/esp32s2/esp32s2_allocateheap.c
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@ -31,7 +31,6 @@
#include <nuttx/mm/mm.h> #include <nuttx/mm/mm.h>
#include <nuttx/board.h> #include <nuttx/board.h>
#include <arch/board/board.h> #include <arch/board/board.h>
#include <arch/esp32s2/memory_layout.h>
#include "xtensa.h" #include "xtensa.h"

1
arch/xtensa/src/esp32s2/esp32s2_clockconfig.c
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@ -31,7 +31,6 @@
#include "hardware/esp32s2_uart.h" #include "hardware/esp32s2_uart.h"
#include "hardware/esp32s2_rtccntl.h" #include "hardware/esp32s2_rtccntl.h"
#include "hardware/esp32s2_system.h" #include "hardware/esp32s2_system.h"
#include "esp32s2_rtc.h"
/**************************************************************************** /****************************************************************************
* Pre-processor Definitions * Pre-processor Definitions

1
arch/xtensa/src/esp32s2/esp32s2_idle.c
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@ -27,7 +27,6 @@
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <nuttx/power/pm.h> #include <nuttx/power/pm.h>
#include "esp32s2_pm.h"
#include "xtensa.h" #include "xtensa.h"
/**************************************************************************** /****************************************************************************

218
arch/xtensa/src/esp32s2/esp32s2_pm.h
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@ -1,218 +0,0 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#ifdef CONFIG_PM
/****************************************************************************
* Public Types
****************************************************************************/
/* Sleep wakeup cause */
enum esp32s2_sleep_source_e
{
/* In case of deep sleep, reset was not caused by exit from deep sleep */
ESP_SLEEP_WAKEUP_UNDEFINED,
/* Not a wakeup cause, used to disable all wakeup sources with
* esp_sleep_disable_wakeup_source
*/
ESP_SLEEP_WAKEUP_ALL,
/* Wakeup caused by external signal using RTC_IO */
ESP_SLEEP_WAKEUP_EXT0,
/* Wakeup caused by external signal using RTC_CNTL */
ESP_SLEEP_WAKEUP_EXT1,
/* Wakeup caused by timer */
ESP_SLEEP_WAKEUP_TIMER,
/* Wakeup caused by touchpad */
ESP_SLEEP_WAKEUP_TOUCHPAD,
/* Wakeup caused by ULP program */
ESP_SLEEP_WAKEUP_ULP,
/* Wakeup caused by GPIO (light sleep only) */
ESP_SLEEP_WAKEUP_GPIO,
/* Wakeup caused by UART (light sleep only) */
ESP_SLEEP_WAKEUP_UART,
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_sleep_enable_timer_wakeup
*
* Description:
* Configure wake-up interval
*
* Input Parameters:
* time_in_us - Configure wake-up time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_sleep_enable_timer_wakeup(uint64_t time_in_us);
/****************************************************************************
* Name: esp32s2_light_sleep_start
*
* Description:
* Enter sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* 0 is returned on success or a negated errno value is returned
*
****************************************************************************/
int esp32s2_light_sleep_start(void);
/****************************************************************************
* Name: esp32s2_pminit
*
* Description:
* Initialize force sleep parameters.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pminit(void);
/****************************************************************************
* Name: esp32s2_pmstandby
*
* Description:
* Enter force sleep time interval.
*
* Input Parameters:
* time_in_us - force sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pmstandby(uint64_t time_in_us);
/****************************************************************************
* Name: esp32s2_sleep_get_wakeup_cause
*
* Description:
* Get the wakeup source which caused wakeup from sleep.
*
* Input Parameters:
* None
*
* Returned Value:
* enum esp32s2_sleep_source_e - Cause of wake up from last sleep.
*
****************************************************************************/
enum esp32s2_sleep_source_e esp32s2_sleep_get_wakeup_cause(void);
/****************************************************************************
* Name: esp32s2_deep_sleep_start
*
* Description:
* Enter deep sleep mode
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_deep_sleep_start(void);
/****************************************************************************
* Name: esp32s2_pmsleep
*
* Description:
* Enter deep sleep.
*
* Input Parameters:
* time_in_us - deep sleep time interval
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_pmsleep(uint64_t time_in_us);
#endif /* CONFIG_PM */
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_PMSLEEP_H */

562
arch/xtensa/src/esp32s2/esp32s2_rtc.c
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@ -1,562 +0,0 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_rtc.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h>
#include <assert.h>
#include "esp32s2_rtc.h"
#include "esp32s2_clockconfig.h"
#include "hardware/esp32s2_i2s.h"
#include "hardware/esp32s2_rtccntl.h"
#include "hardware/esp32s2_i2cbbpll.h"
#include "hardware/esp32s2_system.h"
#include "esp32s2_rtc.h"
#include "xtensa.h"
#include "xtensa_attr.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP 2
#define RTC_CNTL_CK8M_WAIT_SLP 4
#define OTHER_BLOCKS_POWERUP 1
#define OTHER_BLOCKS_WAIT 1
#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP
#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT
#define RTC_CNTL_PLL_BUF_WAIT_SLP 2
#define DELAY_FAST_CLK_SWITCH 3
#define XTAL_32K_DAC_VAL 3
#define XTAL_32K_DRES_VAL 3
#define XTAL_32K_DBIAS_VAL 0
#define DELAY_SLOW_CLK_SWITCH 300
/* Number of fractional bits in values returned by rtc_clk_cal */
#define RTC_CLK_CAL_FRACT 19
/* With the default value of CK8M_DFREQ,
* 8M clock frequency is 8.5 MHz +/- 7%
*/
#define RTC_FAST_CLK_FREQ_APPROX 8500000
/* Disable logging from the ROM code. */
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16))
/* Default initializer for esp32s2_rtc_sleep_config_t
* This initializer sets all fields to "reasonable" values
* (e.g. suggested for production use) based on a combination
* of RTC_SLEEP_PD_x flags.
*/
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 0, \
.rtc_mem_inf_fpu = 0, \
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = 0, \
.rom_mem_pd_en = 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
.rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
.lslp_meminf_pd = 1, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \
}
/* Initializer for rtc_sleep_pd_config_t which
* sets all flags to the same value
*/
#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
.dig_pd = (val), \
.rtc_pd = (val), \
.cpu_pd = (val), \
.i2s_pd = (val), \
.bb_pd = (val), \
.nrx_pd = (val), \
.fe_pd = (val), \
}
/****************************************************************************
* Private Types
****************************************************************************/
/* RTC power and clock control initialization settings */
struct esp32s2_rtc_priv_s
{
uint32_t ck8m_wait : 8; /* Number of rtc_fast_clk cycles to wait for 8M clock to be ready */
uint32_t xtal_wait : 8; /* Number of rtc_fast_clk cycles to wait for XTAL clock to be ready */
uint32_t pll_wait : 8; /* Number of rtc_fast_clk cycles to wait for PLL to be ready */
uint32_t clkctl_init : 1; /* Perform clock control related initialization */
uint32_t pwrctl_init : 1; /* Perform power control related initialization */
uint32_t rtc_dboost_fpd : 1; /* Force power down RTC_DBOOST */
};
/* sleep configuration for rtc_sleep_init function */
struct esp32s2_rtc_sleep_config_s
{
uint32_t lslp_mem_inf_fpu : 1; /* force normal voltage in sleep mode (digital domain memory) */
uint32_t rtc_mem_inf_fpu : 1; /* force normal voltage in sleep mode (RTC memory) */
uint32_t rtc_mem_inf_follow_cpu : 1; /* keep low voltage in sleep mode (even if ULP/touch is used) */
uint32_t rtc_fastmem_pd_en : 1; /* power down RTC fast memory */
uint32_t rtc_slowmem_pd_en : 1; /* power down RTC slow memory */
uint32_t rtc_peri_pd_en : 1; /* power down RTC peripherals */
uint32_t wifi_pd_en : 1; /* power down WiFi */
uint32_t rom_mem_pd_en : 1; /* power down main RAM and ROM */
uint32_t deep_slp : 1; /* power down digital domain */
uint32_t wdt_flashboot_mod_en : 1; /* enable WDT flashboot mode */
uint32_t dig_dbias_wak : 3; /* set bias for digital domain, in active mode */
uint32_t dig_dbias_slp : 3; /* set bias for digital domain, in sleep mode */
uint32_t rtc_dbias_wak : 3; /* set bias for RTC domain, in active mode */
uint32_t rtc_dbias_slp : 3; /* set bias for RTC domain, in sleep mode */
uint32_t lslp_meminf_pd : 1; /* remove all peripheral force power up flags */
uint32_t vddsdio_pd_en : 1; /* power down VDDSDIO regulator */
uint32_t xtal_fpu : 1; /* keep main XTAL powered up in sleep */
};
/* Power down flags for rtc_sleep_pd function */
struct esp32s2_rtc_sleep_pd_config_s
{
uint32_t dig_pd : 1; /* Set to 1 to power down digital part in sleep */
uint32_t rtc_pd : 1; /* Set to 1 to power down RTC memories in sleep */
uint32_t cpu_pd : 1; /* Set to 1 to power down digital memories and CPU in sleep */
uint32_t i2s_pd : 1; /* Set to 1 to power down I2S in sleep */
uint32_t bb_pd : 1; /* Set to 1 to power down WiFi in sleep */
uint32_t nrx_pd : 1; /* Set to 1 to power down WiFi in sleep */
uint32_t fe_pd : 1; /* Set to 1 to power down WiFi in sleep */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
static void IRAM_ATTR esp32s2_rtc_sleep_pd(
struct esp32s2_rtc_sleep_pd_config_s cfg);
static inline bool esp32s2_clk_val_is_valid(uint32_t val);
static void IRAM_ATTR esp32s2_rtc_clk_fast_freq_set(
enum esp32s2_rtc_fast_freq_e fast_freq);
static uint32_t IRAM_ATTR esp32s2_rtc_clk_cal_internal(
enum esp32s2_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles);
static void IRAM_ATTR esp32s2_rtc_clk_slow_freq_set(
enum esp32s2_rtc_slow_freq_e slow_freq);
static void esp32s2_select_rtc_slow_clk(enum esp32s2_slow_clk_sel_e
slow_clk);
/****************************************************************************
* Private Data
****************************************************************************/
static struct esp32s2_rtc_priv_s esp32s2_rtc_priv =
{
.ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT,
.xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT,
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT,
.clkctl_init = 1,
.pwrctl_init = 1,
.rtc_dboost_fpd = 1
};
/****************************************************************************
* Private Functions
****************************************************************************/
extern void ets_delay_us(uint32_t us);
/****************************************************************************
* Name: esp32s2_clk_val_is_valid
*
* Description:
* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are
* stored as two copies in lower and upper 16-bit halves.
* These are the routines to work with such a representation.
*
* Input Parameters:
* val - register value
*
* Returned Value:
* true: Valid register value.
* false: Invalid register value.
*
****************************************************************************/
static inline bool esp32s2_clk_val_is_valid(uint32_t val)
{
return (val & 0xffff) == ((val >> 16) & 0xffff)
&& val != 0 && val != UINT32_MAX;
}
/****************************************************************************
* Public Functions
****************************************************************************/
enum esp32s2_rtc_xtal_freq_e rtc_get_xtal(void)
__attribute__((alias("esp32s2_rtc_clk_xtal_freq_get")));
/****************************************************************************
* Name: esp32s2_rtc_clk_xtal_freq_get
*
* Description:
* Get main XTAL frequency
*
* Input Parameters:
* None
*
* Returned Value:
* XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values)
*
****************************************************************************/
enum esp32s2_rtc_xtal_freq_e IRAM_ATTR esp32s2_rtc_clk_xtal_freq_get(void)
{
/* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
uint32_t xtal_freq_reg = getreg32(RTC_XTAL_FREQ_REG);
if (!esp32s2_clk_val_is_valid(xtal_freq_reg))
{
return RTC_XTAL_FREQ_AUTO;
}
return (xtal_freq_reg & ~RTC_DISABLE_ROM_LOG) & UINT16_MAX;
}
/****************************************************************************
* Name: esp32s2_rtc_update_to_xtal
*
* Description:
* Switch to XTAL frequency, does not disable the PLL
*
* Input Parameters:
* freq - XTAL frequency
* div - REF_TICK divider
*
* Returned Value:
* none
*
****************************************************************************/
void IRAM_ATTR esp32s2_rtc_update_to_xtal(int freq, int div)
{
uint32_t value = (((freq * MHZ) >> 12) & UINT16_MAX)
| ((((freq * MHZ) >> 12) & UINT16_MAX) << 16);
esp32s2_update_cpu_freq(freq);
/* set divider from XTAL to APB clock */
REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1);
/* adjust ref_tick */
modifyreg32(APB_CTRL_XTAL_TICK_CONF_REG, 0,
(freq * MHZ) / REF_CLK_FREQ - 1);
/* switch clock source */
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL,
RTC_CNTL_SOC_CLK_SEL_XTL);
putreg32(value, RTC_APB_FREQ_REG);
/* lower the voltage */
if (freq <= 2)
{
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
}
else
{
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
}
}
/****************************************************************************
* Name: esp32s2_rtc_bbpll_enable
*
* Description:
* Reset BBPLL configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s2_rtc_bbpll_enable(void)
{
modifyreg32(RTC_CNTL_OPTIONS0_REG,
RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD |
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, 0);
/* reset BBPLL configuration */
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY,
BBPLL_IR_CAL_DELAY_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP,
BBPLL_IR_CAL_EXT_CAP_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL,
BBPLL_OC_ENB_FCAL_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON,
BBPLL_OC_ENB_VCON_VAL);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0,
BBPLL_BBADC_CAL_7_0_VAL);
}
/****************************************************************************
* Name: esp32s2_rtc_bbpll_configure
*
* Description:
* Configure main XTAL frequency values according to pll_freq.
*
* Input Parameters:
* xtal_freq - XTAL frequency values
* pll_freq - PLL frequency values
*
* Returned Value:
* None
*
****************************************************************************/
void IRAM_ATTR esp32s2_rtc_bbpll_configure(
enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq)
{
static uint8_t div_ref = 0;
static uint8_t div7_0 = 0;
static uint8_t dr1 = 0;
static uint8_t dr3 = 0;
static uint8_t dchgp = 0;
static uint8_t dcur = 0;
uint8_t i2c_bbpll_lref = 0;
uint8_t i2c_bbpll_div_7_0 = 0;
uint8_t i2c_bbpll_dcur = 0;
if (pll_freq == RTC_PLL_FREQ_480M)
{
/* Clear this register to let the digital part know 480M PLL is used */
SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
/* Configure 480M PLL */
div_ref = 0;
div7_0 = 8;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 4;
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b);
}
else
{
/* Clear this register to let the digital part know 320M PLL is used */
CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL);
/* Configure 320M PLL */
div_ref = 0;
div7_0 = 4;
dr1 = 0;
dr3 = 0;
dchgp = 5;
dcur = 5;
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
}
i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
i2c_bbpll_div_7_0 = div7_0;
i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB) |
(1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
/* Enable calibration by software */
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1);
for (int ext_cap = 0; ext_cap < 16; ext_cap++)
{
uint8_t cal_result;
I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap);
cal_result = I2C_READREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP);
if (cal_result == 0)
{
break;
}
if (ext_cap == 15)
{
ets_printf("BBPLL SOFTWARE CAL FAIL\n");
abort();
}
}
}
/****************************************************************************
* Name: esp32s2_rtc_wait_for_slow_cycle
*
* Description:
* Busy loop until next RTC_SLOW_CLK cycle.
*
* Input Parameters:
* None
*
* Returned Value:
* none
*
****************************************************************************/
void IRAM_ATTR esp32s2_rtc_wait_for_slow_cycle(void)
{
modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING |
TIMG_RTC_CALI_START, 0);
modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY, 0);
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL,
RTC_CAL_RTC_MUX);
/* Request to run calibration for 0 slow clock cycles.
* RDY bit will be set on the nearest slow clock cycle.
*/
REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0);
modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START);
/* RDY needs some time to go low */
ets_delay_us(1);
while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY))
{
ets_delay_us(1);
}
}
/****************************************************************************
* Name: esp_rtc_clk_get_cpu_freq
*
* Description:
* Get the currently used CPU frequency configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int IRAM_ATTR esp_rtc_clk_get_cpu_freq(void)
{
uint32_t source_freq_mhz;
uint32_t div;
uint32_t soc_clk_sel;
uint32_t cpuperiod_sel;
int freq_mhz = 0;
soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
switch (soc_clk_sel)
{
case RTC_CNTL_SOC_CLK_SEL_XTL:
{
div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG,
APB_CTRL_PRE_DIV_CNT) + 1;
source_freq_mhz = (uint32_t) esp32s2_rtc_clk_xtal_freq_get();
freq_mhz = source_freq_mhz / div;
}
break;
case RTC_CNTL_SOC_CLK_SEL_PLL:
{
cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG,
SYSTEM_CPUPERIOD_SEL);
if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80)
{
freq_mhz = 80;
}
else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160)
{
freq_mhz = 160;
}
else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240)
{
freq_mhz = 240;
}
else
{
DEBUGASSERT(0);
}
}
break;
case RTC_CNTL_SOC_CLK_SEL_8M:
{
freq_mhz = 8;
}
break;
case RTC_CNTL_SOC_CLK_SEL_APLL:
default:
DEBUGASSERT(0);
}
return freq_mhz;
}

358
arch/xtensa/src/esp32s2/esp32s2_rtc.h
View File

@ -1,358 +0,0 @@
/****************************************************************************
* arch/xtensa/src/esp32s2/esp32s2_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H
#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/esp32s2_soc.h"
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Number of cycles to wait from the 32k XTAL oscillator to
* consider it running. Larger values increase startup delay.
* Smaller values may cause false positive detection
* (i.e. oscillator runs for a few cycles and then stops).
*/
#define SLOW_CLK_CAL_CYCLES 1024
/* Indicates that 32k oscillator gets input from external oscillator
* instead of a crystal.
*/
#define EXT_OSC_FLAG BIT(3)
/****************************************************************************
* Public Types
****************************************************************************/
/* Possible main XTAL frequency values.
* Enum values should be equal to frequency in MHz.
*/
enum esp32s2_rtc_xtal_freq_e
{
RTC_XTAL_FREQ_AUTO = 0, /* Automatic XTAL frequency detection */
RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */
RTC_XTAL_FREQ_26M = 26, /* 26 MHz XTAL */
RTC_XTAL_FREQ_24M = 24, /* 24 MHz XTAL */
};
/* RTC SLOW_CLK frequency values */
enum esp32s2_rtc_slow_freq_e
{
RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */
RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */
RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */
};
/* RTC FAST_CLK frequency values */
enum esp32s2_rtc_fast_freq_e
{
RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */
RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */
};
/* This is almost the same as esp32s2_rtc_slow_freq_e, except that we define
* an extra enum member for the external 32k oscillator. For convenience,
* lower 2 bits should correspond to esp32s2_rtc_slow_freq_e values.
*/
enum esp32s2_slow_clk_sel_e
{
/* Internal 150 kHz RC oscillator */
SLOW_CLK_150K = RTC_SLOW_FREQ_RTC,
/* External 32 kHz XTAL */
SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL,
/* Internal 8 MHz RC oscillator, divided by 256 */
SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256,
/* External 32k oscillator connected to 32K_XP pin */
SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG
};
/* Clock source to be calibrated using rtc_clk_cal function */
enum esp32s2_rtc_cal_sel_e
{
RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */
RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */
RTC_CAL_32K_XTAL = 2 /* External 32 kHz XTAL */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: esp32s2_rtc_get_slow_clk_rtc
*
* Description:
* Get slow_clk_rtc source.
*
* Input Parameters:
* None
*
* Returned Value:
* The clock source:
* - SLOW_CK
* - CK_XTAL_32K
* - CK8M_D256_OUT
*
****************************************************************************/
enum esp32s2_rtc_slow_freq_e esp32s2_rtc_get_slow_clk(void);
/****************************************************************************
* Name: esp32s2_rtc_clk_cal
*
* Description:
* Measure RTC slow clock's period, based on main XTAL frequency
*
* Input Parameters:
* cal_clk - clock to be measured
* slowclk_cycles - number of slow clock cycles to average
*
* Returned Value:
* Average slow clock period in microseconds, Q13.19 fixed point format
* or 0 if calibration has timed out
*
****************************************************************************/
uint32_t esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk,
uint32_t slowclk_cycles);
/****************************************************************************
* Name: esp32s2_rtc_clk_xtal_freq_get
*
* Description:
* Get main XTAL frequency
*
* Input Parameters:
* None
*
* Returned Value:
* XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values)
*
****************************************************************************/
enum esp32s2_rtc_xtal_freq_e esp32s2_rtc_clk_xtal_freq_get(void);
/****************************************************************************
* Name: esp32s2_rtc_update_to_xtal
*
* Description:
* Switch to XTAL frequency, does not disable the PLL
*
* Input Parameters:
* freq - XTAL frequency
* div - REF_TICK divider
*
* Returned Value:
* none
*
****************************************************************************/
void esp32s2_rtc_update_to_xtal(int freq, int div);
/****************************************************************************
* Name: esp32s2_rtc_bbpll_enable
*
* Description:
* Reset BBPLL configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_bbpll_enable(void);
/****************************************************************************
* Name: esp32s2_rtc_bbpll_configure
*
* Description:
* Configure main XTAL frequency values according to pll_freq.
*
* Input Parameters:
* xtal_freq - XTAL frequency values
* pll_freq - PLL frequency values
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_bbpll_configure(
enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq);
/****************************************************************************
* Name: esp32s2_rtc_clk_set
*
* Description:
* Set RTC CLK frequency.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_clk_set(void);
/****************************************************************************
* Name: esp32s2_rtc_init
*
* Description:
* Initialize RTC clock and power control related functions.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_init(void);
/****************************************************************************
* Name: esp32s2_rtc_time_get
*
* Description:
* Get current value of RTC counter.
*
* Input Parameters:
* None
*
* Returned Value:
* current value of RTC counter
*
****************************************************************************/
uint64_t esp32s2_rtc_time_get(void);
/****************************************************************************
* Name: esp32s2_rtc_wait_for_slow_cycle
*
* Description:
* Busy loop until next RTC_SLOW_CLK cycle.
*
* Input Parameters:
* None
*
* Returned Value:
* none
*
****************************************************************************/
void esp32s2_rtc_wait_for_slow_cycle(void);
/****************************************************************************
* Name: esp_rtc_clk_get_cpu_freq
*
* Description:
* Get the currently used CPU frequency configuration.
*
* Input Parameters:
* None
*
* Returned Value:
* CPU frequency
*
****************************************************************************/
int esp_rtc_clk_get_cpu_freq(void);
/****************************************************************************
* Name: esp32s2_rtc_sleep_init
*
* Description:
* Prepare the chip to enter sleep mode
*
* Input Parameters:
* flags - sleep mode configuration
*
* Returned Value:
* None
*
****************************************************************************/
void esp32s2_rtc_sleep_init(uint32_t flags);
/****************************************************************************
* Name: esp32s2_rtc_sleep_start
*
* Description:
* Enter force sleep mode.
*
* Input Parameters:
* wakeup_opt - bit mask wake up reasons to enable
* reject_opt - bit mask of sleep reject reasons.
*
* Returned Value:
* non-zero if sleep was rejected by hardware
*
****************************************************************************/
int esp32s2_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
#ifdef __cplusplus
}
#endif
#undef EXTERN
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H */

2
arch/xtensa/src/esp32s2/hardware/esp32s2_i2cbbpll.h
View File

@ -176,6 +176,8 @@
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 #define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 #define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
#define I2C_BBPLL_BBADC_CAL_7_0 12
#define I2C_BBPLL_ENT_PLL 10 #define I2C_BBPLL_ENT_PLL 10
#define I2C_BBPLL_ENT_PLL_MSB 3 #define I2C_BBPLL_ENT_PLL_MSB 3
#define I2C_BBPLL_ENT_PLL_LSB 3 #define I2C_BBPLL_ENT_PLL_LSB 3

37
arch/xtensa/src/esp32s2/hardware/esp32s2_soc.h
View File

@ -378,35 +378,16 @@
#define APB_CTRL_PRE_DIV_CNT_V 0x3ff #define APB_CTRL_PRE_DIV_CNT_V 0x3ff
#define APB_CTRL_PRE_DIV_CNT_S 0 #define APB_CTRL_PRE_DIV_CNT_S 0
#define I2C_BBPLL_IR_CAL_DELAY 0 /* ROM functions which read/write internal control bus */
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
#define I2C_BBPLL_OC_ENB_FCAL 4
#define I2C_BBPLL_OC_ENB_VCON 10
#define I2C_BBPLL_BBADC_CAL_7_0 12
#define I2C_BBPLL_OC_LREF 2 extern uint8_t rom_i2c_readreg(uint8_t block, uint8_t host_id,
#define I2C_BBPLL_OC_LREF_MSB 7 uint8_t reg_add);
#define I2C_BBPLL_OC_LREF_LSB 7 extern uint8_t rom_i2c_readreg_mask(uint8_t block, uint8_t host_id,
uint8_t reg_add, uint8_t msb, uint8_t lsb);
#define I2C_BBPLL_OC_DIV_7_0 3 extern void rom_i2c_writereg(uint8_t block, uint8_t host_id,
#define I2C_BBPLL_OC_DIV_7_0_MSB 7 uint8_t reg_add, uint8_t data);
#define I2C_BBPLL_OC_DIV_7_0_LSB 0 extern void rom_i2c_writereg_mask(uint8_t block, uint8_t host_id,
uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
#define I2C_BBPLL_BBADC_DSMP 9
#define I2C_BBPLL_BBADC_DSMP_MSB 7
#define I2C_BBPLL_BBADC_DSMP_LSB 4
#define I2C_BBPLL_OC_DCUR 5
#define I2C_BBPLL_OC_DCUR_MSB 2
#define I2C_BBPLL_OC_DCUR_LSB 0
#define I2C_BBPLL_ENDIV5 11
#define I2C_BBPLL 0x66
#define I2C_BBPLL_HOSTID 4
extern int rom_i2c_writereg(int block, int block_id, int reg_add,
int indata);
#define I2C_WRITEREG_RTC(block, reg_add, indata) \ #define I2C_WRITEREG_RTC(block, reg_add, indata) \
rom_i2c_writereg(block, block##_HOSTID, reg_add, indata) rom_i2c_writereg(block, block##_HOSTID, reg_add, indata)