From 068115e7d613108c016a7150441f2f29803148b8 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 8 Sep 2014 06:14:59 -0600 Subject: [PATCH] SAM3X/Arduino Due: Fix typo in sam3x_periphclks.h; add SCLK definitions to board.h header file. From Fabien Comte --- arch/arm/src/sam34/sam3x_periphclks.h | 4 ++-- arch/arm/src/sam34/sam_rtt.c | 2 +- arch/arm/src/sam34/sam_tc.c | 2 +- arch/arm/src/sam34/sam_wdt.c | 2 +- arch/arm/src/sama5/sam_wdt.c | 6 +++--- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/arm/src/sam34/sam3x_periphclks.h b/arch/arm/src/sam34/sam3x_periphclks.h index a6b106cc88..f20a86a0e8 100644 --- a/arch/arm/src/sam34/sam3x_periphclks.h +++ b/arch/arm/src/sam34/sam3x_periphclks.h @@ -52,8 +52,8 @@ #define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0) #define sam_enableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCER1) -#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PDER0) -#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PDER1) +#define sam_disableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCDR0) +#define sam_disableperiph1(s) putreg32((1 << ((s) - 32)), SAM_PMC_PCDR1) #define sam_supc_enableclk() sam_enableperiph0(SAM_PID_SUPC) #define sam_rstc_enableclk() sam_enableperiph0(SAM_PID_RSTC) diff --git a/arch/arm/src/sam34/sam_rtt.c b/arch/arm/src/sam34/sam_rtt.c index fc9ddd1706..e417a65650 100644 --- a/arch/arm/src/sam34/sam_rtt.c +++ b/arch/arm/src/sam34/sam_rtt.c @@ -67,7 +67,7 @@ # define RTT_PRES 1 #endif -#define RTT_FCLK (BOARD_SLCK_FREQUENCY/RTT_PRES) +#define RTT_FCLK (BOARD_SCLK_FREQUENCY/RTT_PRES) #define RTT_MAXTIMEOUT ((1000000ULL * (0x100000000ULL)) / RTT_FCLK) /* Configuration ************************************************************/ diff --git a/arch/arm/src/sam34/sam_tc.c b/arch/arm/src/sam34/sam_tc.c index b955d6bb03..1f866726a6 100644 --- a/arch/arm/src/sam34/sam_tc.c +++ b/arch/arm/src/sam34/sam_tc.c @@ -66,7 +66,7 @@ /* TODO: Allow selection of any of the input clocks */ -#define TC_FCLK (BOARD_SLCK_FREQUENCY) +#define TC_FCLK (BOARD_SCLK_FREQUENCY) #define TC_MAXTIMEOUT ((1000000ULL * (1ULL + TC_RVALUE_MASK)) / TC_FCLK) /* Configuration ************************************************************/ diff --git a/arch/arm/src/sam34/sam_wdt.c b/arch/arm/src/sam34/sam_wdt.c index 7886b78429..40d59d10a8 100644 --- a/arch/arm/src/sam34/sam_wdt.c +++ b/arch/arm/src/sam34/sam_wdt.c @@ -71,7 +71,7 @@ * 1000 * 64 / Fmin = 49.93 msec */ -#define WDT_FCLK (BOARD_SLCK_FREQUENCY / 128) +#define WDT_FCLK (BOARD_SCLK_FREQUENCY / 128) #define WDT_MAXTIMEOUT ((1000 * (WDT_MR_WDV_MAX+1)) / WDT_FCLK) /* Configuration ************************************************************/ diff --git a/arch/arm/src/sama5/sam_wdt.c b/arch/arm/src/sama5/sam_wdt.c index 8d8d10dcd8..706f8e8a39 100644 --- a/arch/arm/src/sama5/sam_wdt.c +++ b/arch/arm/src/sama5/sam_wdt.c @@ -61,11 +61,11 @@ * 32768 kHz). */ -#ifndef BOARD_SLCK_FREQUENCY -# define BOARD_SLCK_FREQUENCY 32768 +#ifndef BOARD_SCLK_FREQUENCY +# define BOARD_SCLK_FREQUENCY 32768 #endif -#define WDT_FREQUENCY (BOARD_SLCK_FREQUENCY / 128) +#define WDT_FREQUENCY (BOARD_SCLK_FREQUENCY / 128) /* At 32768Hz, the maximum timeout value will be: *