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arch: arm: cxd56xx: nxstyle updates

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Fix nxstyle complains

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2020-04-03 10:54:55 +02:00 committed by Abdelatif Guettouche
parent 55907b0062
commit 06910819e5
11 changed files with 483 additions and 344 deletions
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80
arch/arm/src/cxd56xx/cxd56_adc.c
View File

@ -277,7 +277,8 @@ static struct cxd56adc_dev_s g_hpadc1priv =
}; };
#endif #endif
static bool adc_active[CH_MAX] = { static bool adc_active[CH_MAX] =
{
false, false, false, false, false, false false, false, false, false, false, false
}; };
@ -362,39 +363,44 @@ static int adc_start(adc_ch_t ch, uint8_t freq, FAR struct seq_s *seq,
aerr("SETFIFO failed. %d\n", ret); aerr("SETFIFO failed. %d\n", ret);
return ret; return ret;
} }
ret = seq_ioctl(seq, 0, SCUIOC_SETFIFOMODE, fifomode); ret = seq_ioctl(seq, 0, SCUIOC_SETFIFOMODE, fifomode);
if (ret < 0) if (ret < 0)
{ {
aerr("SETFIFOMODE failed. %d\n", ret); aerr("SETFIFOMODE failed. %d\n", ret);
return ret; return ret;
} }
if (wm)
{ if (wm)
ret = seq_ioctl(seq, 0, SCUIOC_SETWATERMARK, (unsigned long)wm); {
if (ret < 0) ret = seq_ioctl(seq, 0, SCUIOC_SETWATERMARK, (unsigned long)wm);
{ if (ret < 0)
aerr("SETWATERMARK failed. %d\n", ret); {
return ret; aerr("SETWATERMARK failed. %d\n", ret);
} return ret;
} }
if (filter) }
{
ret = seq_ioctl(seq, 0, SCUIOC_SETFILTER, (unsigned long)filter); if (filter)
if (ret < 0) {
{ ret = seq_ioctl(seq, 0, SCUIOC_SETFILTER, (unsigned long)filter);
aerr("SETFILTER failed. %d\n", ret); if (ret < 0)
return ret; {
} aerr("SETFILTER failed. %d\n", ret);
} return ret;
if (notify) }
{ }
ret = seq_ioctl(seq, 0, SCUIOC_SETNOTIFY, (unsigned long)notify);
if (ret < 0) if (notify)
{ {
aerr("SETNOTIFY failed. %d\n", ret); ret = seq_ioctl(seq, 0, SCUIOC_SETNOTIFY, (unsigned long)notify);
return ret; if (ret < 0)
} {
} aerr("SETNOTIFY failed. %d\n", ret);
return ret;
}
}
if (ch <= CH3) if (ch <= CH3)
{ {
/* LPADC.A1 LPADC_CH : todo: GPS ch */ /* LPADC.A1 LPADC_CH : todo: GPS ch */
@ -469,6 +475,7 @@ static int adc_start(adc_ch_t ch, uint8_t freq, FAR struct seq_s *seq,
{ {
val = 0x00000030; val = 0x00000030;
} }
#endif #endif
putreg32(val, SCUADCIF_HPADC_AC0); putreg32(val, SCUADCIF_HPADC_AC0);
#endif #endif
@ -554,6 +561,7 @@ static int adc_start(adc_ch_t ch, uint8_t freq, FAR struct seq_s *seq,
(uint32_t *)SCUADCIF_HPADC1_D2; (uint32_t *)SCUADCIF_HPADC1_D2;
putreg32(1, addr); putreg32(1, addr);
} }
adc_active[ch] = true; adc_active[ch] = true;
} }
else else
@ -603,6 +611,7 @@ static int adc_stop(adc_ch_t ch, FAR struct seq_s *seq)
break; break;
} }
} }
if (is_clockdisable) if (is_clockdisable)
{ {
cxd56_lpadc_clock_disable(); cxd56_lpadc_clock_disable();
@ -646,6 +655,7 @@ static bool adc_validcheck(int cmd)
{ {
return true; return true;
} }
return false; return false;
} }
@ -689,6 +699,7 @@ static int cxd56_adc_open(FAR struct file *filep)
{ {
return ret; return ret;
} }
ainfo("open ch%d freq%d scufifo%d\n", priv->ch, priv->freq, priv->fsize); ainfo("open ch%d freq%d scufifo%d\n", priv->ch, priv->freq, priv->fsize);
return OK; return OK;
@ -721,11 +732,13 @@ static int cxd56_adc_close(FAR struct file *filep)
kmm_free(priv->wm); kmm_free(priv->wm);
priv->wm = NULL; priv->wm = NULL;
} }
if (priv->filter) if (priv->filter)
{ {
kmm_free(priv->filter); kmm_free(priv->filter);
priv->filter = NULL; priv->filter = NULL;
} }
if (priv->notify) if (priv->notify)
{ {
kmm_free(priv->notify); kmm_free(priv->notify);
@ -876,8 +889,8 @@ static int cxd56_adc_ioctl(FAR struct file *filep, int cmd,
* get sampling interval of ADC. * get sampling interval of ADC.
* *
* Input Parameters: * Input Parameters:
* bustype - SCU_BUS_LPADC0, SCU_BUS_LPADC1, SCU_BUS_LPADC2, SCU_BUS_LPADC3, * bustype - SCU_BUS_LPADC0, SCU_BUS_LPADC1, SCU_BUS_LPADC2,
* SCU_BUS_HPADC0, SCU_BUS_HPADC1 * SCU_BUS_LPADC3, SCU_BUS_HPADC0, SCU_BUS_HPADC1
* *interval - Sampling interval * *interval - Sampling interval
* *adjust - Adjustment value used for timestamp calculation * *adjust - Adjustment value used for timestamp calculation
* *
@ -972,6 +985,7 @@ void cxd56_adc_getinterval(int adctype, uint32_t *interval, uint16_t *adjust)
{ {
freq /= 6; freq /= 6;
} }
#endif #endif
if (freq > 0) if (freq > 0)
{ {
@ -1015,6 +1029,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc0): %d\n", ret); aerr("Failed to register driver(lpadc0): %d\n", ret);
return ret; return ret;
} }
#endif #endif
#if defined (CONFIG_CXD56_LPADC1) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL) #if defined (CONFIG_CXD56_LPADC1) || defined (CONFIG_CXD56_LPADC0_1) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc1", &g_adcops, 0666, &g_lpadc1priv); ret = register_driver("/dev/lpadc1", &g_adcops, 0666, &g_lpadc1priv);
@ -1023,6 +1038,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc1): %d\n", ret); aerr("Failed to register driver(lpadc1): %d\n", ret);
return ret; return ret;
} }
#endif #endif
#if defined (CONFIG_CXD56_LPADC2) || defined (CONFIG_CXD56_LPADC_ALL) #if defined (CONFIG_CXD56_LPADC2) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc2", &g_adcops, 0666, &g_lpadc2priv); ret = register_driver("/dev/lpadc2", &g_adcops, 0666, &g_lpadc2priv);
@ -1031,6 +1047,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc2): %d\n", ret); aerr("Failed to register driver(lpadc2): %d\n", ret);
return ret; return ret;
} }
#endif #endif
#if defined (CONFIG_CXD56_LPADC3) || defined (CONFIG_CXD56_LPADC_ALL) #if defined (CONFIG_CXD56_LPADC3) || defined (CONFIG_CXD56_LPADC_ALL)
ret = register_driver("/dev/lpadc3", &g_adcops, 0666, &g_lpadc3priv); ret = register_driver("/dev/lpadc3", &g_adcops, 0666, &g_lpadc3priv);
@ -1039,6 +1056,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(lpadc3): %d\n", ret); aerr("Failed to register driver(lpadc3): %d\n", ret);
return ret; return ret;
} }
#endif #endif
#ifdef CONFIG_CXD56_HPADC0 #ifdef CONFIG_CXD56_HPADC0
ret = register_driver("/dev/hpadc0", &g_adcops, 0666, &g_hpadc0priv); ret = register_driver("/dev/hpadc0", &g_adcops, 0666, &g_hpadc0priv);
@ -1047,6 +1065,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(hpadc0): %d\n", ret); aerr("Failed to register driver(hpadc0): %d\n", ret);
return ret; return ret;
} }
#endif #endif
#ifdef CONFIG_CXD56_HPADC1 #ifdef CONFIG_CXD56_HPADC1
ret = register_driver("/dev/hpadc1", &g_adcops, 0666, &g_hpadc1priv); ret = register_driver("/dev/hpadc1", &g_adcops, 0666, &g_hpadc1priv);
@ -1055,6 +1074,7 @@ int cxd56_adcinitialize(void)
aerr("Failed to register driver(hpadc1): %d\n", ret); aerr("Failed to register driver(hpadc1): %d\n", ret);
return ret; return ret;
} }
#endif #endif
return ret; return ret;

5
arch/arm/src/cxd56xx/cxd56_adc.h
View File

@ -54,7 +54,7 @@ extern "C"
#endif #endif
/**************************************************************************** /****************************************************************************
* Public Functions * Public Function Protoypes
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
@ -65,7 +65,8 @@ extern "C"
****************************************************************************/ ****************************************************************************/
#ifdef CONFIG_CXD56_ADC #ifdef CONFIG_CXD56_ADC
void cxd56_adc_getinterval(int adctype, uint32_t *interval, uint16_t *adjust); void cxd56_adc_getinterval(int adctype, uint32_t *interval,
uint16_t *adjust);
#else #else
#define cxd56_adc_getinterval(adctype, interval, adjust) #define cxd56_adc_getinterval(adctype, interval, adjust)
#endif #endif

2
arch/arm/src/cxd56xx/cxd56_backuplog.c
View File

@ -143,6 +143,7 @@ static void *get_allocated_memory(const char *name, size_t size)
up_backuplog_free(name); up_backuplog_free(name);
} }
} }
return NULL; return NULL;
} }
@ -163,6 +164,7 @@ static int allocate_memory(size_t size)
allocated = i; allocated = i;
break; break;
} }
alloc_bits <<= 1; alloc_bits <<= 1;
} }

81
arch/arm/src/cxd56xx/cxd56_clock.c
View File

@ -35,6 +35,7 @@
* POSSIBILITY OF SUCH DAMAGE. * POSSIBILITY OF SUCH DAMAGE.
* *
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Included Files * Included Files
****************************************************************************/ ****************************************************************************/
@ -111,7 +112,8 @@
* Private Types * Private Types
****************************************************************************/ ****************************************************************************/
enum clock_source { enum clock_source
{
RCOSC = 1, RCOSC = 1,
RTC, RTC,
RCRTC, RCRTC,
@ -139,13 +141,13 @@ struct power_domain
static void cxd56_img_clock_enable(void); static void cxd56_img_clock_enable(void);
static void cxd56_img_clock_disable(void); static void cxd56_img_clock_disable(void);
static void cxd56_scu_clock_ctrl(\ static void cxd56_scu_clock_ctrl(\
uint32_t block, uint32_t intr, int on); uint32_t block, uint32_t intr, int on);
static void cxd56_scu_peri_clock_enable(\ static void cxd56_scu_peri_clock_enable(\
FAR const struct scu_peripheral *p) __unused; FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_disable(\ static void cxd56_scu_peri_clock_disable(\
FAR const struct scu_peripheral *p) __unused; FAR const struct scu_peripheral *p) __unused;
static void cxd56_scu_peri_clock_gating(\ static void cxd56_scu_peri_clock_gating(\
FAR const struct scu_peripheral *p, int enable) __unused; FAR const struct scu_peripheral *p, int enable) __unused;
/**************************************************************************** /****************************************************************************
* Public Data * Public Data
@ -177,7 +179,8 @@ static sem_t g_clockexc = SEM_INITIALIZER(1);
* swreset : SWRESET_SCU * swreset : SWRESET_SCU
* crgintmask : CRG_INT_CLR0, CRG_INT_STAT_RAW0 * crgintmask : CRG_INT_CLR0, CRG_INT_STAT_RAW0
* *
* Each member values are indicated the number of bit in appropriate registers. * Each member values are indicated the number of bit
* in appropriate registers.
*/ */
#if defined(CONFIG_CXD56_SPI3) #if defined(CONFIG_CXD56_SPI3)
@ -305,6 +308,7 @@ static void enable_pwd(int pdid)
do_power_control(); do_power_control();
release_pwd_reset(domain); release_pwd_reset(domain);
} }
g_digital.refs[pdid]++; g_digital.refs[pdid]++;
} }
@ -336,6 +340,7 @@ static void enable_apwd(int apdid)
putreg32(domain | (domain << 16), CXD56_TOPREG_ANA_PW_CTL); putreg32(domain | (domain << 16), CXD56_TOPREG_ANA_PW_CTL);
do_power_control(); do_power_control();
} }
g_analog.refs[apdid]++; g_analog.refs[apdid]++;
} }
@ -359,6 +364,7 @@ static void disable_apwd(int apdid)
/**************************************************************************** /****************************************************************************
* Public Functions * Public Functions
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: cxd56_rcosc_enable * Name: cxd56_rcosc_enable
* *
@ -403,8 +409,8 @@ void cxd56_xosc_enable(void)
* Disable XOSC. * Disable XOSC.
* *
* CAUTION: * CAUTION:
* This function is tentative. We need to consider that clock source control * This function is tentative. We need to consider that
* with other devices which XOSC is used. * clock source control with other devices which XOSC is used.
* *
****************************************************************************/ ****************************************************************************/
@ -846,7 +852,8 @@ static void cxd56_spim_clock_enable(void)
busy_wait(10); busy_wait(10);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN); putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF,
CXD56_TOPREG_SYSIOP_SUB_CKEN);
rst = getreg32(CXD56_TOPREG_SWRESET_BUS); rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
putreg32(rst | XRST_SPIM, CXD56_TOPREG_SWRESET_BUS); putreg32(rst | XRST_SPIM, CXD56_TOPREG_SWRESET_BUS);
putreg32(val | CK_SPIM | CK_COM_BRG | putreg32(val | CK_SPIM | CK_COM_BRG |
@ -966,24 +973,28 @@ void cxd56_spi_clock_enable(int port)
{ {
cxd56_img_spi_clock_enable(); cxd56_img_spi_clock_enable();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI5) #if defined(CONFIG_CXD56_SPI5)
if (port == 5) if (port == 5)
{ {
cxd56_img_wspi_clock_enable(); cxd56_img_wspi_clock_enable();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI0) #if defined(CONFIG_CXD56_SPI0)
if (port == 0) if (port == 0)
{ {
cxd56_spim_clock_enable(); cxd56_spim_clock_enable();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI3) #if defined(CONFIG_CXD56_SPI3)
if (port == 3) if (port == 3)
{ {
cxd56_scu_peri_clock_enable(&g_scuspi); cxd56_scu_peri_clock_enable(&g_scuspi);
} }
#endif #endif
} }
@ -994,24 +1005,28 @@ void cxd56_spi_clock_disable(int port)
{ {
cxd56_img_spi_clock_disable(); cxd56_img_spi_clock_disable();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI5) #if defined(CONFIG_CXD56_SPI5)
if (port == 5) if (port == 5)
{ {
cxd56_img_wspi_clock_disable(); cxd56_img_wspi_clock_disable();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI0) #if defined(CONFIG_CXD56_SPI0)
if (port == 0) if (port == 0)
{ {
cxd56_spim_clock_disable(); cxd56_spim_clock_disable();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI3) #if defined(CONFIG_CXD56_SPI3)
if (port == 3) if (port == 3)
{ {
cxd56_scu_peri_clock_disable(&g_scuspi); cxd56_scu_peri_clock_disable(&g_scuspi);
} }
#endif #endif
} }
@ -1098,13 +1113,16 @@ void cxd56_spi_clock_gear_adjust(int port, uint32_t maxfreq)
{ {
divisor += 1; divisor += 1;
} }
if (divisor > maxdivisor) if (divisor > maxdivisor)
{ {
divisor = maxdivisor; divisor = maxdivisor;
} }
gear = 0x00010000 | divisor; gear = 0x00010000 | divisor;
putreg32(gear, addr); putreg32(gear, addr);
} }
clock_semgive(&g_clockexc); clock_semgive(&g_clockexc);
} }
@ -1132,7 +1150,8 @@ static void cxd56_i2cm_clock_enable(void)
busy_wait(10); busy_wait(10);
putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF, CXD56_TOPREG_SYSIOP_SUB_CKEN); putreg32(val | CK_COM_BRG | CK_AHB_BRG_COMIF,
CXD56_TOPREG_SYSIOP_SUB_CKEN);
rst = getreg32(CXD56_TOPREG_SWRESET_BUS); rst = getreg32(CXD56_TOPREG_SWRESET_BUS);
putreg32(rst | XRST_I2CM, CXD56_TOPREG_SWRESET_BUS); putreg32(rst | XRST_I2CM, CXD56_TOPREG_SWRESET_BUS);
putreg32(val | CK_I2CM | CK_COM_BRG | putreg32(val | CK_I2CM | CK_COM_BRG |
@ -1184,18 +1203,21 @@ void cxd56_i2c_clock_enable(int port)
{ {
cxd56_scu_peri_clock_enable(&g_scui2c0); cxd56_scu_peri_clock_enable(&g_scui2c0);
} }
#endif #endif
#if defined(CONFIG_CXD56_I2C1) #if defined(CONFIG_CXD56_I2C1)
if (port == 1) if (port == 1)
{ {
cxd56_scu_peri_clock_enable(&g_scui2c1); cxd56_scu_peri_clock_enable(&g_scui2c1);
} }
#endif #endif
#if defined(CONFIG_CXD56_I2C2) #if defined(CONFIG_CXD56_I2C2)
if (port == 2) if (port == 2)
{ {
cxd56_i2cm_clock_enable(); cxd56_i2cm_clock_enable();
} }
#endif #endif
} }
@ -1213,18 +1235,21 @@ void cxd56_i2c_clock_disable(int port)
{ {
cxd56_scu_peri_clock_disable(&g_scui2c0); cxd56_scu_peri_clock_disable(&g_scui2c0);
} }
#endif #endif
#if defined(CONFIG_CXD56_I2C1) #if defined(CONFIG_CXD56_I2C1)
if (port == 1) if (port == 1)
{ {
cxd56_scu_peri_clock_disable(&g_scui2c1); cxd56_scu_peri_clock_disable(&g_scui2c1);
} }
#endif #endif
#if defined(CONFIG_CXD56_I2C2) #if defined(CONFIG_CXD56_I2C2)
if (port == 2) if (port == 2)
{ {
cxd56_i2cm_clock_disable(); cxd56_i2cm_clock_disable();
} }
#endif #endif
} }
@ -1242,12 +1267,14 @@ void cxd56_i2c_clock_gate_enable(int port)
{ {
cxd56_scu_peri_clock_gating(&g_scui2c0, 1); cxd56_scu_peri_clock_gating(&g_scui2c0, 1);
} }
#endif #endif
#if defined(CONFIG_CXD56_I2C1) #if defined(CONFIG_CXD56_I2C1)
if (port == 1) if (port == 1)
{ {
cxd56_scu_peri_clock_gating(&g_scui2c1, 1); cxd56_scu_peri_clock_gating(&g_scui2c1, 1);
} }
#endif #endif
} }
@ -1265,32 +1292,34 @@ void cxd56_i2c_clock_gate_disable(int port)
{ {
cxd56_scu_peri_clock_gating(&g_scui2c0, 0); cxd56_scu_peri_clock_gating(&g_scui2c0, 0);
} }
#endif #endif
#if defined(CONFIG_CXD56_I2C1) #if defined(CONFIG_CXD56_I2C1)
if (port == 1) if (port == 1)
{ {
cxd56_scu_peri_clock_gating(&g_scui2c1, 0); cxd56_scu_peri_clock_gating(&g_scui2c1, 0);
} }
#endif #endif
} }
uint32_t cxd56_get_img_uart_baseclock(void) uint32_t cxd56_get_img_uart_baseclock(void)
{ {
uint32_t val; uint32_t val;
int n; int n;
int m; int m;
val = getreg32(CXD56_CRG_GEAR_IMG_UART); val = getreg32(CXD56_CRG_GEAR_IMG_UART);
n = (val >> 16) & 1; n = (val >> 16) & 1;
m = val & 0x7f; m = val & 0x7f;
if (n && m) if (n && m)
{ {
return cxd56_get_appsmp_baseclock() * n / m; return cxd56_get_appsmp_baseclock() * n / m;
} }
else else
{ {
return 0; return 0;
} }
} }
@ -1649,24 +1678,28 @@ uint32_t cxd56_get_spi_baseclock(int port)
{ {
return cxd56_get_img_spi_baseclock(); return cxd56_get_img_spi_baseclock();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI5) #if defined(CONFIG_CXD56_SPI5)
if (port == 5) if (port == 5)
{ {
return cxd56_get_img_wspi_baseclock(); return cxd56_get_img_wspi_baseclock();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI0) #if defined(CONFIG_CXD56_SPI0)
if (port == 0) if (port == 0)
{ {
return cxd56_get_com_baseclock(); return cxd56_get_com_baseclock();
} }
#endif #endif
#if defined(CONFIG_CXD56_SPI3) #if defined(CONFIG_CXD56_SPI3)
if (port == 3) if (port == 3)
{ {
return cxd56_get_scu_baseclock(); return cxd56_get_scu_baseclock();
} }
#endif #endif
return 0; return 0;
} }
@ -1678,18 +1711,21 @@ uint32_t cxd56_get_i2c_baseclock(int port)
{ {
return cxd56_get_scu_baseclock(); return cxd56_get_scu_baseclock();
} }
#endif #endif
#if defined(CONFIG_CXD56_I2C1) #if defined(CONFIG_CXD56_I2C1)
if (port == 1) if (port == 1)
{ {
return cxd56_get_scu_baseclock(); return cxd56_get_scu_baseclock();
} }
#endif #endif
#if defined(CONFIG_CXD56_I2C2) #if defined(CONFIG_CXD56_I2C2)
if (port == 2) if (port == 2)
{ {
return cxd56_get_com_baseclock(); return cxd56_get_com_baseclock();
} }
#endif #endif
return 0; return 0;
} }
@ -1753,6 +1789,7 @@ static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
return; return;
} }
putreg32(val | block, CXD56_TOPREG_SCU_CKEN); putreg32(val | block, CXD56_TOPREG_SCU_CKEN);
} }
else else
@ -1763,6 +1800,7 @@ static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
return; return;
} }
putreg32(val & ~block, CXD56_TOPREG_SCU_CKEN); putreg32(val & ~block, CXD56_TOPREG_SCU_CKEN);
} }
@ -1771,6 +1809,7 @@ static void cxd56_scu_clock_ctrl(uint32_t block, uint32_t intr, int on)
stat = getreg32(CXD56_TOPREG_CRG_INT_STAT_RAW0); stat = getreg32(CXD56_TOPREG_CRG_INT_STAT_RAW0);
busy_wait(1000); busy_wait(1000);
} }
while (retry-- && !(stat & intr)); while (retry-- && !(stat & intr));
putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0); putreg32(0xffffffff, CXD56_TOPREG_CRG_INT_CLR0);
@ -1814,7 +1853,8 @@ static void cxd56_scu_clock_enable(void)
/* Enable each blocks in SCU */ /* Enable each blocks in SCU */
val = getreg32(CXD56_TOPREG_SCU_CKEN); val = getreg32(CXD56_TOPREG_SCU_CKEN);
putreg32(val | SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ, CXD56_TOPREG_SCU_CKEN); putreg32(val | SCU_SCU | SCU_SC | SCU_32K | SCU_SEQ,
CXD56_TOPREG_SCU_CKEN);
do do
{ {
@ -2350,6 +2390,7 @@ int up_pmramctrl(int cmd, uintptr_t addr, size_t size)
val |= 1 << i; val |= 1 << i;
} }
} }
putreg32(val, CXD56_CRG_APP_TILE_CLK_GATING_ENB); putreg32(val, CXD56_CRG_APP_TILE_CLK_GATING_ENB);
} }

2
arch/arm/src/cxd56xx/cxd56_clock.h
View File

@ -71,7 +71,7 @@ extern "C"
#endif #endif
/**************************************************************************** /****************************************************************************
* Public Functions * Public Function Prototypes
****************************************************************************/ ****************************************************************************/
/**************************************************************************** /****************************************************************************

8
arch/arm/src/cxd56xx/cxd56_config.h
View File

@ -56,8 +56,8 @@
# define HAVE_UART 1 # define HAVE_UART 1
#endif #endif
/* Make sure all features are disabled for disabled U[S]ARTs. This simplifies /* Make sure all features are disabled for disabled U[S]ARTs.
* checking later. * This simplifies checking later.
*/ */
#ifndef CONFIG_CXD56_UART0 #ifndef CONFIG_CXD56_UART0
@ -131,8 +131,4 @@
* Public Data * Public Data
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Public Functions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CONFIG_H */ #endif /* __ARCH_ARM_SRC_CXD56XX_CXD56_CONFIG_H */

4
arch/arm/src/cxd56xx/cxd56_cpufifo.c
View File

@ -33,6 +33,10 @@
* *
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>

1
arch/arm/src/cxd56xx/cxd56_delay.c
View File

@ -112,6 +112,7 @@ void up_udelay(useconds_t microseconds)
{ {
} }
} }
loops = loops * (microseconds % 1000) / CXD56XX_LOOPSPERUSEC_ADJUST; loops = loops * (microseconds % 1000) / CXD56XX_LOOPSPERUSEC_ADJUST;
for (i = 0; i < loops; i++) for (i = 0; i < loops; i++)
{ {

624
arch/arm/src/cxd56xx/cxd56_dmac.c
View File

@ -33,6 +33,10 @@
* *
****************************************************************************/ ****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/kmalloc.h> #include <nuttx/kmalloc.h>
@ -65,68 +69,72 @@
#define __WO volatile #define __WO volatile
#define __RW volatile #define __RW volatile
struct dmac_ch_register_map { struct dmac_ch_register_map
__RW uint32_t srcaddr; {
__RW uint32_t destaddr; __RW uint32_t srcaddr;
__RW uint32_t lli; __RW uint32_t destaddr;
__RW uint32_t control; __RW uint32_t lli;
__RW uint32_t configuration; __RW uint32_t control;
uint32_t reserved[3]; __RW uint32_t configuration;
uint32_t reserved[3];
}; };
struct dmac080_ch_register_map { struct dmac080_ch_register_map
__RW uint32_t srcaddr; {
__RW uint32_t destaddr; __RW uint32_t srcaddr;
__RW uint32_t lli; __RW uint32_t destaddr;
__RW uint32_t control; __RW uint32_t lli;
__RW uint32_t configuration; __RW uint32_t control;
__RW uint32_t deflli; __RW uint32_t configuration;
uint32_t reserved[2]; __RW uint32_t deflli;
uint32_t reserved[2];
}; };
struct dmac_register_map { struct dmac_register_map
__RO uint32_t intstatus; {
__RO uint32_t inttcstatus; __RO uint32_t intstatus;
__WO uint32_t inttcclear; __RO uint32_t inttcstatus;
__RO uint32_t interrorstatus; __WO uint32_t inttcclear;
__WO uint32_t interrorclear; __RO uint32_t interrorstatus;
__RO uint32_t rawinttcstatus; __WO uint32_t interrorclear;
__RO uint32_t rawinterrorstatus; __RO uint32_t rawinttcstatus;
__RO uint32_t enbldchns; __RO uint32_t rawinterrorstatus;
__RW uint32_t softbreq; __RO uint32_t enbldchns;
__RW uint32_t softsreq; __RW uint32_t softbreq;
__RW uint32_t softlbreq; __RW uint32_t softsreq;
__RW uint32_t softlsreq; __RW uint32_t softlbreq;
__RW uint32_t configuration; __RW uint32_t softlsreq;
__RW uint32_t sync; __RW uint32_t configuration;
__RW uint32_t sync;
uint32_t reserved0[50]; uint32_t reserved0[50];
struct dmac_ch_register_map channel[2]; struct dmac_ch_register_map channel[2];
}; };
struct dmac080_register_map { struct dmac080_register_map
__RO uint32_t intstatus; {
__RO uint32_t inttcstatus; __RO uint32_t intstatus;
__WO uint32_t inttcclear; __RO uint32_t inttcstatus;
__RO uint32_t interrorstatus; __WO uint32_t inttcclear;
__WO uint32_t interrorclear; __RO uint32_t interrorstatus;
__RO uint32_t rawinttcstatus; __WO uint32_t interrorclear;
__RO uint32_t rawinterrorstatus; __RO uint32_t rawinttcstatus;
__RO uint32_t enbldchns; __RO uint32_t rawinterrorstatus;
__RW uint32_t softbreq; __RO uint32_t enbldchns;
__RW uint32_t softsreq; __RW uint32_t softbreq;
__RW uint32_t softlbreq; __RW uint32_t softsreq;
__RW uint32_t softlsreq; __RW uint32_t softlbreq;
__RW uint32_t configuration; __RW uint32_t softlsreq;
__RW uint32_t sync; __RW uint32_t configuration;
__RW uint32_t sreqmask; __RW uint32_t sync;
__RW uint32_t sreqmask;
uint32_t reserved0[49]; uint32_t reserved0[49];
/* XXX: deflli not supported */ /* XXX: deflli not supported */
struct dmac_ch_register_map channel[5]; struct dmac_ch_register_map channel[5];
}; };
#define DMAC_CH_ENABLE (1u<<0) #define DMAC_CH_ENABLE (1u<<0)
@ -137,15 +145,16 @@ struct dmac080_register_map {
#define itemsof(a) (sizeof(a)/sizeof(a[0])) #define itemsof(a) (sizeof(a)/sizeof(a[0]))
#endif #endif
/** /****************************************************************************
* Link list item structure for use scatter/gather operation * Link list item structure for use scatter/gather operation
*/ ****************************************************************************/
typedef struct { typedef struct
uint32_t src_addr; /**< Source address */ {
uint32_t dest_addr; /**< Destination address */ uint32_t src_addr; /* Source address */
uint32_t nextlli; /**< Next link list */ uint32_t dest_addr; /* Destination address */
uint32_t control; /**< Transfer control */ uint32_t nextlli; /* Next link list */
uint32_t control; /* Transfer control */
} dmac_lli_t; } dmac_lli_t;
#define CXD56_DMAC_M2M 0 /**< Memory to memory */ #define CXD56_DMAC_M2M 0 /**< Memory to memory */
@ -176,66 +185,63 @@ typedef struct {
#define CXD56_DMAC_MAX_SIZE 0xfff #define CXD56_DMAC_MAX_SIZE 0xfff
/** /****************************************************************************
* Helper macro for construct transfer control parameter. * Helper macro for construct transfer control parameter.
* Each parameters are the same with PD_DmacSetControl(). * Each parameters are the same with PD_DmacSetControl().
* *
* @par Example: * Example:
* Here is an example for transfer setting with no interrupt, * Here is an example for transfer setting with no interrupt,
* address increments, 4 byte, 4 burst and 16380 bytes (4 x 4095). * address increments, 4 byte, 4 burst and 16380 bytes (4 x 4095).
* *
* @code
* list.control = PD_DmacCtrlHelper(0, 1, 1, * list.control = PD_DmacCtrlHelper(0, 1, 1,
* PD_DMAC_WIDTH32, PD_DMAC_WIDTH32, * PD_DMAC_WIDTH32, PD_DMAC_WIDTH32,
* PD_DMAC_BSIZE4, PD_DMAC_BSIZE4, * PD_DMAC_BSIZE4, PD_DMAC_BSIZE4,
* 0xfffu); * 0xfffu);
* @endcode ****************************************************************************/
*/
#define DMAC_CTRL_HELPER(intr, di, si, dwidth, swidth, dbsize, sbsize, tsize) \ #define DMAC_CTRL_HELPER(intr, di, si, dwidth, swidth, dbsize, sbsize, tsize) \
(((intr) & 1u) << 31 | \ (((intr) & 1u) << 31 | \
((di) & 1u) << 27 | \ ((di) & 1u) << 27 | \
((si) & 1u) << 26 | \ ((si) & 1u) << 26 | \
((dwidth) & 7u) << 21 | \ ((dwidth) & 7u) << 21 | \
((swidth) & 7u) << 18 | \ ((swidth) & 7u) << 18 | \
((dbsize) & 7u) << 15 | \ ((dbsize) & 7u) << 15 | \
((sbsize) & 7u) << 12 | \ ((sbsize) & 7u) << 12 | \
((tsize) & 0xfffu)) ((tsize) & 0xfffu))
/** /****************************************************************************
* Helper macro for construct transfer control parameter * Helper macro for construct transfer control parameter
* (for APP DMAC channel 2 - 6). * (for APP DMAC channel 2 - 6).
* Each parameters are the same with PD_DmacSetExControl(). * Each parameters are the same with PD_DmacSetExControl().
* *
* @par Example: * Example:
* Here is an example for transfer setting with no interrupt, * Here is an example for transfer setting with no interrupt,
* address increments, 4 byte, 4 burst and 16380 bytes (4 x 4095). * address increments, 4 byte, 4 burst and 16380 bytes (4 x 4095).
* *
* @code
* list.control = PD_DmacExCtrlHelper(0, 1, 1, 0, 0, * list.control = PD_DmacExCtrlHelper(0, 1, 1, 0, 0,
* PD_DMAC_WIDTH32, PD_DMAC_WIDTH32, * PD_DMAC_WIDTH32, PD_DMAC_WIDTH32,
* PD_DMAC_BSIZE4, PD_DMAC_BSIZE4, * PD_DMAC_BSIZE4, PD_DMAC_BSIZE4,
* 0xfffu); * 0xfffu);
* @endcode
* *
* @note If you want to different burst sizes to source and destination, * If you want to different burst sizes to source and destination,
* then data may remained in FIFO. In this case, DMAC cannot clear them. * then data may remained in FIFO. In this case, DMAC cannot clear them.
* Do not use this configuration to transferring unknown size data (especially * Do not use this configuration to transferring unknown size data
* communication peripherals). I recommend the same setting to burst sizes. * (especially communication peripherals).
*/ * I recommend the same setting to burst sizes.
****************************************************************************/
#define DMAC_EX_CTRL_HELPER(\ #define DMAC_EX_CTRL_HELPER(\
intr, di, si, dmaster, smaster, dwidth, swidth, dbsize, sbsize, tsize) \ intr, di, si, dmaster, smaster, dwidth, swidth, dbsize, sbsize, tsize) \
(((intr) & 1u) << 31 | \ (((intr) & 1u) << 31 | \
((di) & 1u) << 30 | \ ((di) & 1u) << 30 | \
((si) & 1u) << 29 | \ ((si) & 1u) << 29 | \
((dmaster) & 1u) << 28 | \ ((dmaster) & 1u) << 28 | \
((smaster) & 1u) << 27 | \ ((smaster) & 1u) << 27 | \
((dwidth) & 3u) << 25 | \ ((dwidth) & 3u) << 25 | \
((swidth) & 3u) << 23 | \ ((swidth) & 3u) << 23 | \
((dbsize) & 3u) << 21 | \ ((dbsize) & 3u) << 21 | \
((sbsize) & 3u) << 19 | \ ((sbsize) & 3u) << 19 | \
((tsize) & 0x7ffffu)) ((tsize) & 0x7ffffu))
static int open_channels = 0; static int open_channels = 0;
@ -244,28 +250,30 @@ static int intr_handler_admac1(int irq, FAR void *context, FAR void *arg);
static int intr_handler_idmac(int irq, FAR void *context, FAR void *arg); static int intr_handler_idmac(int irq, FAR void *context, FAR void *arg);
static int intr_handler_skdmac0(int irq, FAR void *context, FAR void *arg); static int intr_handler_skdmac0(int irq, FAR void *context, FAR void *arg);
static int intr_handler_skdmac1(int irq, FAR void *context, FAR void *arg); static int intr_handler_skdmac1(int irq, FAR void *context, FAR void *arg);
static uint32_t irq_map[] = { static uint32_t irq_map[] =
CXD56_IRQ_APP_DMAC0, {
CXD56_IRQ_APP_DMAC1, CXD56_IRQ_APP_DMAC0,
CXD56_IRQ_IDMAC, CXD56_IRQ_APP_DMAC1,
CXD56_IRQ_IDMAC, CXD56_IRQ_IDMAC,
CXD56_IRQ_IDMAC, CXD56_IRQ_IDMAC,
CXD56_IRQ_IDMAC, CXD56_IRQ_IDMAC,
CXD56_IRQ_IDMAC, CXD56_IRQ_IDMAC,
CXD56_IRQ_SKDMAC_0, CXD56_IRQ_IDMAC,
CXD56_IRQ_SKDMAC_1, CXD56_IRQ_SKDMAC_0,
CXD56_IRQ_SKDMAC_1,
}; };
static int (*intc_handler[])(int irq, FAR void *context, FAR void *arg) = { static int (*intc_handler[])(int irq, FAR void *context, FAR void *arg) =
intr_handler_admac0, {
intr_handler_admac1, intr_handler_admac0,
intr_handler_idmac, intr_handler_admac1,
intr_handler_idmac, intr_handler_idmac,
intr_handler_idmac, intr_handler_idmac,
intr_handler_idmac, intr_handler_idmac,
intr_handler_idmac, intr_handler_idmac,
intr_handler_skdmac0, intr_handler_idmac,
intr_handler_skdmac1, intr_handler_skdmac0,
intr_handler_skdmac1,
}; };
/**************************************************************************** /****************************************************************************
@ -306,7 +314,8 @@ static int dma_stop(int ch);
static int ch2dmac(int ch) static int ch2dmac(int ch)
{ {
switch (ch) { switch (ch)
{
case 0: case 1: case 0: case 1:
return 1; return 1;
case 2: case 3: case 4: case 5: case 6: /* APP IDMAC */ case 2: case 3: case 4: case 5: case 6: /* APP IDMAC */
@ -320,9 +329,10 @@ static int ch2dmac(int ch)
static struct dmac_register_map *get_device(int ch) static struct dmac_register_map *get_device(int ch)
{ {
int id = ch2dmac(ch); int id = ch2dmac(ch);
switch (id) { switch (id)
{
case 1: return (struct dmac_register_map *)DMAC1_REG_BASE; case 1: return (struct dmac_register_map *)DMAC1_REG_BASE;
case 2: return (struct dmac_register_map *)DMAC2_REG_BASE; case 2: return (struct dmac_register_map *)DMAC2_REG_BASE;
case 3: return (struct dmac_register_map *)DMAC3_REG_BASE; case 3: return (struct dmac_register_map *)DMAC3_REG_BASE;
@ -332,23 +342,30 @@ static struct dmac_register_map *get_device(int ch)
static struct dmac_ch_register_map *get_channel(int ch) static struct dmac_ch_register_map *get_channel(int ch)
{ {
struct dmac_register_map *dev = get_device(ch); struct dmac_register_map *dev = get_device(ch);
if (dev == NULL) if (dev == NULL)
return NULL; return NULL;
if (is_dmac(2, dev)) { if (is_dmac(2, dev))
{
return &dev->channel[ch - 7]; return &dev->channel[ch - 7];
} }
else if (is_dmac(3, dev)) { else if (is_dmac(3, dev))
{
return &((struct dmac080_register_map *)dev)->channel[ch - 2]; return &((struct dmac080_register_map *)dev)->channel[ch - 2];
} }
return &dev->channel[ch & 1]; return &dev->channel[ch & 1];
} }
/****************************************************************************
* Private Functions
****************************************************************************/
static int get_pmid(int ch) static int get_pmid(int ch)
{ {
switch (ch) { switch (ch)
{
case 0: case 1: case 0: case 1:
return PM_APP_ADMAC; return PM_APP_ADMAC;
case 2: case 3: case 4: case 5: case 6: case 2: case 3: case 4: case 5: case 6:
@ -358,301 +375,346 @@ static int get_pmid(int ch)
default: default:
break; /* may not comes here */ break; /* may not comes here */
} }
return 0;
return 0;
} }
struct dmac_ch_register_frame { struct dmac_ch_register_frame
uint32_t srcaddr; {
uint32_t destaddr; uint32_t srcaddr;
uint32_t lli; uint32_t destaddr;
uint32_t control; uint32_t lli;
uint32_t configuration; uint32_t control;
uint32_t configuration;
}; };
struct dmac_register_frame { struct dmac_register_frame
uint32_t configuration; {
struct dmac_ch_register_frame channel[2]; uint32_t configuration;
struct dmac_ch_register_frame channel[2];
}; };
static void _dmac_intc_handler(int ch) static void _dmac_intc_handler(int ch)
{ {
struct dmac_register_map *dev = get_device(ch); struct dmac_register_map *dev = get_device(ch);
struct dma_channel_s *dmach; struct dma_channel_s *dmach;
uint32_t mask; uint32_t mask;
int itc; int itc;
int err; int err;
mask = (1u << (ch & 1)); mask = (1u << (ch & 1));
if (is_dmac(2, dev)) { if (is_dmac(2, dev))
{
mask = 1u << (ch - 7); mask = 1u << (ch - 7);
} }
else if (is_dmac(3, dev)) {
else if (is_dmac(3, dev))
{
mask = 1u << (ch - 2); mask = 1u << (ch - 2);
} }
itc = dev->inttcstatus & mask; itc = dev->inttcstatus & mask;
err = dev->interrorstatus & mask; err = dev->interrorstatus & mask;
dev->inttcclear = itc; dev->inttcclear = itc;
dev->interrorclear = err; dev->interrorclear = err;
dmach = &g_dmach[ch]; dmach = &g_dmach[ch];
if (dmach->callback) { if (dmach->callback)
int flags = itc ? CXD56_DMA_INTR_ITC : 0; {
flags |= err ? CXD56_DMA_INTR_ERR : 0; int flags = itc ? CXD56_DMA_INTR_ITC : 0;
dmach->callback((DMA_HANDLE)dmach, flags, dmach->arg); flags |= err ? CXD56_DMA_INTR_ERR : 0;
dmach->callback((DMA_HANDLE)dmach, flags, dmach->arg);
} }
} }
static int intr_handler_admac0(int irq, FAR void *context, FAR void *arg) static int intr_handler_admac0(int irq, FAR void *context, FAR void *arg)
{ {
_dmac_intc_handler(0); _dmac_intc_handler(0);
return OK; return OK;
} }
static int intr_handler_admac1(int irq, FAR void *context, FAR void *arg) static int intr_handler_admac1(int irq, FAR void *context, FAR void *arg)
{ {
_dmac_intc_handler(1); _dmac_intc_handler(1);
return OK; return OK;
} }
static int intr_handler_idmac(int irq, FAR void *context, FAR void *arg) static int intr_handler_idmac(int irq, FAR void *context, FAR void *arg)
{ {
struct dmac_register_map *dev = get_device(2); /* XXX */ struct dmac_register_map *dev = get_device(2); /* XXX */
uint32_t stat = dev->intstatus & 0x1f; uint32_t stat = dev->intstatus & 0x1f;
int i; int i;
for (i = 2; stat; i++, stat >>= 1) { for (i = 2; stat; i++, stat >>= 1)
if (stat & 1) {
_dmac_intc_handler(i); if (stat & 1)
{
_dmac_intc_handler(i);
}
} }
return OK; return OK;
} }
static int intr_handler_skdmac0(int irq, FAR void *context, FAR void *arg) static int intr_handler_skdmac0(int irq, FAR void *context, FAR void *arg)
{ {
_dmac_intc_handler(7); _dmac_intc_handler(7);
return OK; return OK;
} }
static int intr_handler_skdmac1(int irq, FAR void *context, FAR void *arg) static int intr_handler_skdmac1(int irq, FAR void *context, FAR void *arg)
{ {
_dmac_intc_handler(8); _dmac_intc_handler(8);
return OK; return OK;
} }
static void controller_power_on(int ch) static void controller_power_on(int ch)
{ {
int id = get_pmid(ch); int id = get_pmid(ch);
if (id == PM_APP_SKDMAC) if (id == PM_APP_SKDMAC)
return; {
return;
}
/* TODO power on */ /* TODO power on */
} }
static void controller_power_off(int ch) static void controller_power_off(int ch)
{ {
int id = get_pmid(ch); int id = get_pmid(ch);
if (id == PM_APP_SKDMAC) /* Do not disable SKDMAC, leave it to SAKE driver. */ if (id == PM_APP_SKDMAC) /* Do not disable SKDMAC, leave it to SAKE driver. */
return; {
return;
}
/* TODO power off */ /* TODO power off */
} }
int dma_init(int ch) int dma_init(int ch)
{ {
int id = ch2dmac(ch); int id = ch2dmac(ch);
if (!id) if (!id)
return -ENODEV; {
return -ENODEV;
}
controller_power_on(ch); controller_power_on(ch);
irq_attach(irq_map[ch], intc_handler[ch], NULL); irq_attach(irq_map[ch], intc_handler[ch], NULL);
return 0; return 0;
} }
int dma_uninit(int ch) int dma_uninit(int ch)
{ {
int id = ch2dmac(ch); int id = ch2dmac(ch);
if (!id) if (!id)
return -ENODEV; {
return -ENODEV;
}
controller_power_off(ch); controller_power_off(ch);
return 0; return 0;
} }
int dma_open(int ch) int dma_open(int ch)
{ {
struct dmac_register_map *dmac = get_device(ch); struct dmac_register_map *dmac = get_device(ch);
irqstate_t flags; irqstate_t flags;
if (dmac == NULL) if (dmac == NULL)
return -ENODEV; {
return -ENODEV;
flags = enter_critical_section();
if (open_channels & (1u << ch)) {
leave_critical_section(flags);
return -EBUSY;
} }
open_channels |= 1u << ch;
leave_critical_section(flags); flags = enter_critical_section();
g_dmach[ch].callback = NULL; if (open_channels & (1u << ch))
g_dmach[ch].arg = NULL; {
leave_critical_section(flags);
return -EBUSY;
}
dmac->sync = 0; open_channels |= 1u << ch;
dmac->configuration |= 1;
return 0; leave_critical_section(flags);
g_dmach[ch].callback = NULL;
g_dmach[ch].arg = NULL;
dmac->sync = 0;
dmac->configuration |= 1;
return 0;
} }
static int dma_close(int ch) static int dma_close(int ch)
{ {
struct dmac_register_map *dmac = get_device(ch); struct dmac_register_map *dmac = get_device(ch);
uint32_t enabled; uint32_t enabled;
irqstate_t flags; irqstate_t flags;
uint32_t chmask; uint32_t chmask;
int shift; int shift;
if (dmac == NULL) if (dmac == NULL)
return -ENODEV; {
return -ENODEV;
shift = ch & 1;
if (is_dmac(2, dmac)) {
shift = ch - 7;
} }
else if (is_dmac(3, dmac)) {
shift = ch & 1;
if (is_dmac(2, dmac))
{
shift = ch - 7;
}
else if (is_dmac(3, dmac))
{
shift = ch - 2; shift = ch - 2;
} }
enabled = dmac->enbldchns; enabled = dmac->enbldchns;
if (enabled & (1 << shift)) if (enabled & (1 << shift))
return -EBUSY; {
return -EBUSY;
dma_clearintrcallback(ch);
flags = enter_critical_section();
chmask = (3u << (ch & ~1));
if (is_dmac(2, dmac)) {
chmask = 0x3u << 7;
} }
else if (is_dmac(3, dmac)) {
dma_clearintrcallback(ch);
flags = enter_critical_section();
chmask = (3u << (ch & ~1));
if (is_dmac(2, dmac))
{
chmask = 0x3u << 7;
}
else if (is_dmac(3, dmac))
{
chmask = 0x1fu << 2; chmask = 0x1fu << 2;
} }
open_channels &= ~(1u << ch); open_channels &= ~(1u << ch);
/* Stop device if both of channels are already closed */ /* Stop device if both of channels are already closed */
if (!(open_channels & chmask)) if (!(open_channels & chmask))
dmac->configuration &= ~1; {
dmac->configuration &= ~1;
}
leave_critical_section(flags); leave_critical_section(flags);
return 0; return 0;
} }
static int dma_setconfig(int ch, int itc, int ierr, int flowctrl, static int dma_setconfig(int ch, int itc, int ierr, int flowctrl,
int destperi, int srcperi) int destperi, int srcperi)
{ {
struct dmac_ch_register_map *channel = get_channel(ch); struct dmac_ch_register_map *channel = get_channel(ch);
if (channel == NULL) if (channel == NULL)
return -ENODEV; {
return -ENODEV;
}
channel->configuration = (itc & 1) << 15 | channel->configuration = (itc & 1) << 15 |
(ierr & 1) << 14 | (ierr & 1) << 14 |
(flowctrl & 7) << 11 | (flowctrl & 7) << 11 |
1 << 25 | 1 << 24 | /* Burst enable */
(destperi & 0xf) << 6 |
(srcperi & 0xf) << 1;
/* Burst enable */ return 0;
1 << 25 | 1 << 24 |
(destperi & 0xf) << 6 |
(srcperi & 0xf) << 1;
return 0;
} }
static int dma_setintrcallback(int ch, dma_callback_t func, void *data) static int dma_setintrcallback(int ch, dma_callback_t func, void *data)
{ {
if (ch >= NCHANNELS) if (ch >= NCHANNELS)
return -ENODEV; {
return -ENODEV;
}
g_dmach[ch].callback = func; g_dmach[ch].callback = func;
g_dmach[ch].arg = data; g_dmach[ch].arg = data;
up_enable_irq(irq_map[ch]); up_enable_irq(irq_map[ch]);
return 0; return 0;
} }
static int dma_clearintrcallback(int ch) static int dma_clearintrcallback(int ch)
{ {
if (ch >= NCHANNELS) if (ch >= NCHANNELS)
return -ENODEV; {
return -ENODEV;
}
g_dmach[ch].callback = NULL; g_dmach[ch].callback = NULL;
g_dmach[ch].arg = NULL; g_dmach[ch].arg = NULL;
up_disable_irq(irq_map[ch]); up_disable_irq(irq_map[ch]);
return 0; return 0;
} }
static int dma_start(int ch, dmac_lli_t *list) static int dma_start(int ch, dmac_lli_t *list)
{ {
struct dmac_ch_register_map *channel = get_channel(ch); struct dmac_ch_register_map *channel = get_channel(ch);
if (channel == NULL) if (channel == NULL)
return -ENODEV; {
return -ENODEV;
if (list) {
channel->srcaddr = list->src_addr;
channel->destaddr = list->dest_addr;
channel->lli = list->nextlli;
channel->control = list->control;
} }
channel->configuration |= DMAC_CH_ENABLE; if (list)
{
channel->srcaddr = list->src_addr;
channel->destaddr = list->dest_addr;
channel->lli = list->nextlli;
channel->control = list->control;
}
return 0; channel->configuration |= DMAC_CH_ENABLE;
return 0;
} }
static int dma_stop(int ch) static int dma_stop(int ch)
{ {
struct dmac_ch_register_map *channel = get_channel(ch); struct dmac_ch_register_map *channel = get_channel(ch);
if (channel == NULL) if (channel == NULL)
return -ENODEV; {
return -ENODEV;
}
if (!(channel->configuration & DMAC_CH_ENABLE)) if (!(channel->configuration & DMAC_CH_ENABLE))
return 0; /* already stopped */ {
return 0; /* already stopped */
}
/* Set HALT and poll Active bit for FIFO is cleaned */ /* Set HALT and poll Active bit for FIFO is cleaned */
channel->configuration |= DMAC_CH_HALT; channel->configuration |= DMAC_CH_HALT;
(void) channel->lli; (void) channel->lli;
(void) channel->lli; (void) channel->lli;
while (channel->configuration & DMAC_CH_ACTIVE); while (channel->configuration & DMAC_CH_ACTIVE);
channel->configuration &= ~(DMAC_CH_HALT | DMAC_CH_ENABLE); channel->configuration &= ~(DMAC_CH_HALT | DMAC_CH_ENABLE);
return 0; return 0;
} }
/****************************************************************************
* Public Functions
****************************************************************************/
/**************************************************************************** /****************************************************************************
* Name: cxd56_dmainitialize * Name: cxd56_dmainitialize
* *
@ -684,7 +746,8 @@ void weak_function up_dma_initialize(void)
* Name: cxd56_dmachannel * Name: cxd56_dmachannel
* *
* Description: * Description:
* Allocate a DMA channel. This function gives the caller mutually exclusive * Allocate a DMA channel.
* This function gives the caller mutually exclusive
* access to a DMA channel. * access to a DMA channel.
* *
* If no DMA channel is available, then cxd56_dmachannel() will wait until * If no DMA channel is available, then cxd56_dmachannel() will wait until
@ -718,6 +781,7 @@ DMA_HANDLE cxd56_dmachannel(int ch, ssize_t maxsize)
dmaerr("Invalid channel number %d.\n", ch); dmaerr("Invalid channel number %d.\n", ch);
goto err; goto err;
} }
dmach = &g_dmach[ch]; dmach = &g_dmach[ch];
if (maxsize == 0) if (maxsize == 0)

9
arch/arm/src/cxd56xx/cxd56_dmac.h
View File

@ -37,6 +37,10 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H #ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H #define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h> #include <stdint.h>
#include "cxd56_dmac_common.h" #include "cxd56_dmac_common.h"
@ -185,8 +189,9 @@ void cxd56_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg);
* Name: cxd56_dmastop * Name: cxd56_dmastop
* *
* Description: * Description:
* Cancel the DMA. After cxd56_dmastop() is called, the DMA channel is reset * Cancel the DMA.
* and cxd56_dmasetup() must be called before cxd56_dmastart() can be called * After cxd56_dmastop() is called, the DMA channel is reset and
* cxd56_dmasetup() must be called before cxd56_dmastart() can be called
* again * again
* *
* Assumptions: * Assumptions:

11
arch/arm/src/cxd56xx/cxd56_dmac_common.h
View File

@ -38,14 +38,18 @@
#ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H #ifndef __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H
#define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H #define __ARCH_ARM_SRC_CXD56XX_CXD56_DMAC_COMMON_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <stdint.h> #include <stdint.h>
/**************************************************************************** /****************************************************************************
* Public Types * Public Types
****************************************************************************/ ****************************************************************************/
/* DMA_HANDLE provides an opaque are reference that can be used to represent a /* DMA_HANDLE provides an opaque are reference that can be used to represent
* DMA channel. * a DMA channel.
*/ */
typedef FAR void *DMA_HANDLE; typedef FAR void *DMA_HANDLE;
@ -70,7 +74,8 @@ typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
* this should be changed to a uint32_t. * this should be changed to a uint32_t.
*/ */
typedef struct { typedef struct
{
uint16_t channel_cfg; uint16_t channel_cfg;
uint8_t dest_width; uint8_t dest_width;
uint8_t src_width; uint8_t src_width;