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arch/arm/src/stm32f7/stm32_flash.c: Allow programming OTP blocks through progmem interface

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This commit is contained in:
Jussi Kivilinna 2018-10-22 06:17:18 -06:00 committed by Gregory Nutt
parent 4b0327d845
commit 06c6b0ce1b
4 changed files with 22 additions and 9 deletions
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4
arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h
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@ -77,7 +77,7 @@
#define STM32_FLASH_ITCM 0x00200000 /* 0x00200000-0x002fffff: FLASH memory (ITCM) */
#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x080fffff: FLASH memory (AXIM) */
#define STM32_FLASH_BASE STM32_FLASH_AXIM
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: Option bytes (AXIM) */
/* Information Addresses ************************************************************/
@ -85,6 +85,8 @@
#define STM32_SYSMEM_UID 0x1ff07A10 /* The 96-bit unique device identifier */
#define STM32_OTP_ICTM 0x00107800 /* 0x00107800-0x00107A0F: OTP (ITCM) */
#define STM32_OTP_AXIM 0x1ff07800 /* 0x1ff07800-0x1ff07A0F: OTP (AXIM) */
#define STM32_OPT_BASE STM32_OTP_AXIM
#define STM32_OPT_SIZE 1056
/* SRAM Base Addresses **************************************************************/

5
arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h
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@ -77,15 +77,16 @@
#define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */
#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x080fffff: FLASH memory (AXIM) */
#define STM32_FLASH_BASE STM32_FLASH_AXIM
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: Option bytes (AXIM) */
/* Information Addresses ************************************************************/
#define STM32_SYSMEM_AXIM 0x1ff00000 /* 0x1ff00000-0x1ff0edbf: System memory (AXIM) */
#define STM32_SYSMEM_UID 0x1ff0f420 /* The 96-bit unique device identifier */
#define STM32_OTP_ICTM 0x0010f000 /* 0x0010f000-0x0010edbf: OTP (ITCM) */
#define STM32_OTP_AXIM 0x1ff0f000 /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */
#define STM32_OPT_BASE STM32_OTP_AXIM
#define STM32_OPT_SIZE 1056
/* SRAM Base Addresses **************************************************************/

4
arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h
View File

@ -77,7 +77,7 @@
#define STM32_LOADER_BASE 0x01000000 /* 0x01000000- Bootloader */
#define STM32_FLASH_AXIM 0x08000000 /* 0x08000000-0x081fffff: FLASH memory (AXIM) */
#define STM32_FLASH_BASE STM32_FLASH_AXIM
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: OTP (AXIM) */
#define STM32_OPTIONS_BASE 0x1fff0000 /* 0x1ff00000-0x1fff001f: Option bytes (AXIM) */
/* Information Addresses ************************************************************/
@ -86,6 +86,8 @@
#define STM32_SYSMEM_UID 0x1ff0f420 /* The 96-bit unique device identifier */
#define STM32_OTP_ICTM 0x0010f000 /* 0x0010f000-0x0010edbf: OTP (ITCM) */
#define STM32_OTP_AXIM 0x1ff0f000 /* 0x1ff00000-0x1ff0f41f: OTP (AXIM) */
#define STM32_OPT_BASE STM32_OTP_AXIM
#define STM32_OPT_SIZE 1056
/* SRAM Base Addresses **************************************************************/

18
arch/arm/src/stm32f7/stm32_flash.c
View File

@ -360,19 +360,27 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
{
uint8_t *byte = (uint8_t *)buf;
size_t written = count;
uintptr_t flash_base;
/* Check for valid address range */
if (addr >= STM32_FLASH_BASE)
if (addr >= STM32_FLASH_BASE &&
addr + count <= STM32_FLASH_BASE + STM32_FLASH_SIZE)
{
addr -= STM32_FLASH_BASE;
flash_base = STM32_FLASH_BASE;
}
if ((addr+count) > STM32_FLASH_SIZE)
else if (addr >= STM32_OPT_BASE &&
addr + count <= STM32_OPT_BASE + STM32_OPT_SIZE)
{
flash_base = STM32_OPT_BASE;
}
else
{
return -EFAULT;
}
addr -= flash_base;
sem_lock();
/* Get flash ready and begin flashing */
@ -385,7 +393,7 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
modifyreg32(STM32_FLASH_CR, FLASH_CR_PSIZE_MASK, FLASH_CR_PSIZE_X8);
for (addr += STM32_FLASH_BASE; count; count -= 1, byte++, addr += 1)
for (addr += flash_base; count; count -= 1, byte++, addr += 1)
{
/* Write half-word and wait to complete */