diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h index 9d0712b276..f24bf5b7e2 100644 --- a/arch/arm/include/stm32l4/chip.h +++ b/arch/arm/include/stm32l4/chip.h @@ -45,7 +45,12 @@ /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ -/* STM32F476, STM32F486. Differences between family members: 486 has AES. +/* STM32L476, STM32L486, STM32L496, STM32L4A6 + * + * Differences between family members: + * - L486 has AES + * - L496, L4A6 has 320 Kib SRAM, 2xCAN and CameraIF. Most (all?) of these have I2C4. + * - L4A6 has AES and HASH * * ----------- ---------------- ----- ------ ------ ---- ---- ----- * PART PACKAGE GPIOs LCD Tamper FSMC CapS AdcCh @@ -56,6 +61,7 @@ * STM32L4x6Rx LQFP64 51 8x28 2 No 12 16 * STM32L4x6Vx LQFP100 82 8x40 3 Yes 21 16 * STM32L4x6Zx LQFP144 114 8x40 3 Yes 24 24 + * STM32L4x6Ax UFBGA169 132 8x40 3 Yes 24 24 * ----------- ---------------- ----- ------ ------ ---- ---- ----- * * Parts STM32L4x6xC have 256Kb of FLASH @@ -66,8 +72,13 @@ * selection. */ +#if defined(CONFIG_STM32L4_STM32L496XX) +# define STM32L4_SRAM1_SIZE (256*1024) /* 256Kb SRAM1 on AHB bus Matrix */ +# define STM32L4_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */ +#else # define STM32L4_SRAM1_SIZE (96*1024) /* 96Kb SRAM1 on AHB bus Matrix */ # define STM32L4_SRAM2_SIZE (32*1024) /* 32Kb SRAM2 on AHB bus Matrix */ +#endif # define STM32L4_NFSMC 1 /* Have FSMC memory controller */ # define STM32L4_NATIM 2 /* Two advanced timers TIM1 and 8 */ @@ -81,14 +92,22 @@ # define STM32L4_NUSART 3 /* USART 1-3 */ # define STM32L4_NLPUART 1 /* LPUART 1 */ # define STM32L4_NSPI 3 /* SPI1-3 */ +#if defined(CONFIG_STM32L4_STM32L496XX) +# define STM32L4_NI2C 4 /* I2C1-4 */ +#else # define STM32L4_NI2C 3 /* I2C1-3 */ +#endif # define STM32L4_NUSBOTGFS 1 /* USB OTG FS */ +#if defined(CONFIG_STM32L4_STM32L496XX) +# define STM32L4_NCAN 2 /* CAN1-2 */ +#else # define STM32L4_NCAN 1 /* CAN1 */ +#endif # define STM32L4_NSAI 2 /* SAI1-2 */ # define STM32L4_NSDMMC 1 /* SDMMC interface */ # define STM32L4_NDMA 2 /* DMA1-2 */ # define STM32L4_NPORTS 8 /* 8 GPIO ports, GPIOA-H */ -# define STM32L4_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */ +# define STM32L4_NADC 3 /* 12-bit ADC1-3, 24 channels (except V series) */ # define STM32L4_NDAC 2 /* 12-bit DAC1-2 */ # define STM32L4_NCRC 1 /* CRC */ # define STM32L4_NCOMP 2 /* Comparators */ diff --git a/arch/arm/include/stm32l4/irq.h b/arch/arm/include/stm32l4/irq.h index 89e74c1760..abb543bc72 100644 --- a/arch/arm/include/stm32l4/irq.h +++ b/arch/arm/include/stm32l4/irq.h @@ -76,7 +76,8 @@ #define STM32L4_IRQ_FIRST (16) /* Vector number of the first external interrupt */ -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) # include #else # error "Unsupported STM32 L4 chip" diff --git a/arch/arm/src/stm32l4/Kconfig b/arch/arm/src/stm32l4/Kconfig index 68d6ee6806..0a8dceb0fc 100644 --- a/arch/arm/src/stm32l4/Kconfig +++ b/arch/arm/src/stm32l4/Kconfig @@ -24,7 +24,7 @@ config ARCH_CHIP_STM32L476RE select STM32L4_STM32L476XX select STM32L4_FLASH_512KB ---help--- - STM32 L4 Cortex M4, 512 FLASH, 96+32 Kb SRAM + STM32 L4 Cortex M4, 512Kb FLASH, 96+32 Kb SRAM config ARCH_CHIP_STM32L486 bool "STM32L486xx" @@ -33,6 +33,29 @@ config ARCH_CHIP_STM32L486 ---help--- STM32 L4 Cortex M4, AES, 1024Kb FLASH, 96+32 Kb SRAM +config ARCH_CHIP_STM32L496ZE + bool "STM32L496ZE" + select STM32L4_STM32L496XX + select STM32L4_FLASH_512KB + ---help--- + STM32 L4 Cortex M4, 512Kb FLASH, 320 Kb SRAM + +config ARCH_CHIP_STM32L496ZG + bool "STM32L496ZG" + select STM32L4_STM32L496XX + select STM32L4_FLASH_1024KB + ---help--- + STM32 L4 Cortex M4, 1024Kb FLASH, 320 Kb SRAM + +config ARCH_CHIP_STM32L4A6 + bool "STM32L4A6xx" + select STM32L4_STM32L496XX # Close enough to L496 + select STM32L4_FLASH_1024KB + select STM32L4_HAVE_AES + select STM32L4_HAVE_HASH + ---help--- + STM32 L4 Cortex M4, AES, HASH, 1024Kb FLASH, 320 Kb SRAM + endchoice # STM32 L4 Chip Selection # Chip families @@ -82,12 +105,25 @@ config STM32L4_STM32L486XX select ARMV7M_HAVE_DTCM select STM32L4_FLASH_1024KB +config STM32L4_STM32L496XX + bool + default n + select STM32L4_STM32L4X6 + select ARCH_HAVE_FPU + select ARCH_HAVE_DPFPU # REVISIT + select ARMV7M_HAVE_ITCM + select ARMV7M_HAVE_DTCM + select STM32L4_HAVE_I2C4 + select STM32L4_HAVE_CAN2 + select STM32L4_HAVE_DCMI + choice prompt "Embedded FLASH size" default STM32L4_FLASH_1024KB config STM32L4_FLASH_256KB bool "256 KB" + depends on !STM32L4_STM32L496XX config STM32L4_FLASH_512KB bool "512 KB" @@ -132,6 +168,30 @@ menu "STM32L4 Peripheral Support" # These "hidden" settings determine is a peripheral option is available for the # selection MCU +config STM32L4_HAVE_AES + bool + default n + +config STM32L4_HAVE_CAN2 + bool + default n + +config STM32L4_HAVE_COMP + bool + default n + +config STM32L4_HAVE_DCMI + bool + default n + +config STM32L4_HAVE_HASH + bool + default n + +config STM32L4_HAVE_I2C4 + bool + default n + config STM32L4_HAVE_LTDC bool default n @@ -144,10 +204,6 @@ config STM32L4_HAVE_LPTIM2 bool default n -config STM32L4_HAVE_COMP - bool - default n - config STM32L4_HAVE_SAI1 bool default n @@ -244,6 +300,17 @@ config STM32L4_ADC3 config STM32L4_AES bool "AES" default n + depends on STM32L4_HAVE_AES + +config STM32L4_DCMI + bool "DCMI" + default n + depends on STM32L4_HAVE_DCMI + +config STM32L4_HASH + bool "HASH" + default n + depends on STM32L4_HAVE_HASH config STM32L4_RNG bool "RNG" @@ -534,12 +601,25 @@ config STM32L4_I2C3 default n select STM32L4_I2C +config STM32L4_I2C4 + bool "I2C4" + default n + select STM32L4_I2C + depends on STM32L4_HAVE_I2C4 + config STM32L4_CAN1 bool "CAN1" default n select CAN select STM32L4_CAN +config STM32L4_CAN2 + bool "CAN2" + default n + select CAN + select STM32L4_CAN + depends on STM32L4_HAVE_CAN2 + config STM32L4_DAC1 bool "DAC1" default n @@ -2865,7 +2945,7 @@ config STM32L4_I2C_DUTY16_9 endmenu menu "CAN driver configuration" - depends on STM32L4_CAN1 + depends on STM32L4_CAN1 || STM32L4_CAN2 config CAN1_BAUD int "CAN1 BAUD" @@ -2874,6 +2954,13 @@ config CAN1_BAUD ---help--- CAN1 BAUD rate. Required if CONFIG_STM32L4_CAN1 is defined. +config CAN2_BAUD + int "CAN2 BAUD" + default 250000 + depends on STM32L4_CAN2 + ---help--- + CAN2 BAUD rate. Required if CONFIG_STM32L4_CAN2 is defined. + config CAN_TSEG1 int "TSEG1 quanta" default 6 diff --git a/arch/arm/src/stm32l4/README.txt b/arch/arm/src/stm32l4/README.txt index 4e1d31f6aa..6b570ededd 100644 --- a/arch/arm/src/stm32l4/README.txt +++ b/arch/arm/src/stm32l4/README.txt @@ -27,7 +27,7 @@ DMA : works; at least tested with QSPI SRAM2 : OK; can be included in MM region or left separate for special app purposes FIREWALL : Code written, to be tested, requires support from ldscript SPI : Code written, to be tested, including DMA -I2C : Registers defined +I2C : Code written, to be tested (I2C4 missing) RTC : works QSPI : works in polling, interrupt, DMA, and also memory-mapped modes CAN : TODO @@ -58,4 +58,5 @@ DFSDM : TODO (Digital Filter and Sigma-Delta Modulator) LCD : TODO (Segment LCD controller) SAIPLL : works (PLL For Digital Audio interfaces, and other things) SAI : TODO (Digital Audio interfaces, I2S, SPDIF, etc) - +HASH : TODO (SHA-1, SHA-224, SHA-256, HMAC) +DCMI : TODO (Digital Camera interfaces) diff --git a/arch/arm/src/stm32l4/chip.h b/arch/arm/src/stm32l4/chip.h index b4caa13eac..99677fcfc7 100644 --- a/arch/arm/src/stm32l4/chip.h +++ b/arch/arm/src/stm32l4/chip.h @@ -53,13 +53,13 @@ /* If the common ARMv7-M vector handling logic is used, then it expects the * following definition in this file that provides the number of supported external - * interrupts which, for this architecture, is provided in the arch/stm32f7/chip.h + * interrupts which, for this architecture, is provided in the arch/stm32l4/chip.h * header file. */ #define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS -/* Cache line sizes (in bytes)for the STM32L4 */ +/* Cache line sizes (in bytes) for the STM32L4 */ #define ARMV7M_DCACHE_LINESIZE 0 /* no cache */ #define ARMV7M_ICACHE_LINESIZE 0 /* no cache */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_i2c.h b/arch/arm/src/stm32l4/chip/stm32l4_i2c.h index 02927801fd..a28dad8728 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_i2c.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_i2c.h @@ -98,6 +98,20 @@ # define STM32L4_I2C3_TXDR (STM32L4_I2C3_BASE+STM32L4_I2C_TXDR_OFFSET) #endif +#if STM32L4_NI2C > 3 +# define STM32L4_I2C4_CR1 (STM32L4_I2C4_BASE+STM32L4_I2C_CR1_OFFSET) +# define STM32L4_I2C4_CR2 (STM32L4_I2C4_BASE+STM32L4_I2C_CR2_OFFSET) +# define STM32L4_I2C4_OAR1 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR1_OFFSET) +# define STM32L4_I2C4_OAR2 (STM32L4_I2C4_BASE+STM32L4_I2C_OAR2_OFFSET) +# define STM32L4_I2C4_TIMINGR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMINGR_OFFSET) +# define STM32L4_I2C4_TIMEOUTR (STM32L4_I2C4_BASE+STM32L4_I2C_TIMEOUTR_OFFSET) +# define STM32L4_I2C4_ISR (STM32L4_I2C4_BASE+STM32L4_I2C_ISR_OFFSET) +# define STM32L4_I2C4_ICR (STM32L4_I2C4_BASE+STM32L4_I2C_ICR_OFFSET) +# define STM32L4_I2C4_PECR (STM32L4_I2C4_BASE+STM32L4_I2C_PECR_OFFSET) +# define STM32L4_I2C4_RXDR (STM32L4_I2C4_BASE+STM32L4_I2C_RXDR_OFFSET) +# define STM32L4_I2C4_TXDR (STM32L4_I2C4_BASE+STM32L4_I2C_TXDR_OFFSET) +#endif + /* Register Bitfield Definitions ****************************************************/ /* Control register 1 */ diff --git a/arch/arm/src/stm32l4/chip/stm32l4_memorymap.h b/arch/arm/src/stm32l4/chip/stm32l4_memorymap.h index 99271a7a52..33a9b5bd56 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_memorymap.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_memorymap.h @@ -43,7 +43,7 @@ /* STM32F40XXX Address Blocks *******************************************************/ #define STM32L4_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ -#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (96k) */ +#define STM32L4_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block (96k or 256k) */ #define STM32L4_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */ #define STM32L4_FSMC_BASE12 0x60000000 /* 0x60000000-0x7fffffff: 512Mb FSMC bank1&2 block */ # define STM32L4_FSMC_BANK1 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */ @@ -53,7 +53,7 @@ # define STM32L4_QSPI_BANK 0x90000000 /* 0x90000000-0x9fffffff: 256Mb QUADSPI*/ #define STM32L4_FSMC_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: FSMC register block */ #define STM32L4_QSPI_BASE 0xa0001000 /* 0xa0000000-0xbfffffff: QSPI register block */ - /* 0xc0000000-0xdfffffff: 512Mb (not used) */ + /* 0xc0000000-0xdfffffff: 512Mb (not used) */ #define STM32L4_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */ #define STM32L4_REGION_MASK 0xf0000000 @@ -63,31 +63,33 @@ /* Code Base Addresses **************************************************************/ #define STM32L4_BOOT_BASE 0x00000000 /* 0x00000000-0x000fffff: Aliased boot memory */ - /* 0x00100000-0x07ffffff: Reserved */ + /* 0x00100000-0x07ffffff: Reserved */ #define STM32L4_FLASH_BASE 0x08000000 /* 0x08000000-0x080fffff: FLASH memory */ - /* 0x08100000-0x0fffffff: Reserved */ -#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 32Kb SRAM2 */ - /* 0x10010000-0x1ffeffff: Reserved */ + /* 0x08100000-0x0fffffff: Reserved */ +#define STM32L4_SRAM2_BASE 0x10000000 /* 0x10000000-0x1000ffff: 32Kb or 64Kb SRAM2 */ + /* 0x10010000-0x1ffeffff: Reserved */ #define STM32L4_SYSMEM_BASE 0x1fff0000 /* 0x1fff0000-0x1fff7a0f: System memory */ - /* 0x1fff7a10-0x1fff7fff: Reserved */ + /* 0x1fff7a10-0x1fff7fff: Reserved */ #define STM32L4_OPTION_BASE 0x1fffc000 /* 0x1fffc000-0x1fffc007: Option bytes */ - /* 0x1fffc008-0x1fffffff: Reserved */ + /* 0x1fffc008-0x1fffffff: Reserved */ /* System Memory Addresses **********************************************************/ #define STM32L4_SYSMEM_UID 0x1fff7590 /* The 96-bit unique device identifier */ #define STM32L4_SYSMEM_FSIZE 0x1fff75E0 /* This bitfield indicates the size of - * the device Flash memory expressed in - * Kbytes. Example: 0x0400 corresponds - * to 1024 Kbytes. - */ + * the device Flash memory expressed in + * Kbytes. Example: 0x0400 corresponds + * to 1024 Kbytes. + */ #define STM32L4_SYSMEM_PACKAGE 0x1fff7500 /* This bitfield indicates the package - * type. - * 0: LQFP64 - * 2: LQFP100 - * 3: BGA132 - * 4: LQFP144, WLCSP81 or WLCSP72 - */ + * type. + * 0: LQFP64 + * 2: LQFP100 + * 3: UFBGA132 + * 4: LQFP144, WLCSP81 or WLCSP72 + * 16: UFBGA169 + * 17: WLCSP100 + */ /* SRAM Base Addresses **************************************************************/ @@ -116,11 +118,13 @@ #define STM32L4_LPTIM2_BASE 0x40009400 #define STM32L4_SWPMI1_BASE 0x40008800 +#define STM32L4_I2C4_BASE 0x40008400 #define STM32L4_LPUART1_BASE 0x40008000 #define STM32L4_LPTIM1_BASE 0x40007c00 #define STM32L4_OPAMP_BASE 0x40007800 #define STM32L4_DAC_BASE 0x40007400 #define STM32L4_PWR_BASE 0x40007000 +#define STM32L4_CAN2_BASE 0x40006800 #define STM32L4_CAN1_BASE 0x40006400 #define STM32L4_I2C3_BASE 0x40005c00 #define STM32L4_I2C2_BASE 0x40005800 @@ -163,6 +167,7 @@ /* AHB1 Base Addresses **************************************************************/ +#define STM32L4_DMA2D_BASE 0x4002b000 #define STM32L4_TSC_BASE 0x40024000 #define STM32L4_CRC_BASE 0x40023000 #define STM32L4_FLASHIF_BASE 0x40022000 @@ -173,10 +178,13 @@ /* AHB2 Base Addresses **************************************************************/ #define STM32L4_RNG_BASE 0x50060800 +#define STM32L4_HASH_BASE 0x50060400 #define STM32L4_AES_BASE 0x50060000 +#define STM32L4_DCMI_BASE 0x50050000 #define STM32L4_ADC_BASE 0x50040000 #define STM32L4_OTGFS_BASE 0x50000000 -#define STM32L4_GPIOH_BASE 0x50001c00 +#define STM32L4_GPIOI_BASE 0x48002000 +#define STM32L4_GPIOH_BASE 0x48001c00 #define STM32L4_GPIOG_BASE 0x48001800 #define STM32L4_GPIOF_BASE 0x48001400 #define STM32L4_GPIOE_BASE 0x48001000 diff --git a/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h b/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h index 0b2b537f1e..28257e1738 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_pinmap.h @@ -43,7 +43,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) # include "chip/stm32l4x6xx_pinmap.h" #else # error "Unsupported STM32 L4 pin map" diff --git a/arch/arm/src/stm32l4/chip/stm32l4_syscfg.h b/arch/arm/src/stm32l4/chip/stm32l4_syscfg.h index 2e34974769..c1ad478751 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_syscfg.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_syscfg.h @@ -43,7 +43,8 @@ #include #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) /**************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h index c45c199e9b..2aef6f17d5 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h +++ b/arch/arm/src/stm32l4/chip/stm32l4x6xx_rcc.h @@ -44,7 +44,8 @@ #include -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) /**************************************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/stm32l4/stm32l4_allocateheap.c b/arch/arm/src/stm32l4/stm32l4_allocateheap.c index dc39c59e51..d0134de97f 100644 --- a/arch/arm/src/stm32l4/stm32l4_allocateheap.c +++ b/arch/arm/src/stm32l4/stm32l4_allocateheap.c @@ -64,16 +64,17 @@ * following definitions must be provided to specify the size and * location of internal (system) SRAM1 and SRAM2: * - * SRAM1_END 0x20018000 + * SRAM1_START 0x20000000 + * SRAM1_END * SRAM2_START 0x10000000 - * SRAM2_END 0x10008000 + * SRAM2_END * * In addition to internal SRAM, memory may also be available through the FSMC. * In order to use FSMC SRAM, the following additional things need to be * present in the NuttX configuration file: * - * CONFIG_STM32L4_FSMC=y : Enables the FSMC - * CONFIG_STM32L4_FSMC_SRAM=y : Indicates that SRAM is available via the + * CONFIG_STM32L4_FSMC=y : Enables the FSMC + * CONFIG_STM32L4_FSMC_SRAM=y : Indicates that SRAM is available via the * FSMC (as opposed to an LCD or FLASH). * CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC * address space @@ -87,22 +88,28 @@ # undef CONFIG_STM32L4_FSMC_SRAM #endif -/* STM32L4x6xx have 128Kib in two banks, both accessible to DMA: +/* STM32L4[7,8]6xx have 128 Kib in two banks, both accessible to DMA: * - * 1) 96KiB of System SRAM beginning at address 0x2000:0000 - 0x2001:8000 - * 2) 32KiB of System SRAM beginning at address 0x1000:0000 - 0x1000:8000 + * 1) 96 KiB of System SRAM beginning at address 0x2000:0000 - 0x2001:8000 + * 2) 32 KiB of System SRAM beginning at address 0x1000:0000 - 0x1000:8000 + * + * STM32L496xx have 320 Kib in two banks, both accessible to DMA: + * + * 1) 256 KiB of System SRAM beginning at address 0x2000:0000 - 0x2004:0000 + * 2) 64 KiB of System SRAM beginning at address 0x1000:0000 - 0x1001:0000 * * In addition, external FSMC SRAM may be available. */ -/* Set the end of system SRAM */ +/* Set the range of system SRAM */ -#define SRAM1_END 0x20018000 +#define SRAM1_START STM32L4_SRAM_BASE +#define SRAM1_END (SRAM1_START + STM32L4_SRAM1_SIZE) /* Set the range of SRAM2 as well, requires a second memory region */ -#define SRAM2_START 0x10000000 -#define SRAM2_END 0x10008000 +#define SRAM2_START STM32L4_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) #if defined(CONFIG_STM32L4_SRAM2_HEAP) && defined(CONFIG_STM32L4_FSMC_SRAM_HEAP) # if CONFIG_MM_REGIONS < 3 diff --git a/arch/arm/src/stm32l4/stm32l4_dma.c b/arch/arm/src/stm32l4/stm32l4_dma.c index c1b25e64de..d2fd26546e 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.c +++ b/arch/arm/src/stm32l4/stm32l4_dma.c @@ -67,7 +67,8 @@ * chip.h that can associate an STM32 part number with an STM32 family. */ -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) #include "stm32l4x6xx_dma.c" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_dma.h b/arch/arm/src/stm32l4/stm32l4_dma.h index c5ccf60b29..89196cb381 100644 --- a/arch/arm/src/stm32l4/stm32l4_dma.h +++ b/arch/arm/src/stm32l4/stm32l4_dma.h @@ -49,7 +49,8 @@ /* Include the correct DMA register definitions for this STM32 family */ -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) # include "chip/stm32l4x6xx_dma.h" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_firewall.h b/arch/arm/src/stm32l4/stm32l4_firewall.h index 989e7e3c30..ec667fe5a7 100644 --- a/arch/arm/src/stm32l4/stm32l4_firewall.h +++ b/arch/arm/src/stm32l4/stm32l4_firewall.h @@ -47,7 +47,8 @@ /* Include the correct firewall register definitions for this STM32L4 family */ -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) # include "chip/stm32l4x6xx_firewall.h" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.c b/arch/arm/src/stm32l4/stm32l4_gpio.c index 0c3432d6e4..007c3b8514 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.c +++ b/arch/arm/src/stm32l4/stm32l4_gpio.c @@ -55,9 +55,7 @@ #include "chip.h" #include "stm32l4_gpio.h" -#if defined(CONFIG_STM32L4_STM32L478XX) || defined(CONFIG_STM32L4_STM32L486XX) -# include "chip/stm32l4_syscfg.h" -#endif +#include "chip/stm32l4_syscfg.h" /**************************************************************************** * Public Data diff --git a/arch/arm/src/stm32l4/stm32l4_gpio.h b/arch/arm/src/stm32l4/stm32l4_gpio.h index 5d4f74d58d..f4175d817e 100644 --- a/arch/arm/src/stm32l4/stm32l4_gpio.h +++ b/arch/arm/src/stm32l4/stm32l4_gpio.h @@ -54,7 +54,8 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) # include "chip/stm32l4x6xx_gpio.h" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.c b/arch/arm/src/stm32l4/stm32l4_rcc.c index 73abae16c5..6d7a240d89 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4_rcc.c @@ -78,7 +78,8 @@ /* Include chip-specific clocking initialization logic */ -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) # include "stm32l4x6xx_rcc.c" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_rcc.h b/arch/arm/src/stm32l4/stm32l4_rcc.h index 3dae842de8..33549648c2 100644 --- a/arch/arm/src/stm32l4/stm32l4_rcc.h +++ b/arch/arm/src/stm32l4/stm32l4_rcc.h @@ -45,7 +45,8 @@ #include "up_arch.h" #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) # include "chip/stm32l4x6xx_rcc.h" #else # error "Unsupported STM32L4 chip" diff --git a/arch/arm/src/stm32l4/stm32l4_start.c b/arch/arm/src/stm32l4/stm32l4_start.c index 1c391851b4..916985cccf 100644 --- a/arch/arm/src/stm32l4/stm32l4_start.c +++ b/arch/arm/src/stm32l4/stm32l4_start.c @@ -68,7 +68,6 @@ * Mapped as boot memory address 0x0000:0000 at reset. * 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH). * 0x1000:0000 - Start of internal SRAM2 - * 0x1000:7fff - End of internal SRAM2 * 0x2000:0000 - Start of internal SRAM and start of .data (_sdata) * - End of .data (_edata) and start of .bss (_sbss) * - End of .bss (_ebss) and bottom of idle stack @@ -76,11 +75,11 @@ * start of heap. NOTE that the ARM uses a decrement before * store stack so that the correct initial value is the end of * the stack + 4; - * 0x2001:7fff - End of internal SRAM and end of heap */ -#define SRAM2_START 0x10000000 -#define SRAM2_END 0x10008000 +#define SRAM2_START STM32L4_SRAM2_BASE +#define SRAM2_END (SRAM2_START + STM32L4_SRAM2_SIZE) + #define IDLE_STACK ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4) #define HEAP_BASE ((uintptr_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE) diff --git a/arch/arm/src/stm32l4/stm32l4_uart.h b/arch/arm/src/stm32l4/stm32l4_uart.h index e66302d8e4..d6922269fb 100644 --- a/arch/arm/src/stm32l4/stm32l4_uart.h +++ b/arch/arm/src/stm32l4/stm32l4_uart.h @@ -44,7 +44,8 @@ #include "chip.h" -#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) +#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX) || \ + defined(CONFIG_STM32L4_STM32L496XX) # include "chip/stm32l4x6xx_uart.h" #else # error "Unsupported STM32L4 chip"