A10 PIO register definition header file
This commit is contained in:
Gregory Nutt
parent
b7abc8c0fe
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@ -6192,5 +6192,7 @@
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* include/nuttx/fs/smart.h: Move smart.h to include/fs/smart.h
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(2013-12-10).
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* include/nuttx/fs/ramdisk.h: Move ramdisk.h to include/fs/ramdisk.h
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(2013012-10).
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(2013-12-10).
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* arch/arm/src/a1x/chip/a1x_pio.h and a10_piocfg.h: PIO register
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defintion header files (2013-12-10).
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1297
arch/arm/src/a1x/chip/a10_piocfg.h
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1297
arch/arm/src/a1x/chip/a10_piocfg.h
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File diff suppressed because it is too large
Load Diff
228
arch/arm/src/a1x/chip/a1x_pio.h
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228
arch/arm/src/a1x/chip/a1x_pio.h
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/************************************************************************************
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* arch/arm/src/a1x/chip/a1x_pio.h
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H
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#define __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/a1x_memorymap.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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#define PIO_PORTA 0
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#define PIO_PORTB 1
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#define PIO_PORTC 2
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#define PIO_PORTD 3
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#define PIO_PORTE 4
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#define PIO_PORTF 5
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#define PIO_PORTG 6
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#define PIO_PORTH 7
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#define PIO_PORTI 8
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#define PIO_PORTS 9
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#define PIO_CFG_INPUT 0
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#define PIO_CFG_OUTPUT 1
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#define PIO_DRV_LEVEL0 0
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#define PIO_DRV_LEVEL1 1
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#define PIO_DRV_LEVEL2 2
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#define PIO_DRV_LEVEL3 3
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#define PIO_PULL_NONE 0
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#define PIO_PULL_UP 1
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#define PIO_PULL_DOWN 2
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#define PIO_INT_POSEDGE 0
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#define PIO_INT_NEGEDGE 1
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#define PIO_INT_HILEVEL 2
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#define PIO_INT_LOWLEVEL 3
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#define PIO_INT_BOTHEDGES 4
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/* Register offsets *****************************************************************/
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#define A1X_PIO_CFG0_OFFSET(n) (0x0000 + (n)*0x24) /* Port Configure Register 0, n=0-9 */
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#define A1X_PIO_CFG1_OFFSET(n) (0x0004 + (n)*0x24) /* Port Configure Register 1, n=0-9 */
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#define A1X_PIO_CFG2_OFFSET(n) (0x0008 + (n)*0x24) /* Port Configure Register 2, n=0-9 */
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#define A1X_PIO_CFG3_OFFSET(n) (0x000c + (n)*0x24) /* Port Configure Register 3, n=0-9 */
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#define A1X_PIO_DAT_OFFSET(n) (0x0010 + (n)*0x24) /* Port Data Register, n=0-9 */
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#define A1X_PIO_DRV0_OFFSET(n) (0x0014 + (n)*0x24) /* Port Multi-Driving Register 0, n=0-9 */
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#define A1X_PIO_DRV1_OFFSET(n) (0x0018 + (n)*0x24) /* Port Multi-Driving Register 1, n=0-9 */
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#define A1X_PIO_PUL0_OFFSET(n) (0x001c + (n)*0x24) /* Port Pull Register 0, n=0-9 */
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#define A1X_PIO_PUL1_OFFSET(n) (0x0020 + (n)*0x24) /* Port Pull Register 1, n=0-9 */
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#define A1X_PIO_INT_CFG0_OFFSET 0x0200 /* PIO Interrupt Configure Register 0 */
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#define A1X_PIO_INT_CFG1_OFFSET 0x0204 /* PIO Interrupt Configure Register 1 */
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#define A1X_PIO_INT_CFG2_OFFSET 0x0208 /* PIO Interrupt Configure Register 2 */
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#define A1X_PIO_INT_CFG3_OFFSET 0x020c /* PIO Interrupt Configure Register 3 */
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#define A1X_PIO_INT_CTL_OFFSET 0x0210 /* PIO Interrupt Control Register */
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#define A1X_PIO_INT_STA_OFFSET 0x0214 /* PIO Interrupt Status Register */
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#define A1X_PIO_INT_DEB_OFFSET 0x0218 /* PIO Interrupt Debounce Register */
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#define A1X_SDR_PAD_DRV_OFFSET 0x0220 /* SDRAM Pad Multi-Driving Register */
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#define A1X_SDR_PAD_PUL_OFFSET 0x0224 /* SDRAM Pad Pull Register */
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/* Register virtual addresses *******************************************************/
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#define A1X_PIO_CFG0(n) (A1X_PIO_VADDR+A1X_PIO_CFG0_OFFSET(n))
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#define A1X_PIO_CFG1(n) (A1X_PIO_VADDR+A1X_PIO_CFG1_OFFSET(n))
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#define A1X_PIO_CFG2(n) (A1X_PIO_VADDR+A1X_PIO_CFG2_OFFSET(n))
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#define A1X_PIO_CFG3(n) (A1X_PIO_VADDR+A1X_PIO_CFG3_OFFSET(n))
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#define A1X_PIO_DAT(n) (A1X_PIO_VADDR+A1X_PIO_DAT_OFFSET(n))
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#define A1X_PIO_DRV0(n) (A1X_PIO_VADDR+A1X_PIO_DRV0_OFFSET(n))
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#define A1X_PIO_DRV1(n) (A1X_PIO_VADDR+A1X_PIO_DRV1_OFFSET(n))
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#define A1X_PIO_PUL0(n) (A1X_PIO_VADDR+A1X_PIO_PUL0_OFFSET(n))
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#define A1X_PIO_PUL1(n) (A1X_PIO_VADDR+A1X_PIO_PUL1_OFFSET(n))
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#define A1X_PIO_INT_CFG0 (A1X_PIO_VADDR+A1X_PIO_INT_CFG0_OFFSET)
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#define A1X_PIO_INT_CFG1 (A1X_PIO_VADDR+A1X_PIO_INT_CFG1_OFFSET)
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#define A1X_PIO_INT_CFG2 (A1X_PIO_VADDR+A1X_PIO_INT_CFG2_OFFSET)
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#define A1X_PIO_INT_CFG3 (A1X_PIO_VADDR+A1X_PIO_INT_CFG3_OFFSET)
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#define A1X_PIO_INT_CTL (A1X_PIO_VADDR+A1X_PIO_INT_CTL_OFFSET)
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#define A1X_PIO_INT_STA (A1X_PIO_VADDR+A1X_PIO_INT_STA_OFFSET)
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#define A1X_PIO_INT_DEB (A1X_PIO_VADDR+A1X_PIO_INT_DEB_OFFSET)
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#define A1X_SDR_PAD_DRV (A1X_PIO_VADDR+A1X_SDR_PAD_DRV_OFFSET)
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#define A1X_SDR_PAD_PUL (A1X_PIO_VADDR+A1X_SDR_PAD_PUL_OFFSET)
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/* Register bit field definitions ***************************************************/
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/* Port Configure Register 0, n=0-7 */
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#define PIO_CFG0_SHIFT(n) ((n) << 2)
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#define PIO_CFG0_MASK(n)) (7 << PIO_CFG0_SHIFT(n))
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# define PIO_CFG0(m,v) ((uint32_t)(v) << PIO_CFG0_SHIFT(n))
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/* Port Configure Register 1, n=8-15 */
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#define PIO_CFG1_SHIFT(n) (((n) - 8) << 2)
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#define PIO_CFG1_MASK(n)) (7 << PIO_CFG1_SHIFT(n))
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# define PIO_CFG1(m,v) ((uint32_t)(v) << PIO_CFG1_SHIFT(n))
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/* Port Configure Register 2, n=16-23 */
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#define PIO_CFG2_SHIFT(n) (((n) - 16) << 2)
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#define PIO_CFG2_MASK(n)) (7 << PIO_CFG2_SHIFT(n))
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# define PIO_CFG2(m,v) ((uint32_t)(v) << PIO_CFG2_SHIFT(n))
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/* Port Configure Register 3, n=24-31 */
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#define PIO_CFG3_SHIFT(n) (((n) - 24) << 2)
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#define PIO_CFG3_MASK(n)) (7 << PIO_CFG3_SHIFT(n))
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# define PIO_CFG3(m,v) ((uint32_t)(v) << PIO_CFG3_SHIFT(n))
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/* Then bring-in CPU-specific PIO CFG register definitions */
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#if defined(CONFIG_ARCH_CHIP_A10)
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# include "chip/a10_piocfg.h"
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#else
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# error Unrecognized A1X architecture
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#endif
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/* Port n Data Register, n=0-9 */
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#define PIO_DAT(n) (1 << (n)) /* PA data, n=0-31 */
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/* Port n Multi-Driving Register 0, n=0-9 */
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#define PIO_DRV0_SHIFT(n) ((n) << 1) /* PA DRV0, n=0-15 */
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#define PIO_DRV0_MASK(n) (3 << PIO_DRV0_SHIFT(n))
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# define PIO_DRV0_MASK(n,v) ((uint32_t)(v) << PIO_DRV0_SHIFT(n))
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/* Port n Multi-Driving Register 1, n=0-9 */
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#define PIO_DRV1_SHIFT(n) (((n) - 16) << 1) /* PA DRV1, n=16-31 */
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#define PIO_DRV1_MASK(n) (3 << PIO_DRV1_SHIFT(n))
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# define PIO_DRV1_MASK(n,v) ((uint32_t)(v) << PIO_DRV1_SHIFT(n))
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/* Port n Pull Register 0, n=0-9 */
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#define PIO_PUL0_SHIFT(n) ((n) << 1) /* PA PUL0, n=0-15 */
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#define PIO_PUL0_MASK(n) (3 << PIO_PUL0_SHIFT(n))
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# define PIO_PUL0_MASK(n,v) ((uint32_t)(v) << PIO_PUL0_SHIFT(n))
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/* Port n Pull Register 1, n=0-9 */
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#define PIO_PUL1_SHIFT(n) (((n) - 16) << 1) /* PA PUL1, n=16-31 */
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#define PIO_PUL1_MASK(n) (3 << PIO_PUL1_SHIFT(n))
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# define PIO_PUL1_MASK(n,v) ((uint32_t)(v) << PIO_PUL1_SHIFT(n))
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/* PIO Interrupt Configure Register 0 */
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#define PIO_INT_CFG0_SHIFT(n) ((n) << 2)
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#define PIO_INT_CFG0_MASK(n)) (15 << PIO_INT_CFG0_SHIFT(n))
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# define PIO_INT_CFG0(m,v) ((uint32_t)(v) << PIO_INT_CFG0_SHIFT(n))
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/* PIO Interrupt Configure Register 1 */
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#define PIO_INT_CFG1_SHIFT(n) (((n) - 8) << 2)
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#define PIO_INT_CFG1_MASK(n)) (15 << PIO_INT_CFG1_SHIFT(n))
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# define PIO_INT_CFG1(m,v) ((uint32_t)(v) << PIO_INT_CFG1_SHIFT(n))
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/* PIO Interrupt Configure Register 2 */
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#define PIO_INT_CFG2_SHIFT(n) (((n) - 16) << 2)
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#define PIO_INT_CFG2_MASK(n)) (15 << PIO_INT_CFG2_SHIFT(n))
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# define PIO_INT_CFG2(m,v) ((uint32_t)(v) << PIO_INT_CFG2_SHIFT(n))
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/* PIO Interrupt Configure Register 3 */
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#define PIO_INT_CFG3_SHIFT(n) (((n) - 24) << 2)
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#define PIO_INT_CFG3_MASK(n)) (15 << PIO_INT_CFG3_SHIFT(n))
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# define PIO_INT_CFG3(m,v) ((uint32_t)(v) << PIO_INT_CFG3_SHIFT(n))
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/* PIO Interrupt Control Register */
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#define PIO_INT_CTL(n) (1 << (n))
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/* PIO Interrupt Status Register */
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#define PIO_INT_STA(n) (1 << (n))
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/* PIO Interrupt Debounce Register */
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#define PIO_INT_DEB_CLKSEL (1 << 0) /* Bit 0: PIO Interrupt Clock Select */
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#define PIO_INT_DEB_CLKPRESC_SHIFT (4) /* Bit 4-6: Debounce Clock Pre-scale */
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#define PIO_INT_DEB_CLKPRESC_MASK (7 << PIO_INT_DEB_CLKPRESC_SHIFT)
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# define PIO_INT_DEB_CLKPRESC(n) ((uint32_t)(n) << PIO_INT_DEB_CLKPRESC_SHIFT)
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/* SDRAM Pad Multi-Driving Register */
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/* REVISIT: Missing register bit definitions */
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/* SDRAM Pad Pull Register */
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/* REVISIT: Missing register bit definitions */
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#endif /* __ARCH_ARM_SRC_A1X_CHIP_A1X_PIO_H */
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@ -250,6 +250,10 @@ int ov2640_main(int argc, char *argv[])
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return EXIT_FAILURE;
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}
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/* Now if everything is set up properly, the camera output should be
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* visible on the LCD.
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*/
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return EXIT_SUCCESS;
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}
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