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PIC32MZ: Add ability to select flash ECC options

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This commit is contained in:
Gregory Nutt 2015-03-01 09:08:44 -06:00
parent e2e7c791c1
commit 06f8baf709
4 changed files with 39 additions and 6 deletions
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10
arch/mips/src/pic32mz/Kconfig
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@ -364,6 +364,16 @@ config PIC32MZ_TRACE_ENABLE
---help--- ---help---
Trace Enable Trace Enable
config PIC32MZ_ECC_OPTION
int "PIC32 ECC control"
default 3
range 0 3
---help---
0: Flash ECC enabled (locked)
1: Dynamic Flash ECC enabled (locked) */
2: ECC / dynamic ECC disabled (locked) */
3: ECC / dynamic ECC disabled (writable) */
endmenu endmenu
menu "Device Configuration 1 (DEVCFG1)" menu "Device Configuration 1 (DEVCFG1)"

11
arch/mips/src/pic32mz/pic32mz-config.h
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@ -438,9 +438,18 @@
# define CONFIG_PIC32MZ_BOOTISA DEVCFG0_BOOT_MIPS32 # define CONFIG_PIC32MZ_BOOTISA DEVCFG0_BOOT_MIPS32
#endif #endif
#ifndef CONFIG_PIC32MZ_ECC_OPTION
# define CONFIG_PIC32MZ_ECC_OPTION 3
#endif
#if CONFIG_PIC32MZ_ECC_OPTION < 0 || CONFIG_PIC32MZ_ECC_OPTION > 3
# error Invalid CONFIG_PIC32MZ_ECC_OPTION Invalid
# undef CONFIG_PIC32MZ_ECC_OPTION
# define CONFIG_PIC32MZ_ECC_OPTION 3
#endif
#define CONFIG_PIC32MZ_FECCCON (CONFIG_PIC32MZ_ECC_OPTION << DEVCFG0_FECCCON_SHIFT)
/* Not yet configurable settings */ /* Not yet configurable settings */
#define CONFIG_PIC32MZ_FECCCON DEVCFG0_FECCCON_DISWR
#define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP_OFF #define CONFIG_PIC32MZ_FSLEEP DEVCFG0_FSLEEP_OFF
#define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_ALL #define CONFIG_PIC32MZ_DBGPER DEVCFG0_DBGPER_ALL
#define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAG_NORMAL #define CONFIG_PIC32MZ_EJTAGBEN DEVCFG0_EJTAG_NORMAL

23
arch/mips/src/pic32mz/pic32mz-lowinit.c
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@ -51,6 +51,7 @@
#include "chip/pic32mz-prefetch.h" #include "chip/pic32mz-prefetch.h"
#include "chip/pic32mz-osc.h" #include "chip/pic32mz-osc.h"
#include "pic32mz-config.h"
#include "pic32mz-lowconsole.h" #include "pic32mz-lowconsole.h"
#include "pic32mz-lowinit.h" #include "pic32mz-lowinit.h"
@ -59,8 +60,12 @@
****************************************************************************/ ****************************************************************************/
/* Maximum Frequencies ******************************************************/ /* Maximum Frequencies ******************************************************/
#define MAX_FLASH_ECC_HZ 66000000 /* Maximum FLASH speed (Hz) with ECC */ #if CONFIG_PIC32MZ_ECC_OPTION == 3
#define MAX_FLASH_NOECC_HZ 83000000 /* Maximum FLASH speed (Hz) without ECC */ # define MAX_FLASH_HZ 83000000 /* Maximum FLASH speed (Hz) without ECC */
#else
# define MAX_FLASH_HZ 66000000 /* Maximum FLASH speed (Hz) with ECC */
#endif
#define MAX_PBCLK 100000000 /* Max peripheral bus speed (Hz) */ #define MAX_PBCLK 100000000 /* Max peripheral bus speed (Hz) */
#define MAX_PBCLK7 200000000 /* Max peripheral bus speed (Hz) for PBCLK7 */ #define MAX_PBCLK7 200000000 /* Max peripheral bus speed (Hz) for PBCLK7 */
@ -199,15 +204,23 @@ static inline void pic32mz_prefetch(void)
unsigned int residual; unsigned int residual;
uint32_t regval; uint32_t regval;
/* Configure pre-fetch cache FLASH wait states (assuming ECC is enabled) */ /* Configure pre-fetch cache FLASH wait states (assuming ECC is enabled).
* REVISIT: Is this calculation right? It seems like residual should be
*
* residual = BOARD_CPU_CLOCK / nwaits
*
* This logic uses:
*
* BOARD_CPU_CLOCK - nwaits * MAX_FLASH_HZ
*/
residual = BOARD_CPU_CLOCK; residual = BOARD_CPU_CLOCK;
nwaits = 0; nwaits = 0;
while (residual > MAX_FLASH_ECC_HZ) while (residual > MAX_FLASH_HZ)
{ {
nwaits++; nwaits++;
residual -= MAX_FLASH_ECC_HZ; residual -= MAX_FLASH_HZ;
} }
DEBUGASSERT(nwaits < 8); DEBUGASSERT(nwaits < 8);

1
configs/pic32mz-starterkit/nsh/defconfig
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@ -156,6 +156,7 @@ CONFIG_PIC32MZ_UART1=y
# CONFIG_PIC32MZ_JTAG_ENABLE is not set # CONFIG_PIC32MZ_JTAG_ENABLE is not set
CONFIG_PIC32MZ_ICESEL_CH2=y CONFIG_PIC32MZ_ICESEL_CH2=y
# CONFIG_PIC32MZ_TRACE_ENABLE is not set # CONFIG_PIC32MZ_TRACE_ENABLE is not set
CONFIG_PIC32MZ_ECC_OPTION=3
# #
# Device Configuration 1 (DEVCFG1) # Device Configuration 1 (DEVCFG1)