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Merge remote-tracking branch 'origin/master' into bas24

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This commit is contained in:
Gregory Nutt 2014-11-06 14:17:19 -06:00
commit 070694a71f
3 changed files with 66 additions and 57 deletions
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9
arch/arm/src/efm32/chip/efm32_usb.h
View File

@ -2118,6 +2118,10 @@
#define _USB_DAINT_RESETVALUE 0x00000000UL /* Default value for USB_DAINT */
#define _USB_DAINT_MASK 0x007F007FUL /* Mask for USB_DAINT */
#define _USB_DAINT_INEPINT_SHIFT 0 /* Shift value for IN endpoint interrupt bits */
#define _USB_DAINT_INEPINT_MASK 0x7FUL /* Mask of all IN endpoint interrupt bits */
#define USB_DAINT_INEPINT(n) (0x1UL << ((n)+_USB_DAINT_INEPINT_SHIFT))
#define USB_DAINT_INEPINT0 (0x1UL << 0) /* IN Endpoint 0 Interrupt Bit */
#define _USB_DAINT_INEPINT0_SHIFT 0 /* Shift value for USB_INEPINT0 */
#define _USB_DAINT_INEPINT0_MASK 0x1UL /* Bit mask for USB_INEPINT0 */
@ -2153,6 +2157,11 @@
#define _USB_DAINT_INEPINT6_MASK 0x40UL /* Bit mask for USB_INEPINT6 */
#define _USB_DAINT_INEPINT6_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DAINT */
#define USB_DAINT_INEPINT6_DEFAULT (_USB_DAINT_INEPINT6_DEFAULT << 6) /* Shifted mode DEFAULT for USB_DAINT */
#define _USB_DAINT_OUTEPINT_SHIFT 16 /* Shift value for all IN endpoint interrupt bits */
#define _USB_DAINT_OUTEPINT_MASK 0x7F0000UL /* Mask of OUT IN endpoint interrupt bits */
#define USB_DAINT_OUTEPINT(n) (0x1UL << ((n)+_USB_DAINT_OUTEPINT_SHIFT))
#define USB_DAINT_OUTEPINT0 (0x1UL << 16) /* OUT Endpoint 0 Interrupt Bit */
#define _USB_DAINT_OUTEPINT0_SHIFT 16 /* Shift value for USB_OUTEPINT0 */
#define _USB_DAINT_OUTEPINT0_MASK 0x10000UL /* Bit mask for USB_OUTEPINT0 */

72
arch/arm/src/efm32/efm32_usbdev.c
View File

@ -2002,7 +2002,7 @@ static void efm32_usbreset(struct efm32_usbdev_s *priv)
/* Mask all device endpoint interrupts except EP0 */
regval = (USB_DAINT_IEP(EP0) | USB_DAINT_OEP(EP0));
regval = (USB_DAINT_INEPINT(EP0) | USB_DAINT_OUTEPINT(EP0));
efm32_putreg(regval, EFM32_USB_DAINTMSK);
/* Unmask OUT interrupts */
@ -2600,7 +2600,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv)
regval = efm32_getreg(EFM32_USB_DAINT);
regval &= efm32_getreg(EFM32_USB_DAINTMSK);
daint = (regval & _USB_DAINT_OEP_MASK) >> _USB_DAINT_OEP_SHIFT;
daint = (regval & _USB_DAINT_OUTEPINT_MASK) >> _USB_DAINT_OUTEPINT_SHIFT;
if (daint == 0)
{
@ -2615,7 +2615,7 @@ static inline void efm32_epout_interrupt(FAR struct efm32_usbdev_s *priv)
*/
regval = efm32_getreg(EFM32_USB_DAINT);
daint = (regval & _USB_DAINT_OEP_MASK) >> _USB_DAINT_OEP_SHIFT;
daint = (regval & _USB_DAINT_OUTEPINT_MASK) >> _USB_DAINT_OUTEPINT_SHIFT;
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EPOUTUNEXPECTED),
(uint16_t)regval);
@ -2831,7 +2831,7 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv)
daint = efm32_getreg(EFM32_USB_DAINT);
daint &= efm32_getreg(EFM32_USB_DAINTMSK);
daint &= _USB_DAINT_IEP_MASK;
daint &= _USB_DAINT_INEPINT_MASK;
if (daint == 0)
{
@ -2849,7 +2849,7 @@ static inline void efm32_epin_interrupt(FAR struct efm32_usbdev_s *priv)
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_EPINUNEXPECTED),
(uint16_t)daint);
daint &= _USB_DAINT_IEP_MASK;
daint &= _USB_DAINT_INEPINT_MASK;
epno = 0;
while (daint)
@ -3125,12 +3125,12 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
/* Decode status fields */
epphy = (regval & _USB_GRXSTSD_EPNUM_MASK) >> _USB_GRXSTSD_EPNUM_SHIFT;
epphy = (regval & _USB_GRXSTSP_CHEPNUM_MASK) >> _USB_GRXSTSP_CHEPNUM_SHIFT;
privep = &priv->epout[epphy];
/* Handle the RX event according to the packet status field */
switch (regval & _USB_GRXSTSD_PKTSTS_MASK)
switch (regval & _USB_GRXSTSP_PKTSTS_MASK)
{
/* Global OUT NAK. This indicate that the global OUT NAK bit has taken
* effect.
@ -3139,7 +3139,7 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
* Care.
*/
case USB_GRXSTSD_PKTSTS_OUTNAK:
case USB_GRXSTSP_PKTSTS_GOUTNAK:
{
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_OUTNAK), 0);
}
@ -3151,10 +3151,10 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
* EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID.
*/
case USB_GRXSTSD_PKTSTS_OUTRECVD:
case USB_GRXSTSP_PKTSTS_PKTRCV:
{
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_OUTRECVD), epphy);
bcnt = (regval & _USB_GRXSTSD_BCNT_MASK) >> _USB_GRXSTSD_BCNT_SHIFT;
bcnt = (regval & _USB_GRXSTSP_BCNT_MASK) >> _USB_GRXSTSP_BCNT_SHIFT;
if (bcnt > 0)
{
efm32_epout_receive(privep, bcnt);
@ -3171,7 +3171,7 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
* which the data transfer is complete, DPID = Don't Care.
*/
case USB_GRXSTSD_PKTSTS_OUTDONE:
case USB_GRXSTSP_PKTSTS_XFERCOMPL:
{
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_OUTDONE), epphy);
}
@ -3187,7 +3187,7 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
* DPID = Don't Care.
*/
case USB_GRXSTSD_PKTSTS_SETUPDONE:
case USB_GRXSTSP_PKTSTS_SETUPCOMPL:
{
usbtrace(TRACE_INTDECODE(EFM32_TRACEINTID_SETUPDONE), epphy);
}
@ -3199,7 +3199,7 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
* PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0.
*/
case USB_GRXSTSD_PKTSTS_SETUPRECVD:
case USB_GRXSTSP_PKTSTS_SETUPRCV:
{
uint16_t datlen;
@ -3249,7 +3249,7 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
default:
{
usbtrace(TRACE_DEVERROR(EFM32_TRACEERR_INVALIDPARMS),
(regval & _USB_GRXSTSD_PKTSTS_MASK) >> _USB_GRXSTSD_PKTSTS_SHIFT);
(regval & _USB_GRXSTSP_PKTSTS_MASK) >> _USB_GRXSTSP_PKTSTS_SHIFT);
}
break;
}
@ -3257,7 +3257,7 @@ static inline void efm32_rxinterrupt(FAR struct efm32_usbdev_s *priv)
/* Enable the Rx Status Queue Level interrupt */
regval = efm32_getreg(EFM32_USB_GINTMSK);
regval |= USB_GINTMSK_RXFLVL;
regval |= USB_GINTMSK_RXFLVLMSK;
efm32_putreg(regval, EFM32_USB_GINTMSK);
}
@ -3705,7 +3705,7 @@ static void efm32_enablegonak(FAR struct efm32_ep_s *privep)
/* Enable Global OUT NAK mode in the core. */
regval = efm32_getreg(EFM32_USB_DCTL);
regval |= USB_DCTL_SGONAK;
regval |= USB_DCTL_SGOUTNAK;
efm32_putreg(regval, EFM32_USB_DCTL);
#if 0
@ -3726,7 +3726,7 @@ static void efm32_enablegonak(FAR struct efm32_ep_s *privep)
* in OTGFS DCTL register?
*/
while ((efm32_getreg(EFM32_USB_DCTL) & USB_DCTL_GONSTS) == 0);
while ((efm32_getreg(EFM32_USB_DCTL) & USB_DCTL_GOUTNAKSTS) == 0);
#endif
}
@ -3745,7 +3745,7 @@ static void efm32_disablegonak(FAR struct efm32_ep_s *privep)
/* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */
regval = efm32_getreg(EFM32_USB_DCTL);
regval |= USB_DCTL_CGONAK;
regval |= USB_DCTL_CGOUTNAK;
efm32_putreg(regval, EFM32_USB_DCTL);
}
@ -3839,7 +3839,7 @@ static int efm32_epout_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
/* Enable the interrupt for this endpoint */
regval = efm32_getreg(EFM32_USB_DAINTMSK);
regval |= USB_DAINT_OEP(privep->epphy);
regval |= USB_DAINT_OUTEPINT(privep->epphy);
efm32_putreg(regval, EFM32_USB_DAINTMSK);
return OK;
}
@ -3877,19 +3877,19 @@ static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
switch (maxpacket)
{
case 8:
mpsiz = _USB_DIEP0CTL_MPS_8;
mpsiz = _USB_DIEP0CTL_MPS_8B;
break;
case 16:
mpsiz = _USB_DIEP0CTL_MPS_16;
mpsiz = _USB_DIEP0CTL_MPS_16B;
break;
case 32:
mpsiz = _USB_DIEP0CTL_MPS_32;
mpsiz = _USB_DIEP0CTL_MPS_32B;
break;
case 64:
mpsiz = _USB_DIEP0CTL_MPS_64;
mpsiz = _USB_DIEP0CTL_MPS_64B;
break;
default:
@ -3936,7 +3936,7 @@ static int efm32_epin_configure(FAR struct efm32_ep_s *privep, uint8_t eptype,
/* Enable the interrupt for this endpoint */
regval = efm32_getreg(EFM32_USB_DAINTMSK);
regval |= USB_DAINT_IEP(privep->epphy);
regval |= USB_DAINT_INEPINT(privep->epphy);
efm32_putreg(regval, EFM32_USB_DAINTMSK);
return OK;
@ -4066,7 +4066,7 @@ static void efm32_epout_disable(FAR struct efm32_ep_s *privep)
/* Disable endpoint interrupts */
regval = efm32_getreg(EFM32_USB_DAINTMSK);
regval &= ~USB_DAINT_OEP(privep->epphy);
regval &= ~USB_DAINT_OUTEPINT(privep->epphy);
efm32_putreg(regval, EFM32_USB_DAINTMSK);
/* Cancel any queued read requests */
@ -4161,7 +4161,7 @@ static void efm32_epin_disable(FAR struct efm32_ep_s *privep)
/* Disable endpoint interrupts */
regval = efm32_getreg(EFM32_USB_DAINTMSK);
regval &= ~USB_DAINT_IEP(privep->epphy);
regval &= ~USB_DAINT_INEPINT(privep->epphy);
efm32_putreg(regval, EFM32_USB_DAINTMSK);
/* Cancel any queued write requests */
@ -4908,7 +4908,7 @@ static int efm32_pullup(struct usbdev_s *dev, bool enable)
* register
*/
regval &= ~USB_DCTL_SDIS;
regval &= ~USB_DCTL_SFTDISCON;
}
else
{
@ -4916,7 +4916,7 @@ static int efm32_pullup(struct usbdev_s *dev, bool enable)
* register
*/
regval |= USB_DCTL_SDIS;
regval |= USB_DCTL_SFTDISCON;
}
efm32_putreg(regval, EFM32_USB_DCTL);
@ -5193,7 +5193,7 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv)
* interrupts will occur when the TxFIFO is truly empty (not just half full).
*/
efm32_putreg(USB_GAHBCFG_TXFELVL, EFM32_USB_GAHBCFG);
efm32_putreg(USB_GAHBCFG_NPTXFEMPLVL_EMPTY, EFM32_USB_GAHBCFG);
/* Common USB OTG core initialization */
/* Reset after a PHY select and set Host mode. First, wait for AHB master
@ -5366,23 +5366,23 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv)
/* Enable the interrupts in the INTMSK */
regval = (USB_GINTMSK_RXFLVL | USB_GINTMSK_USBSUSP | USB_GINTMSK_ENUMDNE |
USB_GINTMSK_IEP | USB_GINTMSK_OEP | USB_GINTMSK_USBRST);
regval = (USB_GINTMSK_RXFLVLMSK | USB_GINTMSK_USBSUSPMSK | USB_GINTMSK_ENUMDONEMSK |
USB_GINTMSK_IEPINTMSK | USB_GINTMSK_OEPINTMSK | USB_GINTMSK_USBRSTMSK);
#ifdef CONFIG_USBDEV_ISOCHRONOUS
regval |= (USB_GINTMSK_IISOIXFR | USB_GINTMSK_IISOOXFR);
regval |= (USB_GINTMSK_INCOMPISOINMSK | USB_GINTMSK_INCOMPLPMSK);
#endif
#ifdef CONFIG_USBDEV_SOFINTERRUPT
regval |= USB_GINTMSK_SOF;
regval |= USB_GINTMSK_SOFMSK;
#endif
#ifdef CONFIG_USBDEV_VBUSSENSING
regval |= (USB_GINTMSK_OTG | USB_GINTMSK_SRQ);
regval |= (USB_GINTMSK_OTGINTMSK | USB_GINTMSK_SESSREQINTMSK);
#endif
#ifdef CONFIG_DEBUG_USB
regval |= USB_GINTMSK_MMIS;
regval |= USB_GINTMSK_MODEMISMSK;
#endif
efm32_putreg(regval, EFM32_USB_GINTMSK);
@ -5393,7 +5393,7 @@ static void efm32_hwinitialize(FAR struct efm32_usbdev_s *priv)
* empty (not just half full).
*/
efm32_putreg(USB_GAHBCFG_GINTMSK | USB_GAHBCFG_TXFELVL,
efm32_putreg(USB_GAHBCFG_GLBLINTRMSK | USB_GAHBCFG_NPTXFEMPLVL_EMPTY,
EFM32_USB_GAHBCFG);
}

42
arch/arm/src/efm32/efm32_usbhost.c
View File

@ -809,7 +809,7 @@ static void efm32_chan_configure(FAR struct efm32_usbhost_s *priv, int chidx)
/* Make sure host channel interrupts are enabled. */
efm32_modifyreg(EFM32_USB_GINTMSK, 0, USB_GINTMSK_HC);
efm32_modifyreg(EFM32_USB_GINTMSK, 0, USB_GINTMSK_HCHINTMSK);
/* Program the HCCHAR register */
@ -2329,7 +2329,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
/* Disable the RxFIFO non-empty interrupt */
intmsk = efm32_getreg(EFM32_USB_GINTMSK);
intmsk &= ~USB_GINTMSK_RXFLVL;
intmsk &= ~USB_GINTMSK_RXFLVLMSK;
efm32_putreg(EFM32_USB_GINTMSK, intmsk);
/* Read and pop the next status from the Rx FIFO */
@ -2402,7 +2402,7 @@ static inline void efm32_gint_rxflvlisr(FAR struct efm32_usbhost_s *priv)
/* Re-enable the RxFIFO non-empty interrupt */
intmsk |= USB_GINTMSK_RXFLVL;
intmsk |= USB_GINTMSK_RXFLVLMSK;
efm32_putreg(EFM32_USB_GINTMSK, intmsk);
}
@ -2949,7 +2949,7 @@ static void efm32_gint_enable(void)
/* Set the GINTMSK bit to unmask the interrupt */
regval = efm32_getreg(EFM32_USB_GAHBCFG);
regval |= USB_GAHBCFG_GINTMSK;
regval |= USB_GAHBCFG_GLBLINTRMSK;
efm32_putreg(EFM32_USB_GAHBCFG, regval);
}
@ -2960,7 +2960,7 @@ static void efm32_gint_disable(void)
/* Clear the GINTMSK bit to mask the interrupt */
regval = efm32_getreg(EFM32_USB_GAHBCFG);
regval &= ~USB_GAHBCFG_GINTMSK;
regval &= ~USB_GAHBCFG_GLBLINTRMSK;
efm32_putreg(EFM32_USB_GAHBCFG, regval);
}
@ -3001,35 +3001,35 @@ static inline void efm32_hostinit_enable(void)
/* Enable the host interrupts */
/* Common interrupts:
*
* USB_GINTMSK_WKUP : Resume/remote wakeup detected interrupt
* USB_GINTMSK_USBSUSP : USB suspend
* USB_GINTMSK_WKUPINTMSK : Resume/remote wakeup detected interrupt
* USB_GINTMSK_USBSUSPMSK : USB suspend
*/
regval = (USB_GINTMSK_WKUP | USB_GINTMSK_USBSUSP);
regval = (USB_GINTMSK_WKUPINTMSK | USB_GINTMSK_USBSUSPMSK);
/* If OTG were supported, we would need to enable the following as well:
*
* USB_GINTMSK_OTG : OTG interrupt
* USB_GINTMSK_SRQ : Session request/new session detected interrupt
* USB_GINTMSK_CIDSCHG : Connector ID status change
* USB_GINTMSK_OTGINTMSK : OTG interrupt
* USB_GINTMSK_SESSREQINTMSK : Session request/new session detected interrupt
* USB_GINTMSK_CONIDSTSCHNGMSK : Connector ID status change
*/
/* Host-specific interrupts
*
* USB_GINTMSK_SOF : Start of frame
* USB_GINTMSK_RXFLVL : RxFIFO non-empty
* USB_GINTMSK_IISOOXFR : Incomplete isochronous OUT transfer
* USB_GINTMSK_HPRT : Host port interrupt
* USB_GINTMSK_HC : Host channels interrupt
* USB_GINTMSK_DISC : Disconnect detected interrupt
* USB_GINTMSK_SOFMSK : Start of frame
* USB_GINTMSK_RXFLVLMSK : RxFIFO non-empty
* USB_GINTMSK_INCOMPLPMSK : Incomplete isochronous OUT transfer
* USB_GINTMSK_PRTINTMSK : Host port interrupt
* USB_GINTMSK_HCHINTMSK : Host channels interrupt
* USB_GINTMSK_DISCONNINTMSK : Disconnect detected interrupt
*/
#ifdef CONFIG_EFM32_OTGFS_SOFINTR
regval |= (USB_GINTMSK_SOF | USB_GINTMSK_RXFLVL | USB_GINTMSK_IISOOXFR |
USB_GINTMSK_HPRT | USB_GINTMSK_HC | USB_GINTMSK_DISC);
regval |= (USB_GINTMSK_SOFMSK | USB_GINTMSK_RXFLVLMSK | USB_GINTMSK_INCOMPLPMSK |
USB_GINTMSK_PRTINTMSK | USB_GINTMSK_HCHINTMSK | USB_GINTMSK_DISCONNINTMSK);
#else
regval |= (USB_GINTMSK_RXFLVL | USB_GINTMSK_IPXFR | USB_GINTMSK_HPRT |
USB_GINTMSK_HC | USB_GINTMSK_DISC);
regval |= (USB_GINTMSK_RXFLVLMSK | USB_GINTMSK_IPXFR | USB_GINTMSK_PRTINTMSK |
USB_GINTMSK_HCHINTMSK | USB_GINTMSK_DISCONNINTMSK);
#endif
efm32_putreg(EFM32_USB_GINTMSK, regval);
}