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fix lpc43_gpdma, largely typos

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ahb 2017-03-07 11:16:08 +01:00
parent 6b0d7335a2
commit 073b3d2c9a
1 changed files with 11 additions and 11 deletions
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22
arch/arm/src/lpc43xx/lpc43_gpdma.c
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@ -323,7 +323,7 @@ void weak_function up_dmainitialize(void)
/* Enable the DMA controller (for little endian operation) */ /* Enable the DMA controller (for little endian operation) */
putreg32(GPDMA_CONFIG_ENA, LPC43_GPDMA_CONFIG); putreg32(GPDMA_CONFIG_ENA, LPC43_GPDMA_GLOBAL_CONFIG);
} }
/**************************************************************************** /****************************************************************************
@ -667,16 +667,16 @@ void lpc43_dmasample(DMA_HANDLE handle, struct lpc43_dmaregs_s *regs)
/* Sample the global DMA registers */ /* Sample the global DMA registers */
regs->gbl.intst = getreg32(LPC43_GPDMA_INTSTAT); regs->gbl.intst = getreg32(LPC43_GPDMA_INTSTAT);
regs->gbl.inttcstat = getreg32(LPC43_GPDMA_INTTCSTAT); regs->gbl.inttcst = getreg32(LPC43_GPDMA_INTTCSTAT);
regs->gbl.interrstat = getreg32(LPC43_GPDMA_INTERRSTAT); regs->gbl.interrst = getreg32(LPC43_GPDMA_INTERRSTAT);
regs->gbl.rawinttcstat = getreg32(LPC43_GPDMA_RAWINTTCSTAT); regs->gbl.rawinttcst = getreg32(LPC43_GPDMA_RAWINTTCSTAT);
regs->gbl.rawinterrstat = getreg32(LPC43_GPDMA_RAWINTERRSTAT); regs->gbl.rawinterrst = getreg32(LPC43_GPDMA_RAWINTERRSTAT);
regs->gbl.enbldchns = getreg32(LPC43_GPDMA_ENBLDCHNS); regs->gbl.enbldchns = getreg32(LPC43_GPDMA_ENBLDCHNS);
regs->gbl.softbreq = getreg32(LPC43_GPDMA_SOFTBREQ); regs->gbl.softbreq = getreg32(LPC43_GPDMA_SOFTBREQ);
regs->gbl.softsreq = getreg32(LPC43_GPDMA_SOFTSREQ); regs->gbl.softsreq = getreg32(LPC43_GPDMA_SOFTSREQ);
regs->gbl.softlbreq = getreg32(LPC43_GPDMA_SOFTLBREQ); regs->gbl.softlbreq = getreg32(LPC43_GPDMA_SOFTLBREQ);
regs->gbl.softlsreq = getreg32(LPC43_GPDMA_SOFTLSREQ); regs->gbl.softlsreq = getreg32(LPC43_GPDMA_SOFTLSREQ);
regs->gbl.config = getreg32(LPC43_GPDMA_CONFIG); regs->gbl.config = getreg32(LPC43_GPDMA_GLOBAL_CONFIG);
regs->gbl.sync = getreg32(LPC43_GPDMA_SYNC); regs->gbl.sync = getreg32(LPC43_GPDMA_SYNC);
/* Sample the DMA channel registers */ /* Sample the DMA channel registers */
@ -712,13 +712,13 @@ void lpc43_dmadump(DMA_HANDLE handle, const struct lpc43_dmaregs_s *regs, const
dmainfo(" INTST[%08x]: %08x\n", dmainfo(" INTST[%08x]: %08x\n",
LPC43_GPDMA_INTSTAT, regs->gbl.intst); LPC43_GPDMA_INTSTAT, regs->gbl.intst);
dmainfo(" INTTCSTAT[%08x]: %08x\n", dmainfo(" INTTCSTAT[%08x]: %08x\n",
LPC43_GPDMA_INTTCSTAT, regs->gbl.inttcstat); LPC43_GPDMA_INTTCSTAT, regs->gbl.inttcst);
dmainfo(" INTERRSTAT[%08x]: %08x\n", dmainfo(" INTERRSTAT[%08x]: %08x\n",
LPC43_GPDMA_INTERRSTAT, regs->gbl.interrstat); LPC43_GPDMA_INTERRSTAT, regs->gbl.interrst);
dmainfo(" RAWINTTCSTAT[%08x]: %08x\n", dmainfo(" RAWINTTCSTAT[%08x]: %08x\n",
LPC43_GPDMA_RAWINTTCSTAT, regs->gbl.rawinttcstat); LPC43_GPDMA_RAWINTTCSTAT, regs->gbl.rawinttcst);
dmainfo(" RAWINTERRSTAT[%08x]: %08x\n", dmainfo(" RAWINTERRSTAT[%08x]: %08x\n",
LPC43_GPDMA_RAWINTERRSTAT, regs->gbl.rawinterrstat); LPC43_GPDMA_RAWINTERRSTAT, regs->gbl.rawinterrst);
dmainfo(" ENBLDCHNS[%08x]: %08x\n", dmainfo(" ENBLDCHNS[%08x]: %08x\n",
LPC43_GPDMA_ENBLDCHNS, regs->gbl.enbldchns); LPC43_GPDMA_ENBLDCHNS, regs->gbl.enbldchns);
dmainfo(" SOFTBREQ[%08x]: %08x\n", dmainfo(" SOFTBREQ[%08x]: %08x\n",
@ -730,7 +730,7 @@ void lpc43_dmadump(DMA_HANDLE handle, const struct lpc43_dmaregs_s *regs, const
dmainfo(" SOFTLSREQ[%08x]: %08x\n", dmainfo(" SOFTLSREQ[%08x]: %08x\n",
LPC43_GPDMA_SOFTLSREQ, regs->gbl.softlsreq); LPC43_GPDMA_SOFTLSREQ, regs->gbl.softlsreq);
dmainfo(" CONFIG[%08x]: %08x\n", dmainfo(" CONFIG[%08x]: %08x\n",
LPC43_GPDMA_CONFIG, regs->gbl.config); LPC43_GPDMA_GLOBAL_CONFIG, regs->gbl.config);
dmainfo(" SYNC[%08x]: %08x\n", dmainfo(" SYNC[%08x]: %08x\n",
LPC43_GPDMA_SYNC, regs->gbl.sync); LPC43_GPDMA_SYNC, regs->gbl.sync);