diff --git a/arch/arm/src/arm/arm.h b/arch/arm/src/arm/arm.h
index a1473b1bd5..7764965a0c 100644
--- a/arch/arm/src/arm/arm.h
+++ b/arch/arm/src/arm/arm.h
@@ -33,19 +33,19 @@
 
 /* PSR bits */
 
-#define MODE_MASK       0x0000001f /* Bits 0-4: Mode bits */
-#  define USR26_MODE    0x00000000 /*   26-bit User mode */
-#  define FIQ26_MODE    0x00000001 /*   26-bit FIQ mode */
-#  define IRQ26_MODE    0x00000002 /*   26-bit IRQ mode */
-#  define SVC26_MODE    0x00000003 /*   26-bit Supervisor mode */
-#  define MODE32_BIT    0x00000010 /*   Bit 4: 32-bit mode */
-#  define USR_MODE      0x00000010 /*   32-bit User mode */
-#  define FIQ_MODE      0x00000011 /*   32-bit FIQ mode */
-#  define IRQ_MODE      0x00000012 /*   32-bit IRQ mode */
-#  define SVC_MODE      0x00000013 /*   32-bit Supervisor mode */
-#  define ABT_MODE      0x00000017 /*   32-bit Abort mode */
-#  define UND_MODE      0x0000001b /*   32-bit Undefined mode */
-#  define SYSTEM_MODE   0x0000001f /*   32-bit System mode */
+#define PSR_MODE_MASK   0x0000001f /* Bits 0-4: Mode bits */
+#define PSR_MODE_USR26  0x00000000 /*   26-bit User mode */
+#define PSR_MODE_FIQ26  0x00000001 /*   26-bit FIQ mode */
+#define PSR_MODE_IRQ26  0x00000002 /*   26-bit IRQ mode */
+#define PSR_MODE_SVC26  0x00000003 /*   26-bit Supervisor mode */
+#define PSR_MODE_MODE32 0x00000010 /*   Bit 4: 32-bit mode */
+#define PSR_MODE_USR    0x00000010 /*   32-bit User mode */
+#define PSR_MODE_FIQ    0x00000011 /*   32-bit FIQ mode */
+#define PSR_MODE_IRQ    0x00000012 /*   32-bit IRQ mode */
+#define PSR_MODE_SVC    0x00000013 /*   32-bit Supervisor mode */
+#define PSR_MODE_ABT    0x00000017 /*   32-bit Abort mode */
+#define PSR_MODE_UND    0x0000001b /*   32-bit Undefined mode */
+#define PSR_MODE_SYS    0x0000001f /*   32-bit System mode */
 #define PSR_T_BIT       0x00000020 /* Bit 5: Thumb state */
 #define PSR_F_BIT       0x00000040 /* Bit 6: FIQ disable */
 #define PSR_I_BIT       0x00000080 /* Bit 7: IRQ disable */
diff --git a/arch/arm/src/arm/arm_head.S b/arch/arm/src/arm/arm_head.S
index 170b87a220..42218ec3b4 100644
--- a/arch/arm/src/arm/arm_head.S
+++ b/arch/arm/src/arm/arm_head.S
@@ -222,7 +222,7 @@
 __start:
 	/* Make sure that we are in SVC mode with all IRQs disabled */
 
-	mov		r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
+	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
 	msr		cpsr_c, r0
 
 	/* Initialize DRAM using a macro provided by board-specific logic */
diff --git a/arch/arm/src/arm/arm_initialstate.c b/arch/arm/src/arm/arm_initialstate.c
index 3b0544ae2b..d247838c20 100644
--- a/arch/arm/src/arm/arm_initialstate.c
+++ b/arch/arm/src/arm/arm_initialstate.c
@@ -102,20 +102,20 @@ void up_initial_state(struct tcb_s *tcb)
     {
       /* It is a kernel thread.. set supervisor mode */
 
-      cpsr               = SVC_MODE | PSR_F_BIT;
+      cpsr               = PSR_MODE_SVC | PSR_F_BIT;
     }
   else
     {
       /* It is a normal task or a pthread.  Set user mode */
 
-      cpsr               = USR_MODE | PSR_F_BIT;
+      cpsr               = PSR_MODE_USR | PSR_F_BIT;
     }
 #else
   /* If the kernel build is not selected, then all threads run in
    * supervisor-mode.
    */
 
-  cpsr                   = SVC_MODE | PSR_F_BIT;
+  cpsr                   = PSR_MODE_SVC | PSR_F_BIT;
 #endif
 
   /* Enable or disable interrupts, based on user configuration */
diff --git a/arch/arm/src/arm/arm_nommuhead.S b/arch/arm/src/arm/arm_nommuhead.S
index 4e073837f8..514e2129d6 100644
--- a/arch/arm/src/arm/arm_nommuhead.S
+++ b/arch/arm/src/arm/arm_nommuhead.S
@@ -58,7 +58,7 @@ __start:
 
 	/* First, setup initial processor mode */
 
-	mov		r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
 	msr		cpsr, r0
 
 	/* Setup system stack (and get the BSS range) */
diff --git a/arch/arm/src/arm/arm_schedulesigaction.c b/arch/arm/src/arm/arm_schedulesigaction.c
index 30a1d5882c..fb401d45f5 100644
--- a/arch/arm/src/arm/arm_schedulesigaction.c
+++ b/arch/arm/src/arm/arm_schedulesigaction.c
@@ -131,7 +131,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
                */
 
               CURRENT_REGS[REG_PC]      = (uint32_t)arm_sigdeliver;
-              CURRENT_REGS[REG_CPSR]    = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
+              CURRENT_REGS[REG_CPSR]    = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
 
               /* And make sure that the saved context in the TCB
                * is the same as the interrupt return context.
@@ -163,7 +163,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
            */
 
           tcb->xcp.regs[REG_PC]      = (uint32_t)arm_sigdeliver;
-          tcb->xcp.regs[REG_CPSR]    = SVC_MODE | PSR_I_BIT | PSR_F_BIT;
+          tcb->xcp.regs[REG_CPSR]    = PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT;
         }
     }
 }
diff --git a/arch/arm/src/arm/arm_vectors.S b/arch/arm/src/arm/arm_vectors.S
index 811008144e..5616988ef6 100644
--- a/arch/arm/src/arm/arm_vectors.S
+++ b/arch/arm/src/arm/arm_vectors.S
@@ -89,8 +89,8 @@ arm_vectorirq:
 
 	/* Then switch back to SVC mode */
 
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	bic	lr, lr, #PSR_MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
 	msr	cpsr_c, lr		/* Switch to SVC mode */
 
 	/* Create a context structure.  First set aside a stack frame
@@ -221,8 +221,8 @@ arm_vectordata:
 
 	/* Then switch back to SVC mode */
 
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	bic	lr, lr, #PSR_MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
 	msr	cpsr_c, lr		/* Switch to SVC mode */
 
 	/* Create a context structure.  First set aside a stack frame
@@ -297,8 +297,8 @@ arm_vectorprefetch:
 
 	/* Then switch back to SVC mode */
 
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	bic	lr, lr, #PSR_MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
 	msr	cpsr_c, lr		/* Switch to SVC mode */
 
 	/* Create a context structure.  First set aside a stack frame
@@ -366,8 +366,8 @@ arm_vectorundefinsn:
 
 	/* Then switch back to SVC mode */
 
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	bic	lr, lr, #PSR_MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
 	msr	cpsr_c, lr		/* Switch to SVC mode */
 
 	/* Create a context structure.  First set aside a stack frame
diff --git a/arch/arm/src/c5471/c5471_irq.c b/arch/arm/src/c5471/c5471_irq.c
index 43d93c8838..d5a0b19db8 100644
--- a/arch/arm/src/c5471/c5471_irq.c
+++ b/arch/arm/src/c5471/c5471_irq.c
@@ -170,7 +170,7 @@ void up_irqinitialize(void)
   /* And finally, enable interrupts */
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
-  up_irq_restore(SVC_MODE | PSR_F_BIT);
+  up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
 #endif
 }
 
diff --git a/arch/arm/src/c5471/c5471_vectors.S b/arch/arm/src/c5471/c5471_vectors.S
index 592cb8789c..10f369f04f 100644
--- a/arch/arm/src/c5471/c5471_vectors.S
+++ b/arch/arm/src/c5471/c5471_vectors.S
@@ -87,8 +87,8 @@ arm_vectorirq:
 
 	/* Then switch back to SVC mode */
 
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	bic	lr, lr, #PSR_MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
 	msr	cpsr_c, lr		/* Switch to SVC mode */
 
 	/* Create a context structure.  First set aside a stack frame
@@ -245,8 +245,8 @@ arm_vectordata:
 
 	/* Then switch back to SVC mode */
 
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	bic	lr, lr, #PSR_MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
 	msr	cpsr_c, lr		/* Switch to SVC mode */
 
 	/* Create a context structure.  First set aside a stack frame
@@ -311,8 +311,8 @@ arm_vectorprefetch:
 
 	/* Then switch back to SVC mode */
 
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	bic	lr, lr, #PSR_MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
 	msr	cpsr_c, lr		/* Switch to SVC mode */
 
 	/* Create a context structure.  First set aside a stack frame
@@ -377,8 +377,8 @@ arm_vectorundefinsn:
 
 	/* Then switch back to SVC mode */
 
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
+	bic	lr, lr, #PSR_MODE_MASK	/* Keep F and T bits */
+	orr	lr, lr, #(PSR_MODE_SVC | PSR_I_BIT)
 	msr	cpsr_c, lr		/* Switch to SVC mode */
 
 	/* Create a context structure.  First set aside a stack frame
diff --git a/arch/arm/src/dm320/dm320_irq.c b/arch/arm/src/dm320/dm320_irq.c
index 176f5bd4f2..08d9447d45 100644
--- a/arch/arm/src/dm320/dm320_irq.c
+++ b/arch/arm/src/dm320/dm320_irq.c
@@ -107,7 +107,7 @@ void up_irqinitialize(void)
   /* And finally, enable interrupts */
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
-  up_irq_restore(SVC_MODE | PSR_F_BIT);
+  up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
 #endif
 }
 
diff --git a/arch/arm/src/dm320/dm320_restart.S b/arch/arm/src/dm320/dm320_restart.S
index 9f0bab147a..6e2d1e0164 100644
--- a/arch/arm/src/dm320/dm320_restart.S
+++ b/arch/arm/src/dm320/dm320_restart.S
@@ -53,7 +53,7 @@
 up_restart:
 	/* Make sure that we are in SVC mode with all IRQs disabled */
 
-	mov	r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT)
+	mov	r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
 	msr	cpsr_c, r0
 
 	/* Create identity mapping for first MB section to support
diff --git a/arch/arm/src/imx1/imx_irq.c b/arch/arm/src/imx1/imx_irq.c
index 4784d40daf..2274aee5f4 100644
--- a/arch/arm/src/imx1/imx_irq.c
+++ b/arch/arm/src/imx1/imx_irq.c
@@ -90,7 +90,7 @@ void up_irqinitialize(void)
 
   /* And finally, enable interrupts */
 
-  up_irq_restore(SVC_MODE | PSR_F_BIT);
+  up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
 #endif
 }
 
diff --git a/arch/arm/src/lpc214x/lpc214x_head.S b/arch/arm/src/lpc214x/lpc214x_head.S
index 45e9cb6ac3..637e7c52b6 100644
--- a/arch/arm/src/lpc214x/lpc214x_head.S
+++ b/arch/arm/src/lpc214x/lpc214x_head.S
@@ -495,7 +495,7 @@ _vector_table:
 __start:
 	/* Setup the initial processor mode */
 
-	mov	r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+	mov	r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
 	msr	cpsr, r0
 
 	/* Set up external memory mode (if so selected) */
diff --git a/arch/arm/src/lpc214x/lpc214x_irq.c b/arch/arm/src/lpc214x/lpc214x_irq.c
index 14978fc163..e702d41b3d 100644
--- a/arch/arm/src/lpc214x/lpc214x_irq.c
+++ b/arch/arm/src/lpc214x/lpc214x_irq.c
@@ -102,7 +102,7 @@ void up_irqinitialize(void)
   /* And finally, enable interrupts */
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
-  up_irq_restore(SVC_MODE | PSR_F_BIT);
+  up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
 #endif
 }
 
diff --git a/arch/arm/src/lpc2378/lpc23xx_head.S b/arch/arm/src/lpc2378/lpc23xx_head.S
index c81ba3b57a..47e02d7593 100644
--- a/arch/arm/src/lpc2378/lpc23xx_head.S
+++ b/arch/arm/src/lpc2378/lpc23xx_head.S
@@ -144,7 +144,7 @@ __start:
 
 	/* First, setup initial processor mode */
 
-	mov	r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+	mov	r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
 	msr	cpsr, r0
 
 /* Configure the uart so that we can get debug output as soon
diff --git a/arch/arm/src/lpc2378/lpc23xx_irq.c b/arch/arm/src/lpc2378/lpc23xx_irq.c
index 4c42856798..05500baec9 100644
--- a/arch/arm/src/lpc2378/lpc23xx_irq.c
+++ b/arch/arm/src/lpc2378/lpc23xx_irq.c
@@ -119,7 +119,7 @@ void up_irqinitialize(void)
   /* Enable global ARM interrupts */
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
-  up_irq_restore(SVC_MODE | PSR_F_BIT);
+  up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
 #endif
 }
 
diff --git a/arch/arm/src/lpc31xx/lpc31_irq.c b/arch/arm/src/lpc31xx/lpc31_irq.c
index 4215960a5a..9418060f73 100644
--- a/arch/arm/src/lpc31xx/lpc31_irq.c
+++ b/arch/arm/src/lpc31xx/lpc31_irq.c
@@ -115,7 +115,7 @@ void up_irqinitialize(void)
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
   /* And finally, enable interrupts */
 
-  up_irq_restore(SVC_MODE | PSR_F_BIT);
+  up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
 #endif
 }
 
diff --git a/arch/arm/src/moxart/moxart_irq.c b/arch/arm/src/moxart/moxart_irq.c
index 8ce7747b41..cdc9fb334a 100644
--- a/arch/arm/src/moxart/moxart_irq.c
+++ b/arch/arm/src/moxart/moxart_irq.c
@@ -154,7 +154,7 @@ void up_irqinitialize(void)
           getreg32(0x98800020));
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
-  up_irq_restore(SVC_MODE | PSR_F_BIT);
+  up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
 #endif
 }
 
diff --git a/arch/arm/src/str71x/str71x_head.S b/arch/arm/src/str71x/str71x_head.S
index 6e94ffdf28..0e92efb68b 100644
--- a/arch/arm/src/str71x/str71x_head.S
+++ b/arch/arm/src/str71x/str71x_head.S
@@ -470,7 +470,7 @@ __flashstart:
 
 	/* Setup the initial processor mode */
 
-	mov		r0, #(SVC_MODE | PSR_I_BIT | PSR_F_BIT )
+	mov		r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT )
 	msr		cpsr, r0
 
 	/* Initialize the external memory interface (EMI) */
diff --git a/arch/arm/src/str71x/str71x_irq.c b/arch/arm/src/str71x/str71x_irq.c
index 3ce1359935..8fee73dc87 100644
--- a/arch/arm/src/str71x/str71x_irq.c
+++ b/arch/arm/src/str71x/str71x_irq.c
@@ -89,7 +89,7 @@ void up_irqinitialize(void)
   /* Enable global ARM interrupts */
 
 #ifndef CONFIG_SUPPRESS_INTERRUPTS
-  up_irq_restore(SVC_MODE | PSR_F_BIT);
+  up_irq_restore(PSR_MODE_SVC | PSR_F_BIT);
 #endif
 }