diff --git a/arch/arm/src/sama5/chip/sam_can.h b/arch/arm/src/sama5/chip/sam_can.h index d518d0c73d..8efbbd51c6 100644 --- a/arch/arm/src/sama5/chip/sam_can.h +++ b/arch/arm/src/sama5/chip/sam_can.h @@ -265,7 +265,7 @@ #define CAN_MMR_MTIMEMARK_SHIFT (0) /* Bits 0-15: Mailbox Timemark */ #define CAN_MMR_MTIMEMARK_MASK (0xffff << CAN_MMR_MTIMEMARK_SHIFT) # define CAN_MMR_MTIMEMARK(n) ((uint32_t)(n) << 19) -#define CAN_MMR_PRIOR_SHIFT (16) /* Bits 16-nn: Mailbox Priority */ +#define CAN_MMR_PRIOR_SHIFT (16) /* Bits 16-19: Mailbox Priority */ #define CAN_MMR_PRIOR_MASK (15 << CAN_MMR_PRIOR_SHIFT) # define CAN_MMR_PRIOR(n) ((uint32_t)(n) << CAN_MMR_PRIOR_SHIFT) #define CAN_MMR_MOT_SHIFT (24) /* Bits 24-26: Mailbox Object Type */ diff --git a/arch/arm/src/sama5/chip/sam_hsmc.h b/arch/arm/src/sama5/chip/sam_hsmc.h index cec7027ffd..20b06294ca 100644 --- a/arch/arm/src/sama5/chip/sam_hsmc.h +++ b/arch/arm/src/sama5/chip/sam_hsmc.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/src/sama5/chip/sam_hsmc.h * - * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -176,7 +176,7 @@ #define SAM_HSMC_KEY1_OFFSET 0x06a4 /* HSMC OCMS KEY1 Register */ #define SAM_HSMC_KEY2_OFFSET 0x06a8 /* HSMC OCMS KEY2 Register */ /* 0x06ac-0x06e0 Reserved */ -#define SAM_HSMC_WPCR_OFFSET 0x06e4 /* HSMC Write Protection Control Register */ +#define SAM_HSMC_WPMR_OFFSET 0x06e4 /* HSMC Write Protection Mode Register */ #define SAM_HSMC_WPSR_OFFSET 0x06e8 /* HSMC Write Protection Status Register */ /* 0x06fc Reserved */ @@ -293,7 +293,7 @@ #define SAM_HSMC_OCMS (SAM_HSMC_VBASE+SAM_HSMC_OCMS_OFFSET) #define SAM_HSMC_KEY1 (SAM_HSMC_VBASE+SAM_HSMC_KEY1_OFFSET) #define SAM_HSMC_KEY2 (SAM_HSMC_VBASE+SAM_HSMC_KEY2_OFFSET) -#define SAM_HSMC_WPCR (SAM_HSMC_VBASE+SAM_HSMC_WPCR_OFFSET) +#define SAM_HSMC_WPMR (SAM_HSMC_VBASE+SAM_HSMC_WPMR_OFFSET) #define SAM_HSMC_WPSR (SAM_HSMC_VBASE+SAM_HSMC_WPSR_OFFSET) /* SMC Register Bit Definitions *****************************************************/ @@ -428,7 +428,9 @@ /* PMECC Interrupt Status Register */ -#define HSMC_PMECCISR_ERRIS(n) (1 << (n)) /* Bits 0-7: Error Interrupt Status */ +#define HSMC_PMECCISR_ERRIS_SHIFT (0) /* Bits 0-7: Error Interrupt Status */ +#define HSMC_PMECCISR_ERRIS_MASK (0xff << HSMC_PMECCISR_ERRIS_SHIFT) +# define HSMC_PMECCISR_ERRIS(n) (1 << (n)) /* Bits n: Error on sector n */ /* PMECC Redundancy x Register (32-bit ECC value) */ @@ -569,12 +571,12 @@ /* HSMC OCMS KEY1 Register (32-bits of 64-bit key value) */ /* HSMC OCMS KEY2 Register (32-bits of 64-bit key value) */ -/* HSMC Write Protection Control Register */ +/* HSMC Write Protection Mode Register */ -#define HSMC_WPCR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ -#define HSMC_WPCR_WPKEY_SHIFT (8) /* Bit 8-31: Write Protection KEY password */ -#define HSMC_WPCR_WPKEY_MASK (0xffffff << HSMC_WPCR_WPKEY_SHIFT) -# define HSMC_WPCR_WPKEY (0x534d43 << HSMC_WPCR_WPKEY_SHIFT) +#define HSMC_WPMR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */ +#define HSMC_WPMR_WPKEY_SHIFT (8) /* Bit 8-31: Write Protection KEY password */ +#define HSMC_WPMR_WPKEY_MASK (0x00ffffff << HSMC_WPMR_WPKEY_SHIFT) +# define HSMC_WPMR_WPKEY (0x00534d43 << HSMC_WPMR_WPKEY_SHIFT) /* HSMC Write Protection Status Register */ @@ -585,6 +587,8 @@ /* NFC Command/Data Registers *******************************************************/ +/* NFC Command and Status Registers */ + #define NFCADDR_CMD_CMD1_SHIFT (2) /* Bits 2-9: Command Register Value for Cycle 1 */ #define NFCADDR_CMD_CMD1_MASK (0xff << NFCADDR_CMD_CMD1_SHIFT) # define NFCADDR_CMD_CMD1(n) ((uint32_t)(n) << NFCADDR_CMD_CMD1_SHIFT) @@ -616,7 +620,9 @@ #define NFCADDR_CMD_DATADIS (0 << 25) /* Bit 25: 0=NFC Data disable */ #define NFCADDR_CMD_NFCRD (0 << 26) /* Bit 26: 0=NFC Read Enable */ #define NFCADDR_CMD_NFCWR (1 << 26) /* Bit 26: 1=NFC Write Enable */ -#define NFCADDR_CMD_NFCCMD (1 << 27) /* Bit 27: 1=NFC Command Enable */ +#define NFCADDR_CMD_NFCCMD (1 << 27) /* Bit 27: 1=NFC Command Enable (status only) */ + +/* NFC Data Address */ #define NFCDATA_ADDT_CYCLE1_SHIFT (0) /* Bits 0-7: NAND Flash Array Address Cycle 1 */ #define NFCDATA_ADDT_CYCLE1_MASK (0xff << NFCDATA_ADDT_CYCLE1_SHIFT) @@ -624,8 +630,8 @@ #define NFCDATA_ADDT_CYCLE2_SHIFT (8) /* Bits 8-15: NAND Flash Array Address Cycle 2 */ #define NFCDATA_ADDT_CYCLE2_MASK (0xff << NFCDATA_ADDT_CYCLE2_SHIFT) # define NFCDATA_ADDT_CYCLE2(n) ((uint32_t)(n) << NFCDATA_ADDT_CYCLE2_SHIFT) -#define NFCDATA_ADDT_CYCLE3_SHIFT (nn) /* Bits 16-23: NAND Flash Array Address Cycle 3 */ -#define NFCDATA_ADDT_CYCLE3_MASK (16 << NFCDATA_ADDT_CYCLE3_SHIFT) +#define NFCDATA_ADDT_CYCLE3_SHIFT (16) /* Bits 16-23: NAND Flash Array Address Cycle 3 */ +#define NFCDATA_ADDT_CYCLE3_MASK (0xff << NFCDATA_ADDT_CYCLE3_SHIFT) # define NFCDATA_ADDT_CYCLE3(n) ((uint32_t)(n) << NFCDATA_ADDT_CYCLE3_SHIFT) #define NFCDATA_ADDT_CYCLE4_SHIFT (24) /* Bits 24-31: NAND Flash Array Address Cycle 4 */ #define NFCDATA_ADDT_CYCLE4_MASK (0xff << NFCDATA_ADDT_CYCLE4_SHIFT) diff --git a/arch/arm/src/sama5/chip/sam_isi.h b/arch/arm/src/sama5/chip/sam_isi.h index bfc9443a1b..dd6779f07a 100644 --- a/arch/arm/src/sama5/chip/sam_isi.h +++ b/arch/arm/src/sama5/chip/sam_isi.h @@ -126,7 +126,7 @@ #define ISI_CFG1_SLD_SHIFT (16) /* Bits 16-23: Start of Line Delay */ #define ISI_CFG1_SLD_MASK (0xff << ISI_CFG1_SLD_SHIFT) # define ISI_CFG1_SLD(n) ((uint32_t)(n) << ISI_CFG1_SLD_SHIFT) -#define ISI_CFG1_SFD_SHIFT (nn) /* Bits nn-nn: Start of Frame Delay */ +#define ISI_CFG1_SFD_SHIFT (24) /* Bits 24-31: Start of Frame Delay */ #define ISI_CFG1_SFD_MASK (0xff << ISI_CFG1_SLD_SHIFT) # define ISI_CFG1_SFD(n) ((uint32_t)(n) << ISI_CFG1_SLD_SHIFT) @@ -299,10 +299,10 @@ /* Write Protection Control Register */ -#define ISI_WPCR_WP_EN (1 << 0) /* Bit 0: Write Protection Enable */ -#define ISI_WPCR_WP_KEY_SHIFT (8) /* Bits nn-nn: Write Protection KEY Password */ -#define ISI_WPCR_WP_KEY_MASK (0xffffff << ISI_WPCR_WP_KEY_SHIFT) -# define ISI_WPCR_WP_KEY (0x495349 << ISI_WPCR_WP_KEY_SHIFT) /* (ASCII code for "ISI") */ +#define ISI_WPCR_WPEN (1 << 0) /* Bit 0: Write Protection Enable */ +#define ISI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protection KEY Password */ +#define ISI_WPCR_WPKEY_MASK (000xffffff << ISI_WPCR_WPKEY_SHIFT) +# define ISI_WPCR_WPKEY (0x00495349 << ISI_WPCR_WPKEY_SHIFT) /* (ASCII code for "ISI") */ /* Write Protection Status Register */ diff --git a/arch/arm/src/sama5/chip/sam_lcdc.h b/arch/arm/src/sama5/chip/sam_lcdc.h index 1b9495afbf..ba7ff55d78 100644 --- a/arch/arm/src/sama5/chip/sam_lcdc.h +++ b/arch/arm/src/sama5/chip/sam_lcdc.h @@ -1288,7 +1288,7 @@ #define LCDC_HEOCFG17_XPHI0COEFF2_SHIFT (16) /* Bits 16-23: Horizontal Coefficient for phase 0 tap 2 */ #define LCDC_HEOCFG17_XPHI0COEFF2_MASK (0xff << LCDC_HEOCFG17_XPHI0COEFF2_SHIFT) # define LCDC_HEOCFG17_XPHI0COEFF2(n) ((uint32_t)(n) << LCDC_HEOCFG17_XPHI0COEFF2_SHIFT) -#define LCDC_HEOCFG17_XPHI0COEFF3_SHIFT (24) /* Bits 2431nn: Horizontal Coefficient for phase 0 tap 3 */ +#define LCDC_HEOCFG17_XPHI0COEFF3_SHIFT (24) /* Bits 24-31: Horizontal Coefficient for phase 0 tap 3 */ #define LCDC_HEOCFG17_XPHI0COEFF3_MASK (0xff << LCDC_HEOCFG17_XPHI0COEFF3_SHIFT) # define LCDC_HEOCFG17_XPHI0COEFF3(n) ((uint32_t)(n) << LCDC_HEOCFG17_XPHI0COEFF3_SHIFT) @@ -1309,7 +1309,7 @@ #define LCDC_HEOCFG19_XPHI1COEFF2_SHIFT (16) /* Bits 16-23: Horizontal Coefficient for phase 1 tap 2 */ #define LCDC_HEOCFG19_XPHI1COEFF2_MASK (0xff << LCDC_HEOCFG19_XPHI1COEFF2_SHIFT) # define LCDC_HEOCFG19_XPHI1COEFF2(n) ((uint32_t)(n) << LCDC_HEOCFG19_XPHI1COEFF2_SHIFT) -#define LCDC_HEOCFG19_XPHI1COEFF3_SHIFT (24) /* Bits 2431nn: Horizontal Coefficient for phase 1 tap 3 */ +#define LCDC_HEOCFG19_XPHI1COEFF3_SHIFT (24) /* Bits 24-31: Horizontal Coefficient for phase 1 tap 3 */ #define LCDC_HEOCFG19_XPHI1COEFF3_MASK (0xff << LCDC_HEOCFG19_XPHI1COEFF3_SHIFT) # define LCDC_HEOCFG19_XPHI1COEFF3(n) ((uint32_t)(n) << LCDC_HEOCFG19_XPHI1COEFF3_SHIFT) @@ -1330,7 +1330,7 @@ #define LCDC_HEOCFG21_XPHI2COEFF2_SHIFT (16) /* Bits 16-23: Horizontal Coefficient for phase 2 tap 2 */ #define LCDC_HEOCFG21_XPHI2COEFF2_MASK (0xff << LCDC_HEOCFG21_XPHI2COEFF2_SHIFT) # define LCDC_HEOCFG21_XPHI2COEFF2(n) ((uint32_t)(n) << LCDC_HEOCFG21_XPHI2COEFF2_SHIFT) -#define LCDC_HEOCFG21_XPHI2COEFF3_SHIFT (24) /* Bits 2431nn: Horizontal Coefficient for phase 2 tap 3 */ +#define LCDC_HEOCFG21_XPHI2COEFF3_SHIFT (24) /* Bits 24-31: Horizontal Coefficient for phase 2 tap 3 */ #define LCDC_HEOCFG21_XPHI2COEFF3_MASK (0xff << LCDC_HEOCFG21_XPHI2COEFF3_SHIFT) # define LCDC_HEOCFG21_XPHI2COEFF3(n) ((uint32_t)(n) << LCDC_HEOCFG21_XPHI2COEFF3_SHIFT) @@ -1351,7 +1351,7 @@ #define LCDC_HEOCFG23_XPHI3COEFF2_SHIFT (16) /* Bits 16-23: Horizontal Coefficient for phase 3 tap 2 */ #define LCDC_HEOCFG23_XPHI3COEFF2_MASK (0xff << LCDC_HEOCFG23_XPHI3COEFF2_SHIFT) # define LCDC_HEOCFG23_XPHI3COEFF2(n) ((uint32_t)(n) << LCDC_HEOCFG23_XPHI3COEFF2_SHIFT) -#define LCDC_HEOCFG23_XPHI3COEFF3_SHIFT (24) /* Bits 2431nn: Horizontal Coefficient for phase 3 tap 3 */ +#define LCDC_HEOCFG23_XPHI3COEFF3_SHIFT (24) /* Bits 24-31: Horizontal Coefficient for phase 3 tap 3 */ #define LCDC_HEOCFG23_XPHI3COEFF3_MASK (0xff << LCDC_HEOCFG23_XPHI3COEFF3_SHIFT) # define LCDC_HEOCFG23_XPHI3COEFF3(n) ((uint32_t)(n) << LCDC_HEOCFG23_XPHI3COEFF3_SHIFT) @@ -1372,7 +1372,7 @@ #define LCDC_HEOCFG25_XPHI4COEFF2_SHIFT (16) /* Bits 16-25: Horizontal Coefficient for phase 4 tap 2 */ #define LCDC_HEOCFG25_XPHI4COEFF2_MASK (0xff << LCDC_HEOCFG25_XPHI4COEFF2_SHIFT) # define LCDC_HEOCFG25_XPHI4COEFF2(n) ((uint32_t)(n) << LCDC_HEOCFG25_XPHI4COEFF2_SHIFT) -#define LCDC_HEOCFG25_XPHI4COEFF3_SHIFT (24) /* Bits 2431nn: Horizontal Coefficient for phase 4 tap 3 */ +#define LCDC_HEOCFG25_XPHI4COEFF3_SHIFT (24) /* Bits 24-31: Horizontal Coefficient for phase 4 tap 3 */ #define LCDC_HEOCFG25_XPHI4COEFF3_MASK (0xff << LCDC_HEOCFG25_XPHI4COEFF3_SHIFT) # define LCDC_HEOCFG25_XPHI4COEFF3(n) ((uint32_t)(n) << LCDC_HEOCFG25_XPHI4COEFF3_SHIFT) @@ -1393,7 +1393,7 @@ #define LCDC_HEOCFG27_XPHI5COEFF2_SHIFT (16) /* Bits 16-25: Horizontal Coefficient for phase 5 tap 2 */ #define LCDC_HEOCFG27_XPHI5COEFF2_MASK (0xff << LCDC_HEOCFG27_XPHI5COEFF2_SHIFT) # define LCDC_HEOCFG27_XPHI5COEFF2(n) ((uint32_t)(n) << LCDC_HEOCFG27_XPHI5COEFF2_SHIFT) -#define LCDC_HEOCFG27_XPHI5COEFF3_SHIFT (24) /* Bits 2431nn: Horizontal Coefficient for phase 5 tap 3 */ +#define LCDC_HEOCFG27_XPHI5COEFF3_SHIFT (24) /* Bits 24-31: Horizontal Coefficient for phase 5 tap 3 */ #define LCDC_HEOCFG27_XPHI5COEFF3_MASK (0xff << LCDC_HEOCFG27_XPHI5COEFF3_SHIFT) # define LCDC_HEOCFG27_XPHI5COEFF3(n) ((uint32_t)(n) << LCDC_HEOCFG27_XPHI5COEFF3_SHIFT) @@ -1414,7 +1414,7 @@ #define LCDC_HEOCFG29_XPHI6COEFF2_SHIFT (16) /* Bits 16-25: Horizontal Coefficient for phase 6 tap 2 */ #define LCDC_HEOCFG29_XPHI6COEFF2_MASK (0xff << LCDC_HEOCFG29_XPHI6COEFF2_SHIFT) # define LCDC_HEOCFG29_XPHI6COEFF2(n) ((uint32_t)(n) << LCDC_HEOCFG29_XPHI6COEFF2_SHIFT) -#define LCDC_HEOCFG29_XPHI6COEFF3_SHIFT (24) /* Bits 2431nn: Horizontal Coefficient for phase 6 tap 3 */ +#define LCDC_HEOCFG29_XPHI6COEFF3_SHIFT (24) /* Bits 24-31: Horizontal Coefficient for phase 6 tap 3 */ #define LCDC_HEOCFG29_XPHI6COEFF3_MASK (0xff << LCDC_HEOCFG29_XPHI6COEFF3_SHIFT) # define LCDC_HEOCFG29_XPHI6COEFF3(n) ((uint32_t)(n) << LCDC_HEOCFG29_XPHI6COEFF3_SHIFT) @@ -1435,7 +1435,7 @@ #define LCDC_HEOCFG31_XPHI7COEFF2_SHIFT (16) /* Bits 16-25: Horizontal Coefficient for phase 7 tap 2 */ #define LCDC_HEOCFG31_XPHI7COEFF2_MASK (0xff << LCDC_HEOCFG31_XPHI7COEFF2_SHIFT) # define LCDC_HEOCFG31_XPHI7COEFF2(n) ((uint32_t)(n) << LCDC_HEOCFG31_XPHI7COEFF2_SHIFT) -#define LCDC_HEOCFG31_XPHI7COEFF3_SHIFT (24) /* Bits 2431nn: Horizontal Coefficient for phase 7 tap 3 */ +#define LCDC_HEOCFG31_XPHI7COEFF3_SHIFT (24) /* Bits 24-31: Horizontal Coefficient for phase 7 tap 3 */ #define LCDC_HEOCFG31_XPHI7COEFF3_MASK (0xff << LCDC_HEOCFG31_XPHI7COEFF3_SHIFT) # define LCDC_HEOCFG31_XPHI7COEFF3(n) ((uint32_t)(n) << LCDC_HEOCFG31_XPHI7COEFF3_SHIFT)