page tables must be aligned
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2900 42af7a65-404d-4744-a932-0658087f49c3
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@ -69,63 +69,73 @@
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#if CONFIG_PAGING_PAGESIZE == 1024
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#if CONFIG_PAGING_PAGESIZE == 1024
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/* Base of the L2 page table (aligned to 4Kb byte boundaries) */
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# define PGTABLE_L2_BASE_PADDR PGTABLE_L2_FINE_PBASE
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# define PGTABLE_L2_BASE_VADDR PGTABLE_L2_FINE_VBASE
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/* Number of pages in an L2 table per L1 entry */
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/* Number of pages in an L2 table per L1 entry */
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# define PTE_NPAGES PTE_TINY_NPAGES
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# define PTE_NPAGES PTE_TINY_NPAGES
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/* Mask to get the page table physical address from an L1 entry */
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/* Mask to get the page table physical address from an L1 entry */
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# define PG_L1_PADDRMASK PMD_FINE_TEX_MASK
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# define PG_L1_PADDRMASK PMD_FINE_TEX_MASK
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/* MMU Flags for each memory region */
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/* MMU Flags for each memory region */
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW)
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# define MMU_L2_VECTRWFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW)
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# define MMU_L2_VECTRWFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW)
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# define MMU_L2_VECTROFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L2_VECTROFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRO|PTE_CACHEABLE)
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#elif CONFIG_PAGING_PAGESIZE == 4096
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#elif CONFIG_PAGING_PAGESIZE == 4096
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/* Base of the L2 page table (aligned to 1Kb byte boundaries) */
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# define PGTABLE_L2_BASE_PADDR PGTABLE_L2_COARSE_PBASE
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# define PGTABLE_L2_BASE_VADDR PGTABLE_L2_COARSE_VBASE
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/* Number of pages in an L2 table per L1 entry */
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/* Number of pages in an L2 table per L1 entry */
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# define PTE_NPAGES PTE_SMALL_NPAGES
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# define PTE_NPAGES PTE_SMALL_NPAGES
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/* Mask to get the page table physical address from an L1 entry */
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/* Mask to get the page table physical address from an L1 entry */
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# define PG_L1_PADDRMASK PMD_COARSE_TEX_MASK
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# define PG_L1_PADDRMASK PMD_COARSE_TEX_MASK
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/* MMU Flags for each memory region. */
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/* MMU Flags for each memory region. */
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
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# define MMU_L2_VECTRWFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
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# define MMU_L2_VECTRWFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
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# define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
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#else
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#else
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# error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
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# error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
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#endif
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#endif
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#define PT_SIZE (4*PTE_NPAGES)
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#define PT_SIZE (4*PTE_NPAGES)
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/* We position the locked region PTEs at the beginning of L2 page
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/* We position the locked region PTEs at the beginning of L2 page
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* table.
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* table.
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*/
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*/
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#define PG_L1_LOCKED_PADDR (PGTABLE_BASE_PADDR + ((PG_LOCKED_VBASE >> 20) << 2))
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#define PG_L1_LOCKED_PADDR (PGTABLE_BASE_PADDR + ((PG_LOCKED_VBASE >> 20) << 2))
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#define PG_L1_LOCKED_VADDR (PGTABLE_BASE_VADDR + ((PG_LOCKED_VBASE >> 20) << 2))
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#define PG_L1_LOCKED_VADDR (PGTABLE_BASE_VADDR + ((PG_LOCKED_VBASE >> 20) << 2))
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#define PG_L2_LOCKED_PADDR PGTABLE_L2_BASE_PADDR
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#define PG_L2_LOCKED_PADDR PGTABLE_L2_BASE_PADDR
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#define PG_L2_LOCKED_VADDR PGTABLE_L2_BASE_VADDR
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#define PG_L2_LOCKED_VADDR PGTABLE_L2_BASE_VADDR
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#define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED)
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#define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED)
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/* We position the paged region PTEs immediately after the locked
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/* We position the paged region PTEs immediately after the locked
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* region PTEs. NOTE that the size of the paged regions is much
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* region PTEs. NOTE that the size of the paged regions is much
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@ -133,39 +143,39 @@
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* core of what the On-Demanding Paging feature provides.
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* core of what the On-Demanding Paging feature provides.
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*/
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*/
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#define PG_L1_PAGED_PADDR (PGTABLE_BASE_PADDR + ((PG_PAGED_VBASE >> 20) << 2))
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#define PG_L1_PAGED_PADDR (PGTABLE_BASE_PADDR + ((PG_PAGED_VBASE >> 20) << 2))
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#define PG_L1_PAGED_VADDR (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2))
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#define PG_L1_PAGED_VADDR (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2))
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#define PG_L2_PAGED_PADDR (PGTABLE_L2_BASE_PADDR + PG_L2_LOCKED_SIZE)
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#define PG_L2_PAGED_PADDR (PGTABLE_L2_BASE_PADDR + PG_L2_LOCKED_SIZE)
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#define PG_L2_PAGED_VADDR (PGTABLE_L2_BASE_VADDR + PG_L2_LOCKED_SIZE)
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#define PG_L2_PAGED_VADDR (PGTABLE_L2_BASE_VADDR + PG_L2_LOCKED_SIZE)
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#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NVPAGED)
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#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NVPAGED)
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/* This describes the overall text region */
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/* This describes the overall text region */
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#define PG_L1_TEXT_PADDR PG_L1_LOCKED_PADDR
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#define PG_L1_TEXT_PADDR PG_L1_LOCKED_PADDR
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#define PG_L1_TEXT_VADDR PG_L1_LOCKED_VADDR
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#define PG_L1_TEXT_VADDR PG_L1_LOCKED_VADDR
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#define PG_L2_TEXT_PADDR PG_L2_LOCKED_PADDR
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#define PG_L2_TEXT_PADDR PG_L2_LOCKED_PADDR
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#define PG_L2_TEXT_VADDR PG_L2_LOCKED_VADDR
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#define PG_L2_TEXT_VADDR PG_L2_LOCKED_VADDR
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#define PG_L2_TEXT_SIZE (PG_L2_LOCKED_SIZE + PG_L2_PAGED_SIZE)
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#define PG_L2_TEXT_SIZE (PG_L2_LOCKED_SIZE + PG_L2_PAGED_SIZE)
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/* We position the data section PTEs just after the text region PTE's */
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/* We position the data section PTEs just after the text region PTE's */
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#define PG_L1_DATA_PADDR (PGTABLE_BASE_PADDR + ((PG_DATA_VBASE >> 20) << 2))
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#define PG_L1_DATA_PADDR (PGTABLE_BASE_PADDR + ((PG_DATA_VBASE >> 20) << 2))
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#define PG_L1_DATA_VADDR (PGTABLE_BASE_VADDR + ((PG_DATA_VBASE >> 20) << 2))
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#define PG_L1_DATA_VADDR (PGTABLE_BASE_VADDR + ((PG_DATA_VBASE >> 20) << 2))
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#define PG_L2_DATA_PADDR (PGTABLE_L2_BASE_PADDR + PG_L2_TEXT_SIZE)
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#define PG_L2_DATA_PADDR (PGTABLE_L2_BASE_PADDR + PG_L2_TEXT_SIZE)
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#define PG_L2_DATA_VADDR (PGTABLE_L2_BASE_VADDR + PG_L2_TEXT_SIZE)
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#define PG_L2_DATA_VADDR (PGTABLE_L2_BASE_VADDR + PG_L2_TEXT_SIZE)
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#define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES)
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#define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES)
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/* Page Table Info: The number of pages in the in the page table
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/* Page Table Info: The number of pages in the in the page table
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* (PG_PGTABLE_NPAGES). We position the pagetable PTEs just after
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* (PG_PGTABLE_NPAGES). We position the pagetable PTEs just after
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* the data section PTEs.
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* the data section PTEs.
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*/
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*/
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#define PG_PGTABLE_NPAGES (PGTABLE_SIZE >> PAGESHIFT)
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#define PG_PGTABLE_NPAGES (PGTABLE_SIZE >> PAGESHIFT)
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#define PG_L1_PGTABLE_PADDR (PGTABLE_BASE_PADDR + ((PGTABLE_BASE_VADDR >> 20) << 2))
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#define PG_L1_PGTABLE_PADDR (PGTABLE_BASE_PADDR + ((PGTABLE_BASE_VADDR >> 20) << 2))
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#define PG_L1_PGTABLE_VADDR (PGTABLE_BASE_VADDR + ((PGTABLE_BASE_VADDR >> 20) << 2))
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#define PG_L1_PGTABLE_VADDR (PGTABLE_BASE_VADDR + ((PGTABLE_BASE_VADDR >> 20) << 2))
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#define PG_L2_PGTABLE_PADDR (PG_L2_DATA_PADDR + PG_L2_DATA_SIZE)
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#define PG_L2_PGTABLE_PADDR (PG_L2_DATA_PADDR + PG_L2_DATA_SIZE)
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#define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE)
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#define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE)
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#define PG_L2_PGTABLE_SIZE (4*PG_DATA_NPAGES)
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#define PG_L2_PGTABLE_SIZE (4*PG_DATA_NPAGES)
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/* Vector mapping. One page is required to map the vector table. The
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/* Vector mapping. One page is required to map the vector table. The
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* vector table could lie in at virtual address zero (or at the start
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* vector table could lie in at virtual address zero (or at the start
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@ -197,18 +207,18 @@
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/* Case 1: The configuration tells us everything */
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/* Case 1: The configuration tells us everything */
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#if defined(CONFIG_PAGING_VECPPAGE)
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#if defined(CONFIG_PAGING_VECPPAGE)
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# define PG_VECT_PBASE CONFIG_PAGING_VECPPAGE
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# define PG_VECT_PBASE CONFIG_PAGING_VECPPAGE
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# define PG_L2_VECT_PADDR CONFIG_PAGING_VECL2PADDR
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# define PG_L2_VECT_PADDR CONFIG_PAGING_VECL2PADDR
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# define PG_L2_VECT_VADDR CONFIG_PAGING_VECL2VADDR
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# define PG_L2_VECT_VADDR CONFIG_PAGING_VECL2VADDR
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/* Case 2: Vectors are in low memory and the locked text region starts at
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/* Case 2: Vectors are in low memory and the locked text region starts at
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* the begin of SRAM (which will be aliased to address 0x00000000)
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* the begin of SRAM (which will be aliased to address 0x00000000)
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*/
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*/
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#elif defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_PAGING_LOCKED_PBASE)
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#elif defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_PAGING_LOCKED_PBASE)
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# define PG_VECT_PBASE PG_LOCKED_PBASE
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# define PG_VECT_PBASE PG_LOCKED_PBASE
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# define PG_L2_VECT_PADDR PG_L2_LOCKED_PADDR
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# define PG_L2_VECT_PADDR PG_L2_LOCKED_PADDR
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# define PG_L2_VECT_VADDR PG_L2_LOCKED_VADDR
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# define PG_L2_VECT_VADDR PG_L2_LOCKED_VADDR
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/* Case 3: High vectors or the locked region is not at the beginning or SRAM */
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/* Case 3: High vectors or the locked region is not at the beginning or SRAM */
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/* This is the total number of pages used in the text/data mapping: */
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/* This is the total number of pages used in the text/data mapping: */
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#define PG_TOTAL_NPPAGES (PG_TEXT_NPPAGES + PG_DATA_PAGES + PG_PGTABLE_NPAGES)
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#define PG_TOTAL_NPPAGES (PG_TEXT_NPPAGES + PG_DATA_PAGES + PG_PGTABLE_NPAGES)
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#define PG_TOTAL_NVPAGES (PG_TEXT_NVPAGES + PG_DATA_PAGES + PG_PGTABLE_NPAGES)
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#define PG_TOTAL_NVPAGES (PG_TEXT_NVPAGES + PG_DATA_PAGES + PG_PGTABLE_NPAGES)
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#if PG_TOTAL_NPPAGES >PG_RAM_PAGES
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#if PG_TOTAL_NPPAGES >PG_RAM_PAGES
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# error "Total pages required exceeds RAM size"
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# error "Total pages required exceeds RAM size"
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#endif
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#endif
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* written.
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* written.
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*/
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*/
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#define PG_POOL_VA2L1OFFSET(va) (((va) >> 20) << 2)
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#define PG_POOL_VA2L1OFFSET(va) (((va) >> 20) << 2)
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#define PG_POOL_VA2L1VADDR(va) (PGTABLE_BASE_VADDR + PG_POOL_VA2L1OFFSET(va))
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#define PG_POOL_VA2L1VADDR(va) (PGTABLE_BASE_VADDR + PG_POOL_VA2L1OFFSET(va))
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#define PG_POOL_L12PPTABLE(L1) ((L1) & PG_L1_PADDRMASK)
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#define PG_POOL_L12PPTABLE(L1) ((L1) & PG_L1_PADDRMASK)
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#define PG_POOL_L12VPTABLE(L1) (PG_POOL_L12PPTABLE(L1) - PGTABLE_BASE_PADDR + PGTABLE_BASE_VADDR)
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#define PG_POOL_L12VPTABLE(L1) (PG_POOL_L12PPTABLE(L1) - PGTABLE_BASE_PADDR + PGTABLE_BASE_VADDR)
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#define PG_POOL_L1VBASE (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2))
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#define PG_POOL_L1VBASE (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2))
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#define PG_POOL_L1VEND (PG_POOL_L1VBASE + (CONFIG_PAGING_NVPAGED << 2))
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#define PG_POOL_L1VEND (PG_POOL_L1VBASE + (CONFIG_PAGING_NVPAGED << 2))
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#define PG_POOL_VA2L2NDX(va) (((va) - PG_PAGED_VBASE) >> PAGESHIFT)
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#define PG_POOL_VA2L2NDX(va) (((va) - PG_PAGED_VBASE) >> PAGESHIFT)
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#define PG_POOL_NDX2VA(ndx) (((ndx) << PAGESHIFT) + PG_PAGED_VBASE)
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#define PG_POOL_NDX2VA(ndx) (((ndx) << PAGESHIFT) + PG_PAGED_VBASE)
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#define PG_POOL_MAXL2NDX PG_POOL_VA2L2NDX(PG_PAGED_VEND)
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#define PG_POOL_MAXL2NDX PG_POOL_VA2L2NDX(PG_PAGED_VEND)
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#define PG_POOL_PGPADDR(ndx) (PG_PAGED_PBASE + ((ndx) << PAGESHIFT))
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#define PG_POOL_PGPADDR(ndx) (PG_PAGED_PBASE + ((ndx) << PAGESHIFT))
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#define PG_POOL_PGVADDR(ndx) (PG_PAGED_VBASE + ((ndx) << PAGESHIFT))
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#define PG_POOL_PGVADDR(ndx) (PG_PAGED_VBASE + ((ndx) << PAGESHIFT))
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#endif /* CONFIG_PAGING */
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#endif /* CONFIG_PAGING */
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while (vector_paddr < end_paddr)
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while (vector_paddr < end_paddr)
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{
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{
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up_setlevel2coarseentry(PGTABLE_L2_BASE_VADDR, vector_paddr, vector_vaddr,
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up_setlevel2coarseentry(PGTABLE_L2_COARSE_VBASE, vector_paddr, vector_vaddr,
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MMU_L2_VECTORFLAGS);
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MMU_L2_VECTORFLAGS);
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vector_paddr += 4096;
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vector_paddr += 4096;
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vector_vaddr += 4096;
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vector_vaddr += 4096;
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/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
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/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
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up_setlevel1entry(PGTABLE_L2_BASE_PADDR, DM320_VECTOR_VCOARSE, MMU_L1_VECTORFLAGS);
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up_setlevel1entry(PGTABLE_L2_COARSE_PBASE, DM320_VECTOR_VCOARSE, MMU_L1_VECTORFLAGS);
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}
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}
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/************************************************************************************
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/************************************************************************************
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#define PGTABLE_BASE_PADDR DM320_SDRAM_PADDR
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#define PGTABLE_BASE_PADDR DM320_SDRAM_PADDR
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#define PGTABLE_SDRAM_PADDR PGTABLE_BASE_PADDR
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#define PGTABLE_SDRAM_PADDR PGTABLE_BASE_PADDR
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#define PGTABLE_L2_BASE_PADDR (PGTABLE_BASE_PADDR+0x00000800)
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#define PGTABLE_L2_COARSE_PBASE (PGTABLE_BASE_PADDR+0x00000800)
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#define PGTABLE_L2_FINE_PBASE (PGTABLE_BASE_PADDR+0x00001000)
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||||||
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
|
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
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||||||
|
|
||||||
#define PGTABLE_BASE_VADDR DM320_SDRAM_VADDR
|
#define PGTABLE_BASE_VADDR DM320_SDRAM_VADDR
|
||||||
#define PGTABLE_SDRAM_VADDR PGTABLE_BASE_VADDR
|
#define PGTABLE_SDRAM_VADDR PGTABLE_BASE_VADDR
|
||||||
#define PGTABLE_L2_BASE_VADDR (PGTABLE_BASE_VADDR+0x00000800)
|
#define PGTABLE_L2_COARSE_VBASE (PGTABLE_BASE_VADDR+0x00000800)
|
||||||
|
#define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+0x00001000)
|
||||||
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
|
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
|
||||||
|
|
||||||
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR)
|
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR)
|
||||||
|
@ -275,7 +275,7 @@ static void up_vectormapping(void)
|
|||||||
|
|
||||||
while (vector_paddr < end_paddr)
|
while (vector_paddr < end_paddr)
|
||||||
{
|
{
|
||||||
up_setlevel2coarseentry(PGTABLE_L2_BASE_VADDR, vector_paddr,
|
up_setlevel2coarseentry(PGTABLE_L2_COARSE_VBASE, vector_paddr,
|
||||||
vector_vaddr, MMU_L2_VECTORFLAGS);
|
vector_vaddr, MMU_L2_VECTORFLAGS);
|
||||||
vector_paddr += 4096;
|
vector_paddr += 4096;
|
||||||
vector_vaddr += 4096;
|
vector_vaddr += 4096;
|
||||||
@ -283,7 +283,7 @@ static void up_vectormapping(void)
|
|||||||
|
|
||||||
/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
|
/* Now set the level 1 descriptor to refer to the level 2 coarse page table. */
|
||||||
|
|
||||||
up_setlevel1entry(PGTABLE_L2_BASE_PADDR, LPC313X_VECTOR_VCOARSE,
|
up_setlevel1entry(PGTABLE_L2_COARSE_PBASE, LPC313X_VECTOR_VCOARSE,
|
||||||
MMU_L1_VECTORFLAGS);
|
MMU_L1_VECTORFLAGS);
|
||||||
}
|
}
|
||||||
#endif
|
#endif
|
||||||
|
@ -321,10 +321,15 @@
|
|||||||
* normal operation). We will reuse this memory for coarse page tables as follows:
|
* normal operation). We will reuse this memory for coarse page tables as follows:
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define PGTABLE_L2_OFFSET ((LPC313X_LAST_PSECTION >> 20) << 2)
|
#define PGTABLE_L2_COARSE_OFFSET ((((LPC313X_LAST_PSECTION >> 20) + 255) & ~255) << 2)
|
||||||
#define PGTABLE_L2_BASE_PADDR (PGTABLE_BASE_PADDR+PGTABLE_L2_OFFSET)
|
#define PGTABLE_L2_COARSE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_COARSE_OFFSET)
|
||||||
|
#define PGTABLE_L2_COARSE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_COARSE_OFFSET)
|
||||||
|
|
||||||
|
#define PGTABLE_L2_FINE_OFFSET ((((LPC313X_LAST_PSECTION >> 20) + 1023) & ~1023) << 2)
|
||||||
|
#define PGTABLE_L2_FINE_PBASE (PGTABLE_BASE_PADDR+PGTABLE_L2_FINE_OFFSET)
|
||||||
|
#define PGTABLE_L2_FINE_VBASE (PGTABLE_BASE_VADDR+PGTABLE_L2_FINE_OFFSET)
|
||||||
|
|
||||||
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
|
#define PGTABLE_L2_END_PADDR (PGTABLE_BASE_PADDR+PGTABLE_SIZE)
|
||||||
#define PGTABLE_L2_BASE_VADDR (PGTABLE_BASE_VADDR+PGTABLE_L2_OFFSET)
|
|
||||||
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
|
#define PGTABLE_L2_END_VADDR (PGTABLE_BASE_VADDR+PGTABLE_SIZE)
|
||||||
|
|
||||||
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR)
|
#define PGTABLE_L2_ALLOC (PGTABLE_L2_END_VADDR-PGTABLE_L2_BASE_VADDR)
|
||||||
|
Loading…
Reference in New Issue
Block a user