From 080aa07110227574f91268f49af39c510278ca7e Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Tue, 14 Jun 2016 12:34:29 -0600 Subject: [PATCH] arch/mips/: Change some *err() message to *info() messages if what was a *dbg() message does not indicate and error condition. --- arch/mips/src/common/up_exit.c | 20 ++-- arch/mips/src/common/up_initialize.c | 4 +- arch/mips/src/mips32/up_releasepending.c | 2 +- arch/mips/src/mips32/up_reprioritizertr.c | 2 +- arch/mips/src/mips32/up_schedulesigaction.c | 5 +- arch/mips/src/mips32/up_sigdeliver.c | 2 +- arch/mips/src/mips32/up_swint0.c | 52 +++++----- arch/mips/src/mips32/up_vfork.c | 4 +- arch/mips/src/pic32mx/Kconfig | 2 +- arch/mips/src/pic32mx/pic32mx-ethernet.c | 102 +++++++++--------- arch/mips/src/pic32mx/pic32mx-exception.c | 98 ++++++++---------- arch/mips/src/pic32mx/pic32mx-gpio.c | 22 ++-- arch/mips/src/pic32mx/pic32mx-spi.c | 27 +++-- arch/mips/src/pic32mx/pic32mx-usbdev.c | 109 ++++++++++---------- arch/mips/src/pic32mz/Kconfig | 4 +- arch/mips/src/pic32mz/pic32mz-ethernet.c | 103 +++++++++--------- arch/mips/src/pic32mz/pic32mz-exception.c | 98 ++++++++---------- arch/mips/src/pic32mz/pic32mz-gpio.c | 24 ++--- arch/mips/src/pic32mz/pic32mz-gpio.h | 2 +- arch/mips/src/pic32mz/pic32mz-spi.c | 30 +++--- arch/rgmp/src/x86/com.c | 6 +- 21 files changed, 338 insertions(+), 380 deletions(-) diff --git a/arch/mips/src/common/up_exit.c b/arch/mips/src/common/up_exit.c index ad1dbeb343..d26de05841 100644 --- a/arch/mips/src/common/up_exit.c +++ b/arch/mips/src/common/up_exit.c @@ -87,8 +87,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) int i; #endif - serr(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); - serr(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); + sinfo(" TCB=%p name=%s pid=%d\n", tcb, tcb->argv[0], tcb->pid); + sinfo(" priority=%d state=%d\n", tcb->sched_priority, tcb->task_state); #if CONFIG_NFILE_DESCRIPTORS > 0 filelist = tcb->group->tg_filelist; @@ -97,8 +97,8 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) struct inode *inode = filelist->fl_files[i].f_inode; if (inode) { - serr(" fd=%d refcount=%d\n", - i, inode->i_crefs); + sinfo(" fd=%d refcount=%d\n", + i, inode->i_crefs); } } #endif @@ -111,11 +111,11 @@ static void _up_dumponexit(FAR struct tcb_s *tcb, FAR void *arg) if (filep->fs_fd >= 0) { #if CONFIG_STDIO_BUFFER_SIZE > 0 - serr(" fd=%d nbytes=%d\n", - filep->fs_fd, - filep->fs_bufpos - filep->fs_bufstart); + sinfo(" fd=%d nbytes=%d\n", + filep->fs_fd, + filep->fs_bufpos - filep->fs_bufstart); #else - serr(" fd=%d\n", filep->fs_fd); + sinfo(" fd=%d\n", filep->fs_fd); #endif } } @@ -148,10 +148,10 @@ void _exit(int status) (void)up_irq_save(); - sllerr("TCB=%p exiting\n", this_task()); + sllinfo("TCB=%p exiting\n", this_task()); #if defined(CONFIG_DUMP_ON_EXIT) && defined(CONFIG_DEBUG_FEATURES) - sllerr("Other tasks:\n"); + sllinfo("Other tasks:\n"); sched_foreach(_up_dumponexit, NULL); #endif diff --git a/arch/mips/src/common/up_initialize.c b/arch/mips/src/common/up_initialize.c index f87882685b..2529020267 100644 --- a/arch/mips/src/common/up_initialize.c +++ b/arch/mips/src/common/up_initialize.c @@ -76,13 +76,13 @@ static void up_calibratedelay(void) { int i; - llerr("Beginning 100s delay\n"); + llwarn("Beginning 100s delay\n"); for (i = 0; i < 100; i++) { up_mdelay(1000); } - llerr("End 100s delay\n"); + llwarn("End 100s delay\n"); } #else # define up_calibratedelay() diff --git a/arch/mips/src/mips32/up_releasepending.c b/arch/mips/src/mips32/up_releasepending.c index 57310e30d1..862f81ed75 100644 --- a/arch/mips/src/mips32/up_releasepending.c +++ b/arch/mips/src/mips32/up_releasepending.c @@ -69,7 +69,7 @@ void up_release_pending(void) { struct tcb_s *rtcb = this_task(); - sllerr("From TCB=%p\n", rtcb); + sllinfo("From TCB=%p\n", rtcb); /* Merge the g_pendingtasks list into the ready-to-run task list */ diff --git a/arch/mips/src/mips32/up_reprioritizertr.c b/arch/mips/src/mips32/up_reprioritizertr.c index 0f34c13894..7f80dd31fb 100644 --- a/arch/mips/src/mips32/up_reprioritizertr.c +++ b/arch/mips/src/mips32/up_reprioritizertr.c @@ -97,7 +97,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority) struct tcb_s *rtcb = this_task(); bool switch_needed; - sllerr("TCB=%p PRI=%d\n", tcb, priority); + sllinfo("TCB=%p PRI=%d\n", tcb, priority); /* Remove the tcb task from the ready-to-run list. * sched_removereadytorun will return true if we just diff --git a/arch/mips/src/mips32/up_schedulesigaction.c b/arch/mips/src/mips32/up_schedulesigaction.c index 2af3169ee6..e44384c5aa 100644 --- a/arch/mips/src/mips32/up_schedulesigaction.c +++ b/arch/mips/src/mips32/up_schedulesigaction.c @@ -95,7 +95,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) irqstate_t flags; uint32_t status; - serr("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); /* Make sure that interrupts are disabled */ @@ -109,7 +109,8 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) * being delivered to the currently executing task. */ - serr("rtcb=0x%p g_current_regs=0x%p\n", this_task(), g_current_regs); + sinfo("rtcb=0x%p g_current_regs=0x%p\n", + this_task(), g_current_regs); if (tcb == this_task()) { diff --git a/arch/mips/src/mips32/up_sigdeliver.c b/arch/mips/src/mips32/up_sigdeliver.c index c514731ca1..bf8f8e1708 100644 --- a/arch/mips/src/mips32/up_sigdeliver.c +++ b/arch/mips/src/mips32/up_sigdeliver.c @@ -96,7 +96,7 @@ void up_sigdeliver(void) board_autoled_on(LED_SIGNAL); - serr("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); ASSERT(rtcb->xcp.sigdeliver != NULL); diff --git a/arch/mips/src/mips32/up_swint0.c b/arch/mips/src/mips32/up_swint0.c index 6e23087108..720aaa3bce 100644 --- a/arch/mips/src/mips32/up_swint0.c +++ b/arch/mips/src/mips32/up_swint0.c @@ -66,18 +66,14 @@ #ifdef CONFIG_DEBUG_SYSCALL # define swierr(format, ...) llerr(format, ##__VA_ARGS__) +# define swiwarn(format, ...) llwarn(format, ##__VA_ARGS__) +# define swiinfo(format, ...) llinfo(format, ##__VA_ARGS__) #else # define swierr(x...) +# define swiwarn(x...) +# define swiinfo(x...) #endif -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -89,25 +85,25 @@ #ifdef CONFIG_DEBUG_SYSCALL static void up_registerdump(const uint32_t *regs) { - swierr("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n", - regs[REG_MFLO], regs[REG_MFHI], regs[REG_EPC], regs[REG_STATUS]); - swierr("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n", - regs[REG_AT], regs[REG_V0], regs[REG_V1], regs[REG_A0], - regs[REG_A1], regs[REG_A2], regs[REG_A3]); - swierr("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n", - regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3], - regs[REG_T4], regs[REG_T5], regs[REG_T6], regs[REG_T7]); - swierr("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", - regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3], - regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]); + swiinfo("MFLO:%08x MFHI:%08x EPC:%08x STATUS:%08x\n", + regs[REG_MFLO], regs[REG_MFHI], regs[REG_EPC], regs[REG_STATUS]); + swiinfo("AT:%08x V0:%08x V1:%08x A0:%08x A1:%08x A2:%08x A3:%08x\n", + regs[REG_AT], regs[REG_V0], regs[REG_V1], regs[REG_A0], + regs[REG_A1], regs[REG_A2], regs[REG_A3]); + swiinfo("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x T7:%08x\n", + regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3], + regs[REG_T4], regs[REG_T5], regs[REG_T6], regs[REG_T7]); + swiinfo("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x S6:%08x S7:%08x\n", + regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3], + regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]); #ifdef MIPS32_SAVE_GP - swierr("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n", - regs[REG_T8], regs[REG_T9], regs[REG_GP], regs[REG_SP], - regs[REG_FP], regs[REG_RA]); + swiinfo("T8:%08x T9:%08x GP:%08x SP:%08x FP:%08x RA:%08x\n", + regs[REG_T8], regs[REG_T9], regs[REG_GP], regs[REG_SP], + regs[REG_FP], regs[REG_RA]); #else - swierr("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n", - regs[REG_T8], regs[REG_T9], regs[REG_SP], regs[REG_FP], - regs[REG_RA]); + swiinfo("T8:%08x T9:%08x SP:%08x FP:%08x RA:%08x\n", + regs[REG_T8], regs[REG_T9], regs[REG_SP], regs[REG_FP], + regs[REG_RA]); #endif } #else @@ -168,7 +164,7 @@ int up_swint0(int irq, FAR void *context) */ #ifdef CONFIG_DEBUG_SYSCALL - swierr("Entry: regs: %p cmd: %d\n", regs, regs[REG_R4]); + swiinfo("Entry: regs: %p cmd: %d\n", regs, regs[REG_R4]); up_registerdump(regs); #endif @@ -300,12 +296,12 @@ int up_swint0(int irq, FAR void *context) #ifdef CONFIG_DEBUG_SYSCALL if (regs != g_current_regs) { - swierr("SWInt Return: Context switch!\n"); + swiinfo("SWInt Return: Context switch!\n"); up_registerdump((const uint32_t *)g_current_regs); } else { - swierr("SWInt Return: %d\n", regs[REG_V0]); + swiinfo("SWInt Return: %d\n", regs[REG_V0]); } #endif diff --git a/arch/mips/src/mips32/up_vfork.c b/arch/mips/src/mips32/up_vfork.c index 4ceb0a7215..06b79f7bb1 100644 --- a/arch/mips/src/mips32/up_vfork.c +++ b/arch/mips/src/mips32/up_vfork.c @@ -152,7 +152,7 @@ pid_t up_vfork(const struct vfork_s *context) child = task_vforksetup((start_t)context->ra); if (!child) { - serr("task_vforksetup failed\n"); + sinfo("task_vforksetup failed\n"); return (pid_t)ERROR; } @@ -171,7 +171,7 @@ pid_t up_vfork(const struct vfork_s *context) parent->flags & TCB_FLAG_TTYPE_MASK); if (ret != OK) { - serr("up_create_stack failed: %d\n", ret); + serr("ERROR: up_create_stack failed: %d\n", ret); task_vforkabort(child, -ret); return (pid_t)ERROR; } diff --git a/arch/mips/src/pic32mx/Kconfig b/arch/mips/src/pic32mx/Kconfig index 6d24c3e355..61b5b71c7f 100644 --- a/arch/mips/src/pic32mx/Kconfig +++ b/arch/mips/src/pic32mx/Kconfig @@ -1034,7 +1034,7 @@ config PIC32MX_SPI_ENHBUF config PIC32MX_SPI_REGDEBUG bool "SPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_INFO default n ---help--- Output detailed register-level SPI device debug information. diff --git a/arch/mips/src/pic32mx/pic32mx-ethernet.c b/arch/mips/src/pic32mx/pic32mx-ethernet.c index 0ae50a7357..47cb807acf 100644 --- a/arch/mips/src/pic32mx/pic32mx-ethernet.c +++ b/arch/mips/src/pic32mx/pic32mx-ethernet.c @@ -141,15 +141,6 @@ #define PIC32MX_NBUFFERS (CONFIG_NET_NRXDESC + CONFIG_NET_NTXDESC + 1) /* Debug Configuration *****************************************************/ -/* Register/Descriptor debug -- can only happen of CONFIG_DEBUG_FEATURES is selected. - * This will probably generate much more output than you care to see. - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_NET_REGDEBUG -# undef CONFIG_NET_DESCDEBUG -#endif - /* CONFIG_NET_DUMPPACKET will dump the contents of each packet to the * console. */ @@ -447,7 +438,7 @@ static void pic32mx_ethreset(struct pic32mx_driver_s *priv); #ifdef CONFIG_NET_REGDEBUG static void pic32mx_printreg(uint32_t addr, uint32_t val, bool iswrite) { - llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + nllinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -497,7 +488,7 @@ static void pic32mx_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + nllinfo("[repeats %d more times]\n", count); } } @@ -576,12 +567,12 @@ static void pic32mx_putreg(uint32_t val, uint32_t addr) #ifdef CONFIG_NET_DESCDEBUG static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, const char *msg) { - llerr("TX Descriptor [%p]: %s\n", txdesc, msg); - llerr(" status: %08x\n", txdesc->status); - llerr(" address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address)); - llerr(" tsv1: %08x\n", txdesc->tsv1); - llerr(" tsv2: %08x\n", txdesc->tsv2); - llerr(" nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted)); + nllinfo("TX Descriptor [%p]: %s\n", txdesc, msg); + nllinfo(" status: %08x\n", txdesc->status); + nllinfo(" address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address)); + nllinfo(" tsv1: %08x\n", txdesc->tsv1); + nllinfo(" tsv2: %08x\n", txdesc->tsv2); + nllinfo(" nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted)); } #endif @@ -603,12 +594,12 @@ static void pic32mx_dumptxdesc(struct pic32mx_txdesc_s *txdesc, const char *msg) #ifdef CONFIG_NET_DESCDEBUG static void pic32mx_dumprxdesc(struct pic32mx_rxdesc_s *rxdesc, const char *msg) { - llerr("RX Descriptor [%p]: %s\n", rxdesc, msg); - llerr(" status: %08x\n", rxdesc->status); - llerr(" address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address)); - llerr(" rsv1: %08x\n", rxdesc->rsv1); - llerr(" rsv2: %08x\n", rxdesc->rsv2); - llerr(" nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted)); + nllinfo("RX Descriptor [%p]: %s\n", rxdesc, msg); + nllinfo(" status: %08x\n", rxdesc->status); + nllinfo(" address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address)); + nllinfo(" rsv1: %08x\n", rxdesc->rsv1); + nllinfo(" rsv2: %08x\n", rxdesc->rsv2); + nllinfo(" nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted)); } #endif @@ -1366,7 +1357,8 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) if ((rxdesc->rsv2 & RXDESC_RSV2_OK) == 0) { - nllerr("ERROR. rsv1: %08x rsv2: %08x\n", rxdesc->rsv1, rxdesc->rsv2); + nllerr("ERROR. rsv1: %08x rsv2: %08x\n", + rxdesc->rsv1, rxdesc->rsv2); NETDEV_RXERRORS(&priv->pd_dev); pic32mx_rxreturn(rxdesc); } @@ -1379,7 +1371,7 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) else if (priv->pd_dev.d_len > CONFIG_NET_ETH_MTU) { - nllerr("Too big. packet length: %d rxdesc: %08x\n", + nllerr("ERROR: Too big. packet length: %d rxdesc: %08x\n", priv->pd_dev.d_len, rxdesc->status); NETDEV_RXERRORS(&priv->pd_dev); pic32mx_rxreturn(rxdesc); @@ -1390,7 +1382,8 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) else if ((rxdesc->status & (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) != (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) { - nllerr("Fragment. packet length: %d rxdesc: %08x\n", priv->pd_dev.d_len, rxdesc->status); + nllerr("ERROR: Fragment. packet length: %d rxdesc: %08x\n", + priv->pd_dev.d_len, rxdesc->status); NETDEV_RXFRAGMENTS(&priv->pd_dev); pic32mx_rxreturn(rxdesc); } @@ -1529,7 +1522,8 @@ static void pic32mx_rxdone(struct pic32mx_driver_s *priv) { /* Unrecognized... drop it. */ - nllerr("Unrecognized packet type dropped: %04x\n", ntohs(BUF->type)); + nllerr("ERROR: Unrecognized packet type dropped: %04x\n", + ntohs(BUF->type)); NETDEV_RXDROPPED(&priv->pd_dev); } @@ -1691,7 +1685,7 @@ static int pic32mx_interrupt(int irq, void *context) if ((status & ETH_INT_RXOVFLW) != 0) { - nllerr("RX Overrun. status: %08x\n", status); + nllerr("ERROR: RX Overrun. status: %08x\n", status); NETDEV_RXERRORS(&priv->pd_dev); } @@ -1702,7 +1696,7 @@ static int pic32mx_interrupt(int irq, void *context) if ((status & ETH_INT_RXBUFNA) != 0) { - nllerr("RX buffer descriptor overrun. status: %08x\n", status); + nllerr("ERROR: RX buffer descriptor overrun. status: %08x\n", status); NETDEV_RXERRORS(&priv->pd_dev); } @@ -1713,7 +1707,7 @@ static int pic32mx_interrupt(int irq, void *context) if ((status & ETH_INT_RXBUSE) != 0) { - nllerr("RX BVCI bus error. status: %08x\n", status); + nllerr("ERROR: RX BVCI bus error. status: %08x\n", status); NETDEV_RXERRORS(&priv->pd_dev); } @@ -1756,7 +1750,7 @@ static int pic32mx_interrupt(int irq, void *context) if ((status & ETH_INT_TXABORT) != 0) { - nllerr("TX abort. status: %08x\n", status); + nllerr("ERROR: TX abort. status: %08x\n", status); NETDEV_TXERRORS(&priv->pd_dev); } @@ -1767,7 +1761,7 @@ static int pic32mx_interrupt(int irq, void *context) if ((status & ETH_INT_TXBUSE) != 0) { - nllerr("TX BVCI bus error. status: %08x\n", status); + nllerr("ERROR: TX BVCI bus error. status: %08x\n", status); NETDEV_TXERRORS(&priv->pd_dev); } @@ -1921,9 +1915,9 @@ static int pic32mx_ifup(struct net_driver_s *dev) uint32_t regval; int ret; - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Reset the Ethernet controller (again) */ @@ -2011,7 +2005,7 @@ static int pic32mx_ifup(struct net_driver_s *dev) ret = pic32mx_phyinit(priv); if (ret != 0) { - nerr("pic32mx_phyinit failed: %d\n", ret); + nerr("ERROR: pic32mx_phyinit failed: %d\n", ret); return ret; } @@ -2373,14 +2367,14 @@ static int pic32mx_rmmac(struct net_driver_s *dev, const uint8_t *mac) #if defined(CONFIG_NET_REGDEBUG) && defined(PIC32MX_HAVE_PHY) static void pic32mx_showmii(uint8_t phyaddr, const char *msg) { - err("PHY " PIC32MX_PHYNAME ": %s\n", msg); - err(" MCR: %04x\n", pic32mx_phyread(phyaddr, MII_MCR)); - err(" MSR: %04x\n", pic32mx_phyread(phyaddr, MII_MSR)); - err(" ADVERTISE: %04x\n", pic32mx_phyread(phyaddr, MII_ADVERTISE)); - err(" LPA: %04x\n", pic32mx_phyread(phyaddr, MII_LPA)); - err(" EXPANSION: %04x\n", pic32mx_phyread(phyaddr, MII_EXPANSION)); + nllinfo("PHY " PIC32MX_PHYNAME ": %s\n", msg); + nllinfo(" MCR: %04x\n", pic32mx_phyread(phyaddr, MII_MCR)); + nllinfo(" MSR: %04x\n", pic32mx_phyread(phyaddr, MII_MSR)); + nllinfo(" ADVERTISE: %04x\n", pic32mx_phyread(phyaddr, MII_ADVERTISE)); + nllinfo(" LPA: %04x\n", pic32mx_phyread(phyaddr, MII_LPA)); + nllinfo(" EXPANSION: %04x\n", pic32mx_phyread(phyaddr, MII_EXPANSION)); #ifdef CONFIG_ETH0_PHY_KS8721 - err(" 10BTCR: %04x\n", pic32mx_phyread(phyaddr, MII_KS8721_10BTCR)); + nllinfo(" 10BTCR: %04x\n", pic32mx_phyread(phyaddr, MII_KS8721_10BTCR)); #endif } #endif @@ -2543,7 +2537,7 @@ static inline int pic32mx_phyreset(uint8_t phyaddr) } } - nerr("Reset failed. MCR: %04x\n", phyreg); + nerr("ERROR: Reset failed. MCR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2590,7 +2584,7 @@ static inline int pic32mx_phyautoneg(uint8_t phyaddr) } } - nerr("Auto-negotiation failed. MSR: %04x\n", phyreg); + nerr("ERROR: Auto-negotiation failed. MSR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2669,7 +2663,7 @@ static int pic32mx_phymode(uint8_t phyaddr, uint8_t mode) #endif } - nerr("Link failed. MSR: %04x\n", phyreg); + nerr("ERROR: Link failed. MSR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2738,7 +2732,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) ret = pic32mx_phyreset(phyaddr); if (ret < 0) { - nerr("Failed to reset PHY at address %d\n", phyaddr); + nerr("ERROR: Failed to reset PHY at address %d\n", phyaddr); continue; } @@ -2771,7 +2765,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) { /* Failed to find PHY at any location */ - nerr("No PHY detected\n"); + nerr("ERROR: No PHY detected\n"); return -ENODEV; } ninfo("phyaddr: %d\n", phyaddr); @@ -2875,7 +2869,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) priv->pd_mode = PIC32MX_100BASET_FD; break; default: - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } #elif defined(CONFIG_ETH0_PHY_DP83848C) @@ -2898,7 +2892,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) priv->pd_mode = PIC32MX_10BASET_FD; break; default: - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } #elif defined(CONFIG_ETH0_PHY_LAN8720) @@ -2943,7 +2937,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) } else { - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } } @@ -2951,9 +2945,9 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv) # warning "PHY Unknown: speed and duplex are bogus" #endif - nerr("%dBase-T %s duplex\n", - (priv->pd_mode & PIC32MX_SPEED_MASK) == PIC32MX_SPEED_100 ? 100 : 10, - (priv->pd_mode & PIC32MX_DUPLEX_MASK) == PIC32MX_DUPLEX_FULL ?"full" : "half"); + ninfo("%dBase-T %s duplex\n", + (priv->pd_mode & PIC32MX_SPEED_MASK) == PIC32MX_SPEED_100 ? 100 : 10, + (priv->pd_mode & PIC32MX_DUPLEX_MASK) == PIC32MX_DUPLEX_FULL ?"full" : "half"); /* Disable auto-configuration. Set the fixed speed/duplex mode. * (probably more than little redundant). diff --git a/arch/mips/src/pic32mx/pic32mx-exception.c b/arch/mips/src/pic32mx/pic32mx-exception.c index 66feb977f9..7ff728db31 100644 --- a/arch/mips/src/pic32mx/pic32mx-exception.c +++ b/arch/mips/src/pic32mx/pic32mx-exception.c @@ -55,22 +55,6 @@ #include "pic32mx-int.h" #include "pic32mx.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -106,88 +90,88 @@ uint32_t *pic32mx_exception(uint32_t *regs) switch (cause & CP0_CAUSE_EXCCODE_MASK) { case CP0_CAUSE_EXCCODE_INT: /* Interrupt */ - llinfo("EXCEPTION: Interrupt" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Interrupt" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TLBL: /* TLB exception (load or instruction fetch) */ - llinfo("EXCEPTION: TLB exception (load or instruction fetch)" - " CAUSE: %08x EPC:%08x\n", cause, epc); + alert("EXCEPTION: TLB exception (load or instruction fetch)" + " CAUSE: %08x EPC:%08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TLBS: /* TLB exception (store) */ - llinfo("EXCEPTION: TLB exception (store)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: TLB exception (store)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_ADEL: /* Address error exception (load or instruction fetch) */ - llinfo("EXCEPTION: Address error exception (load or instruction fetch)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Address error exception (load or instruction fetch)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_ADES: /* Address error exception (store) */ - llinfo("EXCEPTION: Address error exception (store)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Address error exception (store)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_IBE: /* Bus error exception (instruction fetch) */ - llinfo("EXCEPTION: Bus error exception (instruction fetch)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Bus error exception (instruction fetch)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_DBE: /* Bus error exception (data reference: load or store) */ - llinfo("EXCEPTION: Bus error exception (data reference: load or store)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Bus error exception (data reference: load or store)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_SYS: /* Syscall exception */ - llinfo("EXCEPTION: Syscall exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Syscall exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_BP: /* Breakpoint exception */ - llinfo("EXCEPTION: Breakpoint exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Breakpoint exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_RI: /* Reserved instruction exception */ - llinfo("EXCEPTION: Reserved instruction exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Reserved instruction exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_CPU: /* Coprocessor Unusable exception */ - llinfo("EXCEPTION: Coprocessor Unusable exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Coprocessor Unusable exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_OV: /* Arithmetic Overflow exception */ - llinfo("EXCEPTION: Arithmetic Overflow exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Arithmetic Overflow exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TR: /* Trap exception */ - llinfo("EXCEPTION: Trap exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Trap exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_FPE: /* Floating point exception */ - llinfo("EXCEPTION: Floating point exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Floating point exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_C2E: /* Precise Coprocessor 2 exceptions */ - llinfo("EXCEPTION: Precise Coprocessor 2 exceptions" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Precise Coprocessor 2 exceptions" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_MDMX: /* MDMX Unusable (MIPS64) */ - llinfo("EXCEPTION: MDMX Unusable (MIPS64)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: MDMX Unusable (MIPS64)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_WATCH: /* WatchHi/WatchLo address */ - llinfo("EXCEPTION: WatchHi/WatchLo address" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: WatchHi/WatchLo address" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_MCHECK: /* Machine check */ - llinfo("EXCEPTION: Machine check" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Machine check" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_CACHEERR: /* Cache error */ - llinfo("EXCEPTION: Cache error" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Cache error" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; default: - llinfo("EXCEPTION: Unknown" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Unknown" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; } #else - llerr("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc); #endif #endif diff --git a/arch/mips/src/pic32mx/pic32mx-gpio.c b/arch/mips/src/pic32mx/pic32mx-gpio.c index 355d152477..61ecde9e8c 100644 --- a/arch/mips/src/pic32mx/pic32mx-gpio.c +++ b/arch/mips/src/pic32mx/pic32mx-gpio.c @@ -321,17 +321,17 @@ void pic32mx_dumpgpio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the GPIO registers */ sched_lock(); - llerr("IOPORT%c pinset: %04x base: %08x -- %s\n", - 'A'+port, pinset, base, msg); - llerr(" TRIS: %08x PORT: %08x LAT: %08x ODC: %08x\n", - getreg32(base + PIC32MX_IOPORT_TRIS_OFFSET), - getreg32(base + PIC32MX_IOPORT_PORT_OFFSET), - getreg32(base + PIC32MX_IOPORT_LAT_OFFSET), - getreg32(base + PIC32MX_IOPORT_ODC_OFFSET)); - llerr(" CNCON: %08x CNEN: %08x CNPUE: %08x\n", - getreg32(PIC32MX_IOPORT_CNCON), - getreg32(PIC32MX_IOPORT_CNEN), - getreg32(PIC32MX_IOPORT_CNPUE)); + llinfo("IOPORT%c pinset: %04x base: %08x -- %s\n", + 'A'+port, pinset, base, msg); + llinfo(" TRIS: %08x PORT: %08x LAT: %08x ODC: %08x\n", + getreg32(base + PIC32MX_IOPORT_TRIS_OFFSET), + getreg32(base + PIC32MX_IOPORT_PORT_OFFSET), + getreg32(base + PIC32MX_IOPORT_LAT_OFFSET), + getreg32(base + PIC32MX_IOPORT_ODC_OFFSET)); + llinfo(" CNCON: %08x CNEN: %08x CNPUE: %08x\n", + getreg32(PIC32MX_IOPORT_CNCON), + getreg32(PIC32MX_IOPORT_CNEN), + getreg32(PIC32MX_IOPORT_CNPUE)); sched_unlock(); } } diff --git a/arch/mips/src/pic32mx/pic32mx-spi.c b/arch/mips/src/pic32mx/pic32mx-spi.c index 94e20314fc..886dbcae0e 100644 --- a/arch/mips/src/pic32mx/pic32mx-spi.c +++ b/arch/mips/src/pic32mx/pic32mx-spi.c @@ -76,13 +76,11 @@ #ifdef CONFIG_DEBUG_SPI # define spierr llerr -# ifdef CONFIG_DEBUG_INFO -# define spiinfo llerr -# else -# define spiinfo(x...) -# endif +# define spiwarn llwarn +# define spiinfo llinfo #else # define spierr(x...) +# define spiwarn(x...) # define spiinfo(x...) #endif @@ -329,7 +327,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) { if (count == 4) { - llerr("...\n"); + llinfo("...\n"); } return value; } @@ -345,7 +343,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + llinfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -357,7 +355,7 @@ static uint32_t spi_getreg(FAR struct pic32mx_dev_s *priv, unsigned int offset) /* Show the register value read */ - llerr("%08x->%08x\n", addr, value); + llinfo("%08x->%08x\n", addr, value); return value; } #else @@ -395,7 +393,7 @@ static void spi_putreg(FAR struct pic32mx_dev_s *priv, unsigned int offset, /* Show the register value being written */ - llerr("%08x<-%08x\n", addr, value); + llinfo("%08x<-%08x\n", addr, value); /* Then do the write */ @@ -526,7 +524,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) priv->frequency = frequency; priv->actual = actual; - spierr("New frequency: %d Actual: %d\n", frequency, actual); + spiinfo("New frequency: %d Actual: %d\n", frequency, actual); return actual; } @@ -665,7 +663,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) } else { - spierr("Unsupported nbits: %d\n", nbits); + spierr("ERROR: Unsupported nbits: %d\n", nbits); return; } @@ -897,7 +895,7 @@ FAR struct spi_dev_s *pic32mx_spibus_initialize(int port) else #endif { - spierr("Unsuppport port: %d\n", port); + spierr("ERROR: Unsuppport port: %d\n", port); return NULL; } @@ -926,7 +924,8 @@ FAR struct spi_dev_s *pic32mx_spibus_initialize(int port) ret = irq_attach(priv->vector, spi_interrupt); if (ret < 0) { - spierr("Failed to attach vector: %d port: %d\n", priv->vector, port); + spierr("ERROR: Failed to attach vector: %d port: %d\n", + priv->vector, port); goto errout; } #endif @@ -976,7 +975,7 @@ FAR struct spi_dev_s *pic32mx_spibus_initialize(int port) ret = up_prioritize_irq(priv->vector, CONFIG_PIC32MX_SPI_PRIORITY) if (ret < 0) { - spierr("up_prioritize_irq failed: %d\n", ret); + spierr("ERROR: up_prioritize_irq failed: %d\n", ret); goto errout; } #endif diff --git a/arch/mips/src/pic32mx/pic32mx-usbdev.c b/arch/mips/src/pic32mx/pic32mx-usbdev.c index 948df83d89..0c43382e1c 100644 --- a/arch/mips/src/pic32mx/pic32mx-usbdev.c +++ b/arch/mips/src/pic32mx/pic32mx-usbdev.c @@ -79,15 +79,6 @@ # define CONFIG_USBDEV_EP0_MAXSIZE 64 #endif -/* Extremely detailed register/BDT debug that you would normally never want - * enabled. - */ - -#ifndef CONFIG_DEBUG_FEATURES -# undef CONFIG_PIC32MX_USBDEV_REGDEBUG -# undef CONFIG_PIC32MX_USBDEV_BDTDEBUG -#endif - /* Disable this logic because it is buggy. It works most of the time but * has some lurking issues that keep this higher performance solution from * being usable. @@ -289,18 +280,16 @@ # undef CONFIG_PIC32MX_USBDEV_BDTDEBUG # define CONFIG_PIC32MX_USBDEV_BDTDEBUG 1 -# define regerr llerr -# ifdef CONFIG_DEBUG_INFO -# define reginfo llerr -# else -# define reginfo(x...) -# endif +# define regerr llerr +# define regwarn llwarn +# define reginfo llinfo #else # define pic32mx_getreg(addr) getreg16(addr) # define pic32mx_putreg(val,addr) putreg16(val,addr) # define regerr(x...) +# define regwarn(x...) # define reginfo(x...) #endif @@ -309,16 +298,14 @@ #ifdef CONFIG_PIC32MX_USBDEV_BDTDEBUG -# define bdterr llerr -# ifdef CONFIG_DEBUG_INFO -# define bdtinfo llerr -# else -# define bdtinfo(x...) -# endif +# define bdterr llerr +# define bdtwarn llwarn +# define bdtinfo llinfo #else # define bdterr(x...) +# define bdtwarn(x...) # define bdtinfo(x...) #endif @@ -602,16 +589,13 @@ static volatile struct usbotg_bdtentry_s g_bdt[4*PIC32MX_NENDPOINTS] __attribute__ ((aligned(512))); /**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Private Functions + * Private Functions ****************************************************************************/ /**************************************************************************** * Register Operations ****************************************************************************/ + /**************************************************************************** * Name: pic32mx_getreg ****************************************************************************/ @@ -637,8 +621,9 @@ static uint16_t pic32mx_getreg(uint32_t addr) { if (count == 4) { - llerr("...\n"); + reginfo("...\n"); } + return val; } } @@ -653,7 +638,7 @@ static uint16_t pic32mx_getreg(uint32_t addr) { /* Yes.. then show how many times the value repeated */ - llerr("[repeats %d more times]\n", count-3); + reginfo("[repeats %d more times]\n", count-3); } /* Save the new address, value, and count */ @@ -665,7 +650,7 @@ static uint16_t pic32mx_getreg(uint32_t addr) /* Show the register value read */ - llerr("%08x->%04x\n", addr, val); + reginfo("%08x->%04x\n", addr, val); return val; } #endif @@ -679,7 +664,7 @@ static void pic32mx_putreg(uint16_t val, uint32_t addr) { /* Show the register value being written */ - llerr("%08x<-%04x\n", addr, val); + reginfo("%08x<-%04x\n", addr, val); /* Write the value */ @@ -874,8 +859,8 @@ static void pic32mx_epwrite(struct pic32mx_ep_s *privep, /* And, finally, give the BDT to the USB */ - bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", - USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr); + bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", + USB_EPNO(privep->ep.eplog), bdt, status, bdt->addr); bdt->status = status; } @@ -915,8 +900,8 @@ static void pic32mx_wrcomplete(struct pic32mx_usbdev_s *priv, epno, privreq->req.len, privreq->req.xfrd, privreq->inflight[0], privreq->inflight[1]); #endif - bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", - epno, bdtin, bdtin->status, bdtin->addr); + bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", + epno, bdtin, bdtin->status, bdtin->addr); /* We should own the BDT that just completed. But NULLify the entire BDT IN. * Why? So that we can tell later that the BDT available. No, it is not @@ -1340,8 +1325,8 @@ static int pic32mx_rdcomplete(struct pic32mx_usbdev_s *priv, ullinfo("EP%d: len=%d xfrd=%d\n", epno, privreq->req.len, privreq->req.xfrd); - bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", - epno, bdtout, bdtout->status, bdtout->addr); + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdtout, bdtout->status, bdtout->addr); /* We should own the BDT that just completed */ @@ -1484,7 +1469,8 @@ static int pic32mx_ep0rdsetup(struct pic32mx_usbdev_s *priv, uint8_t *dest, /* Then give the BDT to the USB */ - bdterr("EP0 BDT OUT [%p] {%08x, %08x}\n", bdtout, status, bdtout->addr); + bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", + bdtout, status, bdtout->addr); bdtout->status = status; priv->ctrlstate = CTRLSTATE_RDREQUEST; @@ -1585,7 +1571,8 @@ static int pic32mx_rdsetup(struct pic32mx_ep_s *privep, uint8_t *dest, int readl /* Then give the BDT to the USB */ - bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdtout, status, bdtout->addr); + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdtout, status, bdtout->addr); bdtout->status = status; return OK; @@ -2596,7 +2583,8 @@ static void pic32mx_ep0transfer(struct pic32mx_usbdev_s *priv, uint16_t ustat) bdt = &g_bdt[index]; priv->eplist[0].bdtout = bdt; - bdterr("EP0 BDT OUT [%p] {%08x, %08x}\n", bdt, bdt->status, bdt->addr); + bdtinfo("EP0 BDT OUT [%p] {%08x, %08x}\n", + bdt, bdt->status, bdt->addr); /* Check the current EP0 OUT buffer contains a SETUP packet */ @@ -2832,7 +2820,7 @@ static int pic32mx_interrupt(int irq, void *context) if ((usbir & USB_INT_UERR) != 0) { usbtrace(TRACE_INTDECODE(PIC32MX_TRACEINTID_UERR), usbir); - ullerr("Error: EIR=%04x\n", pic32mx_getreg(PIC32MX_USB_EIR)); + ullerr("ERROR: EIR=%04x\n", pic32mx_getreg(PIC32MX_USB_EIR)); /* Clear all pending USB error interrupts */ @@ -3210,7 +3198,8 @@ static int pic32mx_epconfigure(struct usbdev_ep_s *ep, bdt->status = 0; bdt->addr = 0; - bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", + epno, bdt, bdt->status, bdt->addr); /* Now do the same for the other buffer. */ @@ -3218,7 +3207,8 @@ static int pic32mx_epconfigure(struct usbdev_ep_s *ep, bdt->status = 0; bdt->addr = 0; - bdterr("EP%d BDT IN [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT IN [%p] {%08x, %08x}\n", + epno, bdt, bdt->status, bdt->addr); } if (!epin || bidi) @@ -3232,7 +3222,8 @@ static int pic32mx_epconfigure(struct usbdev_ep_s *ep, bdt->status = 0; bdt->addr = 0; - bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdt, bdt->status, bdt->addr); /* Now do the same for the other buffer. */ @@ -3240,7 +3231,8 @@ static int pic32mx_epconfigure(struct usbdev_ep_s *ep, bdt->status = 0; bdt->addr = 0; - bdterr("EP%d BDT OUT [%p] {%08x, %08x}\n", epno, bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT OUT [%p] {%08x, %08x}\n", + epno, bdt, bdt->status, bdt->addr); } /* Get the maxpacket size of the endpoint. */ @@ -3376,7 +3368,8 @@ static int pic32mx_epsubmit(struct usbdev_ep_s *ep, struct usbdev_req_s *req) if (!req || !req->callback || !req->buf || !ep) { usbtrace(TRACE_DEVERROR(PIC32MX_TRACEERR_INVALIDPARMS), 0); - ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + ullerr("ERROR: req=%p callback=%p buf=%p ep=%p\n", + req, req->callback, req->buf, ep); return -EINVAL; } #endif @@ -3575,10 +3568,10 @@ static int pic32mx_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) bdt->addr = (uint8_t *)physaddr; bdt->status = (USB_BDT_UOWN | bytecount); - bdterr("EP0 BDT IN [%p] {%08x, %08x}\n", - bdt, bdt->status, bdt->addr); - bdterr("EP0 BDT IN [%p] {%08x, %08x}\n", - otherbdt, otherbdt->status, otherbdt->addr); + bdtinfo("EP0 BDT IN [%p] {%08x, %08x}\n", + bdt, bdt->status, bdt->addr); + bdtinfo("EP0 BDT IN [%p] {%08x, %08x}\n", + otherbdt, otherbdt->status, otherbdt->addr); } else { @@ -3592,10 +3585,11 @@ static int pic32mx_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) bdt->addr = 0; bdt->status = 0; - bdterr("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); - bdterr("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); + bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, + otherbdt->addr); /* Restart any queued requests (after a delay so that we can be assured * that the hardware has recovered from the stall -- I don't know of any @@ -3627,10 +3621,11 @@ static int pic32mx_epbdtstall(struct usbdev_ep_s *ep, bool resume, bool epin) pic32mx_rqstop(privep); - bdterr("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); - bdterr("EP%d BDT %s [%p] {%08x, %08x}\n", - epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, otherbdt->addr); + bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", bdt, bdt->status, bdt->addr); + bdtinfo("EP%d BDT %s [%p] {%08x, %08x}\n", + epno, epin ? "IN" : "OUT", otherbdt, otherbdt->status, + otherbdt->addr); } return OK; diff --git a/arch/mips/src/pic32mz/Kconfig b/arch/mips/src/pic32mz/Kconfig index 6a66969184..70dcf7d076 100644 --- a/arch/mips/src/pic32mz/Kconfig +++ b/arch/mips/src/pic32mz/Kconfig @@ -332,7 +332,7 @@ config PIC32MZ_SPI_ENHBUF config PIC32MZ_SPI_REGDEBUG bool "SPI Register level debug" - depends on DEBUG_FEATURES + depends on DEBUG_INFO default n ---help--- Output detailed register-level SPI device debug information. @@ -400,7 +400,7 @@ config NET_WOL config NET_REGDEBUG bool "Register level debug" default n - depends on PIC32MZ_ETHERNET && DEBUG_FEATURES + depends on PIC32MZ_ETHERNET && DEBUG_NET_INFO ---help--- Enabled low level register debug. Also needs CONFIG_DEBUG_FEATURES. diff --git a/arch/mips/src/pic32mz/pic32mz-ethernet.c b/arch/mips/src/pic32mz/pic32mz-ethernet.c index af83f64f2a..c1e2671f92 100644 --- a/arch/mips/src/pic32mz/pic32mz-ethernet.c +++ b/arch/mips/src/pic32mz/pic32mz-ethernet.c @@ -465,7 +465,7 @@ static void pic32mz_ethreset(struct pic32mz_driver_s *priv); #ifdef CONFIG_NET_REGDEBUG static void pic32mz_printreg(uint32_t addr, uint32_t val, bool iswrite) { - llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); + nllinfo("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); } #endif @@ -515,7 +515,7 @@ static void pic32mz_checkreg(uint32_t addr, uint32_t val, bool iswrite) { /* No.. More than one. */ - llerr("[repeats %d more times]\n", count); + nllinfo("[repeats %d more times]\n", count); } } @@ -594,12 +594,12 @@ static void pic32mz_putreg(uint32_t val, uint32_t addr) #ifdef CONFIG_NET_DESCDEBUG static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg) { - llerr("TX Descriptor [%p]: %s\n", txdesc, msg); - llerr(" status: %08x\n", txdesc->status); - llerr(" address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address)); - llerr(" tsv1: %08x\n", txdesc->tsv1); - llerr(" tsv2: %08x\n", txdesc->tsv2); - llerr(" nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted)); + nllinfo("TX Descriptor [%p]: %s\n", txdesc, msg); + nllinfo(" status: %08x\n", txdesc->status); + nllinfo(" address: %08x [%08x]\n", txdesc->address, VIRT_ADDR(txdesc->address)); + nllinfo(" tsv1: %08x\n", txdesc->tsv1); + nllinfo(" tsv2: %08x\n", txdesc->tsv2); + nllinfo(" nexted: %08x [%08x]\n", txdesc->nexted, VIRT_ADDR(txdesc->nexted)); } #endif @@ -621,12 +621,12 @@ static void pic32mz_dumptxdesc(struct pic32mz_txdesc_s *txdesc, const char *msg) #ifdef CONFIG_NET_DESCDEBUG static void pic32mz_dumprxdesc(struct pic32mz_rxdesc_s *rxdesc, const char *msg) { - llerr("RX Descriptor [%p]: %s\n", rxdesc, msg); - llerr(" status: %08x\n", rxdesc->status); - llerr(" address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address)); - llerr(" rsv1: %08x\n", rxdesc->rsv1); - llerr(" rsv2: %08x\n", rxdesc->rsv2); - llerr(" nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted)); + nllinfo("RX Descriptor [%p]: %s\n", rxdesc, msg); + nllinfo(" status: %08x\n", rxdesc->status); + nllinfo(" address: %08x [%08x]\n", rxdesc->address, VIRT_ADDR(rxdesc->address)); + nllinfo(" rsv1: %08x\n", rxdesc->rsv1); + nllinfo(" rsv2: %08x\n", rxdesc->rsv2); + nllinfo(" nexted: %08x [%08x]\n", rxdesc->nexted, VIRT_ADDR(rxdesc->nexted)); } #endif @@ -1384,7 +1384,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv) if ((rxdesc->rsv2 & RXDESC_RSV2_OK) == 0) { - nllerr("ERROR. rsv1: %08x rsv2: %08x\n", rxdesc->rsv1, rxdesc->rsv2); + nllwarn("WARNING. rsv1: %08x rsv2: %08x\n", + rxdesc->rsv1, rxdesc->rsv2); NETDEV_RXERRORS(&priv->pd_dev); pic32mz_rxreturn(rxdesc); } @@ -1397,7 +1398,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv) else if (priv->pd_dev.d_len > CONFIG_NET_ETH_MTU) { - nllerr("Too big. packet length: %d rxdesc: %08x\n", priv->pd_dev.d_len, rxdesc->status); + nllwarn("WARNING: Too big. packet length: %d rxdesc: %08x\n", + priv->pd_dev.d_len, rxdesc->status); NETDEV_RXERRORS(&priv->pd_dev); pic32mz_rxreturn(rxdesc); } @@ -1407,7 +1409,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv) else if ((rxdesc->status & (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) != (RXDESC_STATUS_EOP | RXDESC_STATUS_SOP)) { - nllerr("Fragment. packet length: %d rxdesc: %08x\n", priv->pd_dev.d_len, rxdesc->status); + nllwarn("WARNING: Fragment. packet length: %d rxdesc: %08x\n", + priv->pd_dev.d_len, rxdesc->status); NETDEV_RXFRAGMENTS(&priv->pd_dev); pic32mz_rxreturn(rxdesc); } @@ -1546,7 +1549,8 @@ static void pic32mz_rxdone(struct pic32mz_driver_s *priv) { /* Unrecognized... drop it. */ - nllerr("Unrecognized packet type dropped: %04x\n", ntohs(BUF->type)); + nllwarn("WARNING: Unrecognized packet type dropped: %04x\n", + ntohs(BUF->type)); NETDEV_RXDROPPED(&priv->pd_dev); } @@ -1708,7 +1712,7 @@ static int pic32mz_interrupt(int irq, void *context) if ((status & ETH_INT_RXOVFLW) != 0) { - nllerr("RX Overrun. status: %08x\n", status); + nllerr("ERROR: RX Overrun. status: %08x\n", status); NETDEV_RXERRORS(&priv->pd_dev); } @@ -1719,7 +1723,7 @@ static int pic32mz_interrupt(int irq, void *context) if ((status & ETH_INT_RXBUFNA) != 0) { - nllerr("RX buffer descriptor overrun. status: %08x\n", status); + nllerr("ERROR: RX buffer descriptor overrun. status: %08x\n", status); NETDEV_RXERRORS(&priv->pd_dev); } @@ -1730,7 +1734,7 @@ static int pic32mz_interrupt(int irq, void *context) if ((status & ETH_INT_RXBUSE) != 0) { - nllerr("RX BVCI bus error. status: %08x\n", status); + nllerr("ERROR: RX BVCI bus error. status: %08x\n", status); NETDEV_RXERRORS(&priv->pd_dev); } @@ -1773,7 +1777,7 @@ static int pic32mz_interrupt(int irq, void *context) if ((status & ETH_INT_TXABORT) != 0) { - nllerr("TX abort. status: %08x\n", status); + nllerr("ERROR: TX abort. status: %08x\n", status); NETDEV_TXERRORS(&priv->pd_dev); } @@ -1784,7 +1788,7 @@ static int pic32mz_interrupt(int irq, void *context) if ((status & ETH_INT_TXBUSE) != 0) { - nllerr("TX BVCI bus error. status: %08x\n", status); + nllerr("ERROR: TX BVCI bus error. status: %08x\n", status); NETDEV_TXERRORS(&priv->pd_dev); } @@ -1938,9 +1942,9 @@ static int pic32mz_ifup(struct net_driver_s *dev) uint32_t regval; int ret; - nerr("Bringing up: %d.%d.%d.%d\n", - dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, - (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); + nnllinfoBringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); /* Reset the Ethernet controller (again) */ @@ -2028,7 +2032,7 @@ static int pic32mz_ifup(struct net_driver_s *dev) ret = pic32mz_phyinit(priv); if (ret != 0) { - nerr("pic32mz_phyinit failed: %d\n", ret); + nerr("ERROR: pic32mz_phyinit failed: %d\n", ret); return ret; } @@ -2105,11 +2109,10 @@ static int pic32mz_ifup(struct net_driver_s *dev) priv->pd_dev.d_mac.ether_addr_octet[0] = (uint32_t)(regval & 0xff); priv->pd_dev.d_mac.ether_addr_octet[1] = (uint32_t)((regval >> 8) & 0xff); - nerr("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", - dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1], - dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3], - dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]); - + ninfo("MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->d_mac.ether_addr_octet[0], dev->d_mac.ether_addr_octet[1], + dev->d_mac.ether_addr_octet[2], dev->d_mac.ether_addr_octet[3], + dev->d_mac.ether_addr_octet[4], dev->d_mac.ether_addr_octet[5]); #endif /* Continue Ethernet Controller Initialization ****************************/ @@ -2396,14 +2399,14 @@ static int pic32mz_rmmac(struct net_driver_s *dev, const uint8_t *mac) #if defined(CONFIG_NET_REGDEBUG) && defined(PIC32MZ_HAVE_PHY) static void pic32mz_showmii(uint8_t phyaddr, const char *msg) { - err("PHY " PIC32MZ_PHYNAME ": %s\n", msg); - err(" MCR: %04x\n", pic32mz_phyread(phyaddr, MII_MCR)); - err(" MSR: %04x\n", pic32mz_phyread(phyaddr, MII_MSR)); - err(" ADVERTISE: %04x\n", pic32mz_phyread(phyaddr, MII_ADVERTISE)); - err(" LPA: %04x\n", pic32mz_phyread(phyaddr, MII_LPA)); - err(" EXPANSION: %04x\n", pic32mz_phyread(phyaddr, MII_EXPANSION)); + nllinfo("PHY " PIC32MZ_PHYNAME ": %s\n", msg); + nllinfo(" MCR: %04x\n", pic32mz_phyread(phyaddr, MII_MCR)); + nllinfo(" MSR: %04x\n", pic32mz_phyread(phyaddr, MII_MSR)); + nllinfo(" ADVERTISE: %04x\n", pic32mz_phyread(phyaddr, MII_ADVERTISE)); + nllinfo(" LPA: %04x\n", pic32mz_phyread(phyaddr, MII_LPA)); + nllinfo(" EXPANSION: %04x\n", pic32mz_phyread(phyaddr, MII_EXPANSION)); #ifdef CONFIG_ETH0_PHY_KS8721 - err(" 10BTCR: %04x\n", pic32mz_phyread(phyaddr, MII_KS8721_10BTCR)); + nllinfo(" 10BTCR: %04x\n", pic32mz_phyread(phyaddr, MII_KS8721_10BTCR)); #endif } #endif @@ -2566,7 +2569,7 @@ static inline int pic32mz_phyreset(uint8_t phyaddr) } } - nerr("Reset failed. MCR: %04x\n", phyreg); + nerr("ERROR: Reset failed. MCR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2613,7 +2616,7 @@ static inline int pic32mz_phyautoneg(uint8_t phyaddr) } } - nerr("Auto-negotiation failed. MSR: %04x\n", phyreg); + nerr("ERROR: Auto-negotiation failed. MSR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2692,7 +2695,7 @@ static int pic32mz_phymode(uint8_t phyaddr, uint8_t mode) #endif } - nerr("Link failed. MSR: %04x\n", phyreg); + nerr("ERROR: Link failed. MSR: %04x\n", phyreg); return -ETIMEDOUT; } #endif @@ -2761,7 +2764,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) ret = pic32mz_phyreset(phyaddr); if (ret < 0) { - nerr("Failed to reset PHY at address %d\n", phyaddr); + nerr("ERROR: Failed to reset PHY at address %d\n", phyaddr); continue; } @@ -2794,7 +2797,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) { /* Failed to find PHY at any location */ - nerr("No PHY detected\n"); + nerr("ERROR: No PHY detected\n"); return -ENODEV; } ninfo("phyaddr: %d\n", phyaddr); @@ -2898,7 +2901,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) priv->pd_mode = PIC32MZ_100BASET_FD; break; default: - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } #elif defined(CONFIG_ETH0_PHY_DP83848C) @@ -2921,7 +2924,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) priv->pd_mode = PIC32MZ_10BASET_FD; break; default: - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } #elif defined(CONFIG_ETH0_PHY_LAN8720) || defined(CONFIG_ETH0_PHY_LAN8740) || defined(CONFIG_ETH0_PHY_LAN8740A) @@ -2966,7 +2969,7 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) } else { - nerr("Unrecognized mode: %04x\n", phyreg); + nerr("ERROR: Unrecognized mode: %04x\n", phyreg); return -ENODEV; } } @@ -2974,9 +2977,9 @@ static inline int pic32mz_phyinit(struct pic32mz_driver_s *priv) # warning "PHY Unknown: speed and duplex are bogus" #endif - nerr("%dBase-T %s duplex\n", - (priv->pd_mode & PIC32MZ_SPEED_MASK) == PIC32MZ_SPEED_100 ? 100 : 10, - (priv->pd_mode & PIC32MZ_DUPLEX_MASK) == PIC32MZ_DUPLEX_FULL ?"full" : "half"); + ninfo("%dBase-T %s duplex\n", + (priv->pd_mode & PIC32MZ_SPEED_MASK) == PIC32MZ_SPEED_100 ? 100 : 10, + (priv->pd_mode & PIC32MZ_DUPLEX_MASK) == PIC32MZ_DUPLEX_FULL ?"full" : "half"); /* Disable auto-configuration. Set the fixed speed/duplex mode. * (probably more than little redundant). diff --git a/arch/mips/src/pic32mz/pic32mz-exception.c b/arch/mips/src/pic32mz/pic32mz-exception.c index e9cda39ba8..1397d1063f 100644 --- a/arch/mips/src/pic32mz/pic32mz-exception.c +++ b/arch/mips/src/pic32mz/pic32mz-exception.c @@ -55,22 +55,6 @@ #include "chip/pic32mz-int.h" -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -106,88 +90,88 @@ uint32_t *pic32mz_exception(uint32_t *regs) switch (cause & CP0_CAUSE_EXCCODE_MASK) { case CP0_CAUSE_EXCCODE_INT: /* Interrupt */ - llinfo("EXCEPTION: Interrupt" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Interrupt" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TLBL: /* TLB exception (load or instruction fetch) */ - llinfo("EXCEPTION: TLB exception (load or instruction fetch)" - " CAUSE: %08x EPC:%08x\n", cause, epc); + alert("EXCEPTION: TLB exception (load or instruction fetch)" + " CAUSE: %08x EPC:%08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TLBS: /* TLB exception (store) */ - llinfo("EXCEPTION: TLB exception (store)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: TLB exception (store)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_ADEL: /* Address error exception (load or instruction fetch) */ - llinfo("EXCEPTION: Address error exception (load or instruction fetch)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Address error exception (load or instruction fetch)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_ADES: /* Address error exception (store) */ - llinfo("EXCEPTION: Address error exception (store)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Address error exception (store)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_IBE: /* Bus error exception (instruction fetch) */ - llinfo("EXCEPTION: Bus error exception (instruction fetch)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Bus error exception (instruction fetch)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_DBE: /* Bus error exception (data reference: load or store) */ - llinfo("EXCEPTION: Bus error exception (data reference: load or store)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Bus error exception (data reference: load or store)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_SYS: /* Syscall exception */ - llinfo("EXCEPTION: Syscall exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Syscall exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_BP: /* Breakpoint exception */ - llinfo("EXCEPTION: Breakpoint exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Breakpoint exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_RI: /* Reserved instruction exception */ - llinfo("EXCEPTION: Reserved instruction exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Reserved instruction exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_CPU: /* Coprocessor Unusable exception */ - llinfo("EXCEPTION: Coprocessor Unusable exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Coprocessor Unusable exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_OV: /* Arithmetic Overflow exception */ - llinfo("EXCEPTION: Arithmetic Overflow exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Arithmetic Overflow exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_TR: /* Trap exception */ - llinfo("EXCEPTION: Trap exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Trap exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_FPE: /* Floating point exception */ - llinfo("EXCEPTION: Floating point exception" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Floating point exception" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_C2E: /* Precise Coprocessor 2 exceptions */ - llinfo("EXCEPTION: Precise Coprocessor 2 exceptions" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Precise Coprocessor 2 exceptions" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_MDMX: /* MDMX Unusable (MIPS64) */ - llinfo("EXCEPTION: MDMX Unusable (MIPS64)" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: MDMX Unusable (MIPS64)" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_WATCH: /* WatchHi/WatchLo address */ - llinfo("EXCEPTION: WatchHi/WatchLo address" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: WatchHi/WatchLo address" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_MCHECK: /* Machine check */ - llinfo("EXCEPTION: Machine check" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Machine check" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; case CP0_CAUSE_EXCCODE_CACHEERR: /* Cache error */ - llinfo("EXCEPTION: Cache error" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Cache error" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; default: - llinfo("EXCEPTION: Unknown" - " CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: Unknown" + " CAUSE: %08x EPC: %08x\n", cause, epc); break; } #else - llerr("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc); + alert("EXCEPTION: CAUSE: %08x EPC: %08x\n", cause, epc); #endif #endif diff --git a/arch/mips/src/pic32mz/pic32mz-gpio.c b/arch/mips/src/pic32mz/pic32mz-gpio.c index db8c6e5df8..e4123eb0ce 100644 --- a/arch/mips/src/pic32mz/pic32mz-gpio.c +++ b/arch/mips/src/pic32mz/pic32mz-gpio.c @@ -307,7 +307,7 @@ bool pic32mz_gpioread(pinset_t pinset) * ****************************************************************************/ -#if defined(CONFIG_DEBUG_FEATURES) && defined(CONFIG_DEBUG_INFO) && defined(CONFIG_DEBUG_GPIO) +#if defined(CONFIG_DEBUG_INFO) && defined(CONFIG_DEBUG_GPIO) void pic32mz_dumpgpio(uint32_t pinset, const char *msg) { unsigned int port = pic32mz_portno(pinset); @@ -325,17 +325,17 @@ void pic32mz_dumpgpio(uint32_t pinset, const char *msg) /* The following requires exclusive access to the GPIO registers */ sched_lock(); - llerr("IOPORT%c pinset: %04x base: %08x -- %s\n", - 'A'+port, pinset, base, msg); - llerr(" TRIS: %08x PORT: %08x LAT: %08x ODC: %08x\n", - getreg32(base + PIC32MZ_IOPORT_TRIS_OFFSET), - getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET), - getreg32(base + PIC32MZ_IOPORT_LAT_OFFSET), - getreg32(base + PIC32MZ_IOPORT_ODC_OFFSET)); - llerr(" CNCON: %08x CNEN: %08x CNPUE: %08x\n", - getreg32(PIC32MZ_IOPORT_CNCON), - getreg32(PIC32MZ_IOPORT_CNEN), - getreg32(PIC32MZ_IOPORT_CNPUE)); + llinfo("IOPORT%c pinset: %04x base: %08x -- %s\n", + 'A'+port, pinset, base, msg); + llinfo(" TRIS: %08x PORT: %08x LAT: %08x ODC: %08x\n", + getreg32(base + PIC32MZ_IOPORT_TRIS_OFFSET), + getreg32(base + PIC32MZ_IOPORT_PORT_OFFSET), + getreg32(base + PIC32MZ_IOPORT_LAT_OFFSET), + getreg32(base + PIC32MZ_IOPORT_ODC_OFFSET)); + llinfo(" CNCON: %08x CNEN: %08x CNPUE: %08x\n", + getreg32(PIC32MZ_IOPORT_CNCON), + getreg32(PIC32MZ_IOPORT_CNEN), + getreg32(PIC32MZ_IOPORT_CNPUE)); sched_unlock(); } } diff --git a/arch/mips/src/pic32mz/pic32mz-gpio.h b/arch/mips/src/pic32mz/pic32mz-gpio.h index 1c967bc802..f7464a59d4 100644 --- a/arch/mips/src/pic32mz/pic32mz-gpio.h +++ b/arch/mips/src/pic32mz/pic32mz-gpio.h @@ -253,7 +253,7 @@ void pic32mz_gpioirqdisable(pinset_t pinset); * ************************************************************************************/ -#ifdef CONFIG_DEBUG_GPIO +#if defined(CONFIG_DEBUG_INFO) && defined(CONFIG_DEBUG_GPIO) void pic32mz_dumpgpio(uint32_t pinset, const char *msg); #else # define pic32mz_dumpgpio(p,m) diff --git a/arch/mips/src/pic32mz/pic32mz-spi.c b/arch/mips/src/pic32mz/pic32mz-spi.c index 956128eaeb..633698787c 100644 --- a/arch/mips/src/pic32mz/pic32mz-spi.c +++ b/arch/mips/src/pic32mz/pic32mz-spi.c @@ -71,13 +71,11 @@ #ifdef CONFIG_DEBUG_SPI # define spierr llerr -# ifdef CONFIG_DEBUG_INFO -# define spiinfo llerr -# else -# define spiinfo(x...) -# endif +# define spiwarn llwarn +# define spiinfo llinfo #else # define spierr(x...) +# define spiwarn(x...) # define spiinfo(x...) #endif @@ -496,7 +494,7 @@ static bool spi_checkreg(struct pic32mz_dev_s *priv, uintptr_t regaddr, { /* Yes... show how many times we did it */ - llerr("...[Repeats %d times]...\n", priv->ntimes); + llinfo("...[Repeats %d times]...\n", priv->ntimes); } /* Save information about the new access */ @@ -546,8 +544,8 @@ static uint32_t spi_getreg(FAR struct pic32mz_dev_s *priv, { /* Yes.. */ - llerr("%08lx->%08lx\n", - (unsigned long)regaddr, (unsigned long)regval); + llinfo("%08lx->%08lx\n", + (unsigned long)regaddr, (unsigned long)regval); } /* Return the value read */ @@ -588,8 +586,8 @@ static void spi_putaddr(FAR struct pic32mz_dev_s *priv, uintptr_t regaddr, { /* Yes.. */ - llerr("%08lx<-%08lx\n", - (unsigned long)regaddr, (unsigned long)regval); + llinfo("%08lx<-%08lx\n", + (unsigned long)regaddr, (unsigned long)regval); } /* Write the value to the register */ @@ -887,7 +885,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency) priv->frequency = frequency; priv->actual = actual; - spierr("New frequency: %d Actual: %d\n", frequency, actual); + spiinfo("New frequency: %d Actual: %d\n", frequency, actual); return actual; } @@ -1025,7 +1023,7 @@ static void spi_setbits(FAR struct spi_dev_s *dev, int nbits) } else { - spierr("Unsupported nbits: %d\n", nbits); + spierr("ERROR: Unsupported nbits: %d\n", nbits); return; } @@ -1275,7 +1273,7 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port) else #endif { - spierr("Unsuppport port: %d\n", port); + spierr("ERROR: Unsuppport port: %d\n", port); return NULL; } @@ -1311,7 +1309,7 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port) ret = irq_attach(priv->config->rxirq, spi_interrupt); if (ret < 0) { - spierr("Failed to attach RX interrupt: %d port: %d\n", + spierr("ERROR: Failed to attach RX interrupt: %d port: %d\n", priv->config->rxirq, port); goto errout; } @@ -1319,7 +1317,7 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port) ret = irq_attach(priv->config->txirq, spi_interrupt); if (ret < 0) { - spierr("Failed to attach TX interrupt: %d port: %d\n", + spierr("ERROR: Failed to attach TX interrupt: %d port: %d\n", priv->tconfig->xirq, port); goto errout_with_rxirq; } @@ -1327,7 +1325,7 @@ FAR struct spi_dev_s *pic32mz_spibus_initialize(int port) ret = irq_attach(priv->config->firq, spi_interrupt); if (ret < 0) { - spierr("Failed to attach fault interrupt: %d port: %d\n", + spierr("ERROR: Failed to attach fault interrupt: %d port: %d\n", priv->config->firq, port); goto errout_with_txirq; } diff --git a/arch/rgmp/src/x86/com.c b/arch/rgmp/src/x86/com.c index fced9f66e8..495aa4b692 100644 --- a/arch/rgmp/src/x86/com.c +++ b/arch/rgmp/src/x86/com.c @@ -263,23 +263,27 @@ static int up_setup(struct uart_dev_s *dev) } // Set speed; requires DLAB latch + outb(base+COM_LCR, COM_LCR_DLAB); data.val = 115200 / priv->baud; outb(base+COM_DLL, data.sep.low); outb(base+COM_DLM, data.sep.high); // set data bits, stop bit, parity; turn off DLAB latch + outb(base+COM_LCR, priv->lcr.val); // OUT2 must be set to enable interrupt + outb(base+COM_MCR, COM_MCR_OUT2); // setup FIFO + outb(base+COM_FCR, 1); // disable COM interrupts - outb(base+COM_IER, 0); + outb(base+COM_IER, 0); return OK; }