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arm64_mmu.c: Fix kernel L1 page table size

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The kernel L1 page table must be at least 1 page
This commit is contained in:
Ville Juven 2024-09-04 12:25:47 +03:00 committed by Xiang Xiao
parent 4149e45450
commit 080f9ede45
1 changed files with 10 additions and 2 deletions
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12
arch/arm64/src/common/arm64_mmu.c
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@ -131,6 +131,14 @@
#define NUM_BASE_LEVEL_ENTRIES GET_NUM_BASE_LEVEL_ENTRIES( \
CONFIG_ARM64_VA_BITS)
#ifdef CONFIG_BUILD_KERNEL
#define BASE_XLAT_TABLE_SIZE XLAT_TABLE_ENTRIES
#define BASE_XLAT_TABLE_ALIGN PAGE_SIZE
#else
#define BASE_XLAT_TABLE_SIZE NUM_BASE_LEVEL_ENTRIES
#define BASE_XLAT_TABLE_ALIGN NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t)
#endif
#if (CONFIG_ARM64_PA_BITS == 48)
#define TCR_PS_BITS TCR_PS_BITS_256TB
#elif (CONFIG_ARM64_PA_BITS == 44)
@ -149,8 +157,8 @@
* Private Data
****************************************************************************/
static uint64_t base_xlat_table[NUM_BASE_LEVEL_ENTRIES] aligned_data(
NUM_BASE_LEVEL_ENTRIES * sizeof(uint64_t));
static uint64_t base_xlat_table[BASE_XLAT_TABLE_SIZE]
aligned_data(BASE_XLAT_TABLE_ALIGN);
static uint64_t xlat_tables[CONFIG_MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
aligned_data(XLAT_TABLE_ENTRIES * sizeof(uint64_t));