From 081d3f989dc22e55347f602166f7d1eb0e953259 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Mon, 3 Jun 2013 11:23:41 -0600 Subject: [PATCH] Add vector and chip cability definitions for the SAM4L family --- ChangeLog | 4 + arch/arm/include/sam34/chip.h | 148 ++++++++++++++++++++++-- arch/arm/src/sam34/chip.h | 15 +++ arch/arm/src/sam34/chip/sam3u_vectors.h | 3 - arch/arm/src/sam34/chip/sam4l_vectors.h | 136 ++++++++++++++++++++++ arch/arm/src/sam34/chip/sam_pinmap.h | 2 +- arch/arm/src/sam34/sam_dmac.c | 20 ++-- arch/arm/src/sam34/sam_vectors.S | 4 + 8 files changed, 310 insertions(+), 22 deletions(-) create mode 100644 arch/arm/src/sam34/chip/sam4l_vectors.h diff --git a/ChangeLog b/ChangeLog index 5de5652ae9..0ee3d7495c 100644 --- a/ChangeLog +++ b/ChangeLog @@ -4873,3 +4873,7 @@ * arch/arm/include/sam34/sam4l_irq.h and arch/arm/src/sam34/chip/sam4l_memorymap.h: Add interrupt and memory map definitions for the AT91SAM4L (2013-6-3). + * arch/arm/src/sam34/chip/sam4l_vectors.h and arm/src/sam34/sam_vectors.S: + Add interrupt vector support for the SAM4L family (2013-6-3). + * arch/include/sam34/chip.h: Add chip definitions for the SAM4L + family (2013-6-3). diff --git a/arch/arm/include/sam34/chip.h b/arch/arm/include/sam34/chip.h index 9cc7d1b7c5..ce56fd41ed 100644 --- a/arch/arm/include/sam34/chip.h +++ b/arch/arm/include/sam34/chip.h @@ -48,20 +48,152 @@ /* Get customizations for each supported chip */ -#ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E +/* AT91SAM3U Family *****************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_AT91SAM3U4E) + /* Internal memory */ -# define CONFIG_SAM34_SRAM0_SIZE 0x00008000 /* 32Kb */ -# define CONFIG_SAM34_SRAM1_SIZE 0x00004000 /* 16Kb */ -# define CONFIG_SAM34_NFCSRAM_SIZE 0x00001000 /* 4Kb */ +# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (16*1024) /* 16Kb */ +# define CONFIG_SAM34_NFCSRAM_SIZE (4*1024) /* 4Kb */ -/* DMA */ +/* Peripherals */ -# define CONFIG_SAM34_NDMACHAN 4 /* 4 DMA Channels */ +# define SAM34_NDMACHAN 4 /* 4 DMA Channels */ +# define SAM34_NMCI2 1 /* 1 memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 1 /* One USB high speed device */ +# define SAM32_NUDPFS 0 /* No USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ -/* Memory card interface */ +/* AT91SAM4L Family *****************************************************************/ +/* Sub-family differences: + * + * FEATURE ATSAM4LCxx ATSAM4LSxx + * ----------------------- ------------- ------------- + * SEGMENT LCD Yes No + * AESA Yes No + * USB Device + Host Device Only + * + * Note: The SEGMENT LCD capability varies with packaging. + * + * FEATURE ATSAM4Lx2x ATSAM4Lx4x + * ----------------------- ------------- ------------- + * FLASH 256KB 128KB + * SRAM 32KB 32KB + * + * Packaging differences: + * + * FEATURE ATSAM4LxxC ATSAM4LxxB ATSAM4LxxA + * ----------------------- ---------- ---------- ---------- + * Number of Pins 100 64 48 + * Max Frequency 48MHz 48MHz 48MHz + * SEGMENT LCD 4x40 4x23 4x13 + * GPIO 75 43 27 + * High-drive pins 6 3 1 + * External Interrupts 8+NMI 8+NMI 8+NMI + * TWI Masters 2 2 1 + * TWI Master/Slave 2 2 1 + * USART 4 4 3 + * PICOUART 1 1 1 + * Peripheral DMA Channels 16 16 16 + * Peripheral Even System 1 1 1 + * SPI 1 1 1 + * Asynchronous Timers 1 1 1 + * Timer/Counter Channels 6 3 3 + * Parallel Capture Inputs 8 8 8 + * Frequency Meter 1 1 1 + * Watchdog Timer 1 1 1 + * Power Manager 1 1 1 + * Glue Logic LUT 2 2 1 + * ADC 15-channel 7-channel 3-channel + * DAC 1-channel 1-channel 1-channel + * Analog Comparators 4 2 1 + * CATB Sensors 32 32 26 + * Audio Bitstream DAC 1 1 1 + * IIS Controller 1 1 1 + * Packages TQFP/VFBGA TQFP/QFN TQFP/QFN + */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LC2) + +/* Internal memory */ + +# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ +# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 1 /* 1 segment LCD interface */ +# define SAM32_NAESA 1 /* 1 advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LC4) + +/* Internal memory */ + +# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ +# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 1 /* 1 segment LCD interface */ +# define SAM32_NAESA 1 /* 1 advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LS2) + +/* Internal memory */ + +# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ +# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ + +#elif defined(CONFIG_ARCH_CHIP_AT91SAM4LS4) + +/* Internal memory */ + +# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */ +# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */ +# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */ +# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */ + +/* Peripherals */ + +# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */ +# define SAM34_NMCI2 0 /* No memory card interface */ +# define SAM32_NSLCD 0 /* No segment LCD interface */ +# define SAM32_NAESA 0 /* No advanced encryption standard */ +# define SAM32_NUDPHS 0 /* No USB high speed device */ +# define SAM32_NUDPFS 1 /* 1 USB full speed device */ +# define SAM32_NUHPFS 0 /* No USB full speed embedded host */ -# define CONFIG_SAM34_MCI2 1 #else # error "Unknown SAM3/4 chip type" #endif diff --git a/arch/arm/src/sam34/chip.h b/arch/arm/src/sam34/chip.h index cd5f76d89b..3c92f53ef6 100644 --- a/arch/arm/src/sam34/chip.h +++ b/arch/arm/src/sam34/chip.h @@ -49,6 +49,21 @@ #include #include "chip/sam_memorymap.h" +/* If the common ARMv7-M vector handling logic is used, then include the required + * vector definitions as well. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR +# if defined(CONFIG_ARCH_CHIP_SAM3U) +# include "chip/sam3u_vectors.h" +# elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_vectors.h" +# include "chip/sam4l_memorymap.h" +# else +# error Unrecognized SAM architecture +# endif +#endif + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ diff --git a/arch/arm/src/sam34/chip/sam3u_vectors.h b/arch/arm/src/sam34/chip/sam3u_vectors.h index d1828ddd81..fd4c1a39e6 100644 --- a/arch/arm/src/sam34/chip/sam3u_vectors.h +++ b/arch/arm/src/sam34/chip/sam3u_vectors.h @@ -41,9 +41,6 @@ * (upper-case) IRQ number as defined in arch/arm/include/sam/sam3u_irq.h. * sam_vectors.S will defined the VECTOR in different ways in order to generate * the interrupt vectors and handlers in their final form. - * - * - * Vectors for low and medium density devices */ /* If the common ARMv7-M vector handling is used, then all it needs is the following diff --git a/arch/arm/src/sam34/chip/sam4l_vectors.h b/arch/arm/src/sam34/chip/sam4l_vectors.h new file mode 100644 index 0000000000..b4158965ff --- /dev/null +++ b/arch/arm/src/sam34/chip/sam4l_vectors.h @@ -0,0 +1,136 @@ +/************************************************************************************************ + * arch/arm/src/sam34/chip/sam4l_vectors.h + * + * Copyright (C) 2013 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************************/ + +/************************************************************************************************ + * Pre-processor Definitions + ************************************************************************************************/ +/* This file is included by sam_vectors.S. It provides the macro VECTOR that + * supplies ach SAM3U vector in terms of a (lower-case) ISR label and an + * (upper-case) IRQ number as defined in arch/arm/include/sam/sam4l_irq.h. + * sam_vectors.S will defined the VECTOR in different ways in order to generate + * the interrupt vectors and handlers in their final form. + */ + +/* If the common ARMv7-M vector handling is used, then all it needs is the following + * definition that provides the number of supported vectors. + */ + +#ifdef CONFIG_ARMV7M_CMNVECTOR + +/* Reserve 80 interrupt table entries for I/O interrupts. */ + +# define ARMV7M_PERIPHERAL_INTERRUPTS 80 + +#else + VECTOR(sam_hflashc, SAM_IRQ_HFLASHC) /* Vector 16+0: Flash Controller */ + VECTOR(sam_pdca0, SAM_IRQ_PDCA0) /* Vector 16+1: Peripheral DMA Controller 0 */ + VECTOR(sam_pdca1, SAM_IRQ_PDCA1) /* Vector 16+2: Peripheral DMA Controller 1 */ + VECTOR(sam_pdca2, SAM_IRQ_PDCA2) /* Vector 16+3: Peripheral DMA Controller 2 */ + VECTOR(sam_pdca3, SAM_IRQ_PDCA3) /* Vector 16+4: Peripheral DMA Controller 3 */ + VECTOR(sam_pdca4, SAM_IRQ_PDCA4) /* Vector 16+5: Peripheral DMA Controller 4 */ + VECTOR(sam_pdca5, SAM_IRQ_PDCA5) /* Vector 16+6: Peripheral DMA Controller 5 */ + VECTOR(sam_pdca6, SAM_IRQ_PDCA6) /* Vector 16+7: Peripheral DMA Controller 6 */ + VECTOR(sam_pdca7, SAM_IRQ_PDCA7) /* Vector 16+8: Peripheral DMA Controller 7 */ + VECTOR(sam_pdca8, SAM_IRQ_PDCA8) /* Vector 16+9: Peripheral DMA Controller 8 */ + VECTOR(sam_pdca9, SAM_IRQ_PDCA9) /* Vector 16+10: Peripheral DMA Controller 9 */ + VECTOR(sam_pdca10, SAM_IRQ_PDCA10) /* Vector 16+11: Peripheral DMA Controller 10 */ + VECTOR(sam_pdca11, SAM_IRQ_PDCA11) /* Vector 16+12: Peripheral DMA Controller 11 */ + VECTOR(sam_pdca12, SAM_IRQ_PDCA12) /* Vector 16+13: Peripheral DMA Controller 12 */ + VECTOR(sam_pdca13, SAM_IRQ_PDCA13) /* Vector 16+14: Peripheral DMA Controller 13 */ + VECTOR(sam_pdca14, SAM_IRQ_PDCA14) /* Vector 16+15: Peripheral DMA Controller 14 */ + VECTOR(sam_pdca15, SAM_IRQ_PDCA15) /* Vector 16+16: Peripheral DMA Controller 15 */ + VECTOR(sam_crccu, SAM_IRQ_CRCCU) /* Vector 16+17: CRC Calculation Unit */ + VECTOR(sam_usbc, SAM_IRQ_USBC) /* Vector 16+18: USB 2.0 Interface */ + VECTOR(sam_pevc_tr, SAM_IRQ_PEVC_TR) /* Vector 16+19: Peripheral Event Controller TR */ + VECTOR(sam_pevc_ov, SAM_IRQ_PEVC_OV) /* Vector 16+20: Peripheral Event Controller OV */ + VECTOR(sam_aesa, SAM_IRQ_AESA) /* Vector 16+21: Advanced Encryption Standard */ + VECTOR(sam_pm, SAM_IRQ_PM) /* Vector 16+22: Power Manager */ + VECTOR(sam_scif, SAM_IRQ_SCIF) /* Vector 16+23: System Control Interface */ + VECTOR(sam_freqm, SAM_IRQ_FREQM) /* Vector 16+24: Frequency Meter */ + VECTOR(sam_gpio0, SAM_IRQ_GPIO0) /* Vector 16+25: General-Purpose Input/Output Controller 0 */ + VECTOR(sam_gpio1, SAM_IRQ_GPIO1) /* Vector 16+26: General-Purpose Input/Output Controller 1 */ + VECTOR(sam_gpio2, SAM_IRQ_GPIO2) /* Vector 16+27: General-Purpose Input/Output Controller 2 */ + VECTOR(sam_gpio3, SAM_IRQ_GPIO3) /* Vector 16+28: General-Purpose Input/Output Controller 3 */ + VECTOR(sam_gpio4, SAM_IRQ_GPIO4) /* Vector 16+29: General-Purpose Input/Output Controller 4 */ + VECTOR(sam_gpio5, SAM_IRQ_GPIO5) /* Vector 16+30: General-Purpose Input/Output Controller 5 */ + VECTOR(sam_gpio6, SAM_IRQ_GPIO6) /* Vector 16+31: General-Purpose Input/Output Controller 6 */ + VECTOR(sam_gpio7, SAM_IRQ_GPIO7) /* Vector 16+32: General-Purpose Input/Output Controller 7 */ + VECTOR(sam_gpio8, SAM_IRQ_GPIO8) /* Vector 16+33: General-Purpose Input/Output Controller 8 */ + VECTOR(sam_gpio9, SAM_IRQ_GPIO9) /* Vector 16+34: General-Purpose Input/Output Controller 9 */ + VECTOR(sam_gpio10, SAM_IRQ_GPIO10) /* Vector 16+35: General-Purpose Input/Output Controller 10 */ + VECTOR(sam_gpio11, SAM_IRQ_GPIO11) /* Vector 16+36: General-Purpose Input/Output Controller 11 */ + VECTOR(sam_bpm, SAM_IRQ_BPM) /* Vector 16+37: Backup Power Manager */ + VECTOR(sam_bscif, SAM_IRQ_BSCIF) /* Vector 16+38: Backup System Control Interface */ + VECTOR(sam_ast_alarm, SAM_IRQ_AST_ALARM) /* Vector 16+39: Asynchronous Timer ALARM */ + VECTOR(sam_ast_per, SAM_IRQ_AST_PER) /* Vector 16+40: Asynchronous Timer PER */ + VECTOR(sam_ast_ovf, SAM_IRQ_AST_OVF) /* Vector 16+41: Asynchronous Timer OVF */ + VECTOR(sam_ast_ready, SAM_IRQ_AST_READY) /* Vector 16+42: Asynchronous Timer READY */ + VECTOR(sam_ast_clkready, SAM_IRQ_AST_CLKREADY) /* Vector 16+43: Asynchronous Timer CLKREADY */ + VECTOR(sam_wdt, SAM_IRQ_WDT) /* Vector 16+44: Watchdog Timer */ + VECTOR(sam_eic1, SAM_IRQ_EIC1) /* Vector 16+45: External Interrupt Controller 1 */ + VECTOR(sam_eic2, SAM_IRQ_EIC2) /* Vector 16+46: External Interrupt Controller 2 */ + VECTOR(sam_eic3, SAM_IRQ_EIC3) /* Vector 16+47: External Interrupt Controller 3 */ + VECTOR(sam_eic4, SAM_IRQ_EIC4) /* Vector 16+48: External Interrupt Controller 4 */ + VECTOR(sam_eic5, SAM_IRQ_EIC5) /* Vector 16+49: External Interrupt Controller 5 */ + VECTOR(sam_eic6, SAM_IRQ_EIC6) /* Vector 16+50: External Interrupt Controller 6 */ + VECTOR(sam_eic7, SAM_IRQ_EIC7) /* Vector 16+51: External Interrupt Controller 7 */ + VECTOR(sam_eic8, SAM_IRQ_EIC8) /* Vector 16+52: External Interrupt Controller 8 */ + VECTOR(sam_iisc, SAM_IRQ_IISC) /* Vector 16+53: Inter-IC Sound (I2S) Controller */ + VECTOR(sam_spi, SAM_IRQ_SPI) /* Vector 16+54: Serial Peripheral Interface */ + VECTOR(sam_tc00, SAM_IRQ_TC00) /* Vector 16+55: Timer/Counter 0 */ + VECTOR(sam_tc01, SAM_IRQ_TC01) /* Vector 16+56: Timer/Counter 1 */ + VECTOR(sam_tc02, SAM_IRQ_TC02) /* Vector 16+57: Timer/Counter 2 */ + VECTOR(sam_tc10, SAM_IRQ_TC10) /* Vector 16+58: Timer/Counter 10 */ + VECTOR(sam_tc11, SAM_IRQ_TC11) /* Vector 16+59: Timer/Counter 11 */ + VECTOR(sam_tc12, SAM_IRQ_TC12) /* Vector 16+60: Timer/Counter 12 */ + VECTOR(sam_twim0, SAM_IRQ_TWIM0) /* Vector 16+61: Two-wire Master Interface TWIM0 */ + VECTOR(sam_twis0, SAM_IRQ_TWIS0) /* Vector 16+62: Two-wire Slave Interface TWIS0 */ + VECTOR(sam_twim1, SAM_IRQ_TWIM1) /* Vector 16+63: Two-wire Master Interface TWIM1 */ + VECTOR(sam_twis1, SAM_IRQ_TWIS1) /* Vector 16+64: Two-wire Slave Interface TWIS1 */ + VECTOR(sam_usart0, SAM_IRQ_USART0) /* Vector 16+65: USART0 */ + VECTOR(sam_usart1, SAM_IRQ_USART1) /* Vector 16+66: USART1 */ + VECTOR(sam_usart2, SAM_IRQ_USART2) /* Vector 16+67: USART2 */ + VECTOR(sam_usart3, SAM_IRQ_USART3) /* Vector 16+68: USART3 */ + VECTOR(sam_adcife, SAM_IRQ_ADCIFE) /* Vector 16+69: ADC controller interface */ + VECTOR(sam_dacc, SAM_IRQ_DACC) /* Vector 16+70: DAC Controller */ + VECTOR(sam_acifc, SAM_IRQ_ACIFC) /* Vector 16+71: Analog Comparator Interface */ + VECTOR(sam_abdacb, SAM_IRQ_ABDACB) /* Vector 16+72: Audio Bitstream DAC */ + VECTOR(sam_trng, SAM_IRQ_TRNG) /* Vector 16+73: True Random Number Generator */ + VECTOR(sam_parc, SAM_IRQ_PARC) /* Vector 16+74: Parallel Capture */ + VECTOR(sam_catb, SAM_IRQ_CATB) /* Vector 16+75: Capacitive Touch Module B */ + VECTOR(sam_twim2, SAM_IRQ_TWIM2) /* Vector 16+77: Two-wire Master Interface */ + VECTOR(sam_twim3, SAM_IRQ_TWIM3) /* Vector 16+78: Two-wire Master Interface */ + VECTOR(sam_lcdca, SAM_IRQ_LCDCA) /* Vector 16+79: LCD Controller A */ +#endif diff --git a/arch/arm/src/sam34/chip/sam_pinmap.h b/arch/arm/src/sam34/chip/sam_pinmap.h index 2adfac974f..6adb547bf7 100644 --- a/arch/arm/src/sam34/chip/sam_pinmap.h +++ b/arch/arm/src/sam34/chip/sam_pinmap.h @@ -46,7 +46,7 @@ #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_pinmap.h" #else -# Unrecognized SAM architecture +# error Unrecognized SAM architecture #endif #endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PINMAP_H */ diff --git a/arch/arm/src/sam34/sam_dmac.c b/arch/arm/src/sam34/sam_dmac.c index 75d6927542..b11199fb17 100644 --- a/arch/arm/src/sam34/sam_dmac.c +++ b/arch/arm/src/sam34/sam_dmac.c @@ -78,14 +78,14 @@ /* Check the number of link list descriptors to allocate */ #ifndef CONFIG_SAM34_NLLDESC -# define CONFIG_SAM34_NLLDESC CONFIG_SAM34_NDMACHAN +# define CONFIG_SAM34_NLLDESC SAM34_NDMACHAN #endif -#if CONFIG_SAM34_NLLDESC < CONFIG_SAM34_NDMACHAN -# warning "At least CONFIG_SAM34_NDMACHAN descriptors must be allocated" +#if CONFIG_SAM34_NLLDESC < SAM34_NDMACHAN +# warning "At least SAM34_NDMACHAN descriptors must be allocated" # undef CONFIG_SAM34_NLLDESC -# define CONFIG_SAM34_NLLDESC CONFIG_SAM34_NDMACHAN +# define CONFIG_SAM34_NLLDESC SAM34_NDMACHAN #endif /* Register values **********************************************************/ @@ -150,15 +150,15 @@ static struct dma_linklist_s g_linklist[CONFIG_SAM34_NLLDESC]; /* This array describes the state of each DMA */ -static struct sam_dma_s g_dma[CONFIG_SAM34_NDMACHAN] = +static struct sam_dma_s g_dma[SAM34_NDMACHAN] = { #ifdef CONFIG_ARCH_CHIP_AT91SAM3U4E /* the AT91SAM3U4E has four DMA channels. The FIFOs for channels 0-2 are * 8 bytes in size; channel 3 is 32 bytes. */ -#if CONFIG_SAM34_NDMACHAN != 4 -# error "Logic here assumes CONFIG_SAM34_NDMACHAN is 4" +#if SAM34_NDMACHAN != 4 +# error "Logic here assumes SAM34_NDMACHAN is 4" #endif { @@ -1099,7 +1099,7 @@ static int sam_dmainterrupt(int irq, void *context) { /* Yes.. Check each bit to see which channel has interrupted */ - for (chndx = 0; chndx < CONFIG_SAM34_NDMACHAN; chndx++) + for (chndx = 0; chndx < SAM34_NDMACHAN; chndx++) { /* Are any interrupts pending for this channel? */ @@ -1185,7 +1185,7 @@ void weak_function up_dmainitialize(void) /* Initialize semaphores */ sem_init(&g_chsem, 0, 1); - sem_init(&g_dsem, 0, CONFIG_SAM34_NDMACHAN); + sem_init(&g_dsem, 0, SAM34_NDMACHAN); } /**************************************************************************** @@ -1224,7 +1224,7 @@ DMA_HANDLE sam_dmachannel(uint32_t dmach_flags) dmach = NULL; sam_takechsem(); - for (chndx = 0; chndx < CONFIG_SAM34_NDMACHAN; chndx++) + for (chndx = 0; chndx < SAM34_NDMACHAN; chndx++) { struct sam_dma_s *candidate = &g_dma[chndx]; if (!candidate->inuse && diff --git a/arch/arm/src/sam34/sam_vectors.S b/arch/arm/src/sam34/sam_vectors.S index a80df32632..007367857c 100644 --- a/arch/arm/src/sam34/sam_vectors.S +++ b/arch/arm/src/sam34/sam_vectors.S @@ -132,6 +132,8 @@ sam_vectors: #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_vectors.h" #else # Unrecognized SAM architecture #endif @@ -165,6 +167,8 @@ handlers: #if defined(CONFIG_ARCH_CHIP_SAM3U) # include "chip/sam3u_vectors.h" +#elif defined(CONFIG_ARCH_CHIP_SAM4L) +# include "chip/sam4l_vectors.h" #else # Unrecognized SAM architecture #endif