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arch/arm/src/tiva: Implements an EEPROM driver in compliance with MTD driver as provided by NUTTX for TM4C1294. The EEPROM driver currently supports only two functionalities - read bytes(multiple of 4) and write bytes (multiple of 4).

Browse Source 
Squashed commit of the following:

Author: Gregory Nutt <gnutt@nuttx.org>
    Fix some spacing
    arch/arm/src/tiva:  Verify that the EEPROM driver at least builds.
    arch/arm/src/tiva:  Move unused function added to tm4c129_syscontrol.c to tiva_eeprom.c where it is actually used.
    arch/arm/src/tiva:  Reorganize EEPROM register definitions so that the file organization is more like other platforms.
    arch/arm/src/tiva:  Trying to resolve EEPROM register addressing.  Still some issues.
    arch/arm/src/tiva:  Ran uncrustify on tiva_eeprom.c
    arch/arm/src/tiva:  EEPROM driver is a little closer to coding standard.  Still a way to go.

Author: Shirshak Sengupta <sgshirshak@gmail.com>
    arch/arm/src/tiva: Implemented EEPROM driver in compliance with MTD driver as provided by NUTTX for TM4C1294. The EEPROM driver needs to be initialized by calling the function tiva_EEPROMInit The EEPROM driver currently supports only two functionalities - read bytes(multiple of 4) and write bytes (multiple of 4). Note - Rest of the features of EEPROM will be implemented in the future.
This commit is contained in:
Shirshak Sengupta 2018-04-29 11:04:09 -06:00 committed by Gregory Nutt
parent 9a1277bd8f
commit 0835143537
11 changed files with 1224 additions and 182 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm/src/tiva/Kconfig
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@ -100,6 +100,7 @@ config ARCH_CHIP_TM4C1294NC
select ARCH_CHIP_TM4C
select ARCH_CHIP_TM4C129
select TIVA_HAVE_ETHERNET
select TIVA_HAVE_EEPROM
config ARCH_CHIP_TM4C129XNC
bool "TM4C129XNC"
@ -292,6 +293,10 @@ config TIVA_HAVE_SSI3
bool
default n
config TIVA_HAVE_EEPROM
bool
default n
config TIVA_HAVE_ETHERNET
bool
default n
@ -537,6 +542,13 @@ config TIVA_FLASH
---help---
Enable MTD driver support for internal FLASH.
config TIVA_EEPROM
bool "Internal EEPROM driver"
default n
depends on TIVA_HAVE_EEPROM && EXPERIMENTAL
---help---
Enable MTD driver support for internal EEPROM.
endmenu
config TIVA_RAMVBAR

7
arch/arm/src/tiva/Make.defs
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@ -1,7 +1,8 @@
############################################################################
# arch/arm/src/tiva/Make.defs
#
# Copyright (C) 2009-2011, 2013-2014 Gregory Nutt. All rights reserved.
# Copyright (C) 2009-2011, 2013-2014, 2018 Gregory Nutt. All rights
# reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
@ -123,3 +124,7 @@ endif
ifeq ($(CONFIG_TIVA_FLASH),y)
CHIP_CSRCS += tiva_flash.c
endif
ifeq ($(CONFIG_TIVA_EEPROM),y)
CHIP_CSRCS += tiva_eeprom.c
endif

17
arch/arm/src/tiva/chip.h
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@ -53,23 +53,8 @@
#include "chip/tiva_ssi.h" /* SSI modules */
#include "chip/tiva_ethernet.h" /* Ethernet MAC and PHY */
#include "chip/tiva_flash.h" /* FLASH */
#include "chip/tiva_eeprom.h" /* EEPROM */
#include "chip/tiva_timer.h" /* Timer */
#include "chip/tiva_adc.h" /* ADC */
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/************************************************************************************
* Public Types
************************************************************************************/
/************************************************************************************
* Public Data
************************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_TIVA_CHIP_H */

4
arch/arm/src/tiva/chip/lm4f_syscontrol.h
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@ -84,6 +84,7 @@
#define TIVA_SYSCON_PPEEPROM_OFFSET 0x358 /* EEPROM Peripheral Present */
#define TIVA_SYSCON_PPWTIMER_OFFSET 0x35c /* 32/64-Bit Wide Timer Peripheral Present */
#define TIVA_SYSCON_SR_OFFSET 0x500
#define TIVA_SYSCON_SRWD_OFFSET 0x500 /* Watchdog Timer Software Reset */
#define TIVA_SYSCON_SRTIMER_OFFSET 0x504 /* 16/32-Bit Timer Software Reset */
#define TIVA_SYSCON_SRGPIO_OFFSET 0x508 /* GPIO Software Reset */
@ -99,6 +100,7 @@
#define TIVA_SYSCON_SREEPROM_OFFSET 0x558 /* EEPROM Software Reset */
#define TIVA_SYSCON_SRWTIMER_OFFSET 0x55c /* 32/64-Bit Wide Timer Software Reset */
#define TIVA_SYSCON_RCGC_OFFSET 0x600
#define TIVA_SYSCON_RCGCWD_OFFSET 0x600 /* Watchdog Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCTIMER_OFFSET 0x604 /* 16/32-Bit Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCGPIO_OFFSET 0x608 /* GPIO Run Mode Clock Gating Control*/
@ -228,6 +230,7 @@
#define TIVA_SYSCON_PPEEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_PPEEPROM_OFFSET)
#define TIVA_SYSCON_PPWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_PPWTIMER_OFFSET)
#define TIVA_SYSCON_SR_BASE (TIVA_SYSCON_BASE + TIVA_SYSCON_SR_OFFSET)
#define TIVA_SYSCON_SRWD (TIVA_SYSCON_BASE + TIVA_SYSCON_SRWD_OFFSET)
#define TIVA_SYSCON_SRTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_SRTIMER_OFFSET)
#define TIVA_SYSCON_SRGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_SRGPIO_OFFSET)
@ -243,6 +246,7 @@
#define TIVA_SYSCON_SREEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_SREEPROM_OFFSET)
#define TIVA_SYSCON_SRWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_SRWTIMER_OFFSET)
#define TIVA_SYSCON_RCGC_BASE (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC_OFFSET)
#define TIVA_SYSCON_RCGCWD (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCWD_OFFSET)
#define TIVA_SYSCON_RCGCTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCTIMER_OFFSET)
#define TIVA_SYSCON_RCGCGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCGPIO_OFFSET)

203
arch/arm/src/tiva/chip/tiva_eeprom.h Normal file
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@ -0,0 +1,203 @@
/************************************************************************************
* arch/arm/src/tiva/chip/tiva_eeprom.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Shirshak Sengupta <sgshirshak@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_CHIP_TIVA_EEPROM_H
#define __ARCH_ARM_SRC_TIVA_CHIP_TIVA_EEPROM_H
/************************************************************************************
* Included Files
************************************************************************************/
/* Register Offsets *****************************************************************/
#define TIVA_EEPROM_EESIZE_OFFSET 0x0000 /* EEPROM Size Information */
#define TIVA_EEPROM_EEBLOCK_OFFSET 0x0004 /* EEPROM Current Block */
#define TIVA_EEPROM_EEOFFSET_OFFSET 0x0008 /* EEPROM Current Offset */
#define TIVA_EEPROM_EERDWR_OFFSET 0x0010 /* EEPROM Read-Write */
#define TIVA_EEPROM_EERDWRINC_OFFSET 0x0014 /* EEPROM Read-Write with Increment */
#define TIVA_EEPROM_EEDONE_OFFSET 0x0018 /* EEPROM Done Status */
#define TIVA_EEPROM_EESUPP_OFFSET 0x001c /* EEPROM Support Control and Status */
#define TIVA_EEPROM_EEUNLOCK_OFFSET 0x0020 /* EEPROM Unlock */
#define TIVA_EEPROM_EEPROT_OFFSET 0x0030 /* EEPROM Protection */
#define TIVA_EEPROM_EEPASS0_OFFSET 0x0034 /* EEPROM Password */
#define TIVA_EEPROM_EEPASS1_OFFSET 0x0038 /* EEPROM Password */
#define TIVA_EEPROM_EEPASS2_OFFSET 0x003c /* EEPROM Password */
#define TIVA_EEPROM_EEINT_OFFSET 0x0040 /* EEPROM Interrupt */
#define TIVA_EEPROM_EEHIDE_OFFSET 0x0050 /* EEPROM Block Hide */
#define TIVA_EEPROM_EEHIDE0_OFFSET 0x0050 /* EEPROM Block Hide 0 */
#define TIVA_EEPROM_EEHIDE1_OFFSET 0x0054 /* EEPROM Block Hide 1 */
#define TIVA_EEPROM_EEHIDE2_OFFSET 0x0058 /* EEPROM Block Hide 2 */
#define TIVA_EEPROM_EEDBGME_OFFSET 0x0080 /* EEPROM Debug Mass Erase */
#define TIVA_EEPROM_PP_OFFSET 0x0fc0 /* EEPROM Peripheral Properties */
/* Register Addresses ***************************************************************/
#define TIVA_EEPROM_EESIZE (TIVA_EEPROM_BASE + TIVA_EEPROM_EESIZE_OFFSET)
#define TIVA_EEPROM_EEBLOCK (TIVA_EEPROM_BASE + TIVA_EEPROM_EEBLOCK_OFFSET)
#define TIVA_EEPROM_EEOFFSET (TIVA_EEPROM_BASE + TIVA_EEPROM_EEOFFSET_OFFSET)
#define TIVA_EEPROM_EERDWR (TIVA_EEPROM_BASE + TIVA_EEPROM_EERDWR_OFFSET)
#define TIVA_EEPROM_EERDWRINC (TIVA_EEPROM_BASE + TIVA_EEPROM_EERDWRINC_OFFSET)
#define TIVA_EEPROM_EEDONE (TIVA_EEPROM_BASE + TIVA_EEPROM_EEDONE_OFFSET)
#define TIVA_EEPROM_EESUPP (TIVA_EEPROM_BASE + TIVA_EEPROM_EESUPP_OFFSET)
#define TIVA_EEPROM_EEUNLOCK (TIVA_EEPROM_BASE + TIVA_EEPROM_EEUNLOCK_OFFSET)
#define TIVA_EEPROM_EEPROT (TIVA_EEPROM_BASE + TIVA_EEPROM_EEPROT_OFFSET)
#define TIVA_EEPROM_EEPASS0 (TIVA_EEPROM_BASE + TIVA_EEPROM_EEPASS0_OFFSET)
#define TIVA_EEPROM_EEPASS1 (TIVA_EEPROM_BASE + TIVA_EEPROM_EEPASS1_OFFSET)
#define TIVA_EEPROM_EEPASS2 (TIVA_EEPROM_BASE + TIVA_EEPROM_EEPASS2_OFFSET)
#define TIVA_EEPROM_EEINT (TIVA_EEPROM_BASE + TIVA_EEPROM_EEINT_OFFSET)
#define TIVA_EEPROM_EEHIDE0 (TIVA_EEPROM_BASE + TIVA_EEPROM_EEHIDE0_OFFSET)
#define TIVA_EEPROM_EEHIDE (TIVA_EEPROM_BASE + TIVA_EEPROM_EEHIDE_OFFSET)
#define TIVA_EEPROM_EEHIDE1 (TIVA_EEPROM_BASE + TIVA_EEPROM_EEHIDE1_OFFSET)
#define TIVA_EEPROM_EEHIDE2 (TIVA_EEPROM_BASE + TIVA_EEPROM_EEHIDE2_OFFSET)
#define TIVA_EEPROM_EEDBGME (TIVA_EEPROM_BASE + TIVA_EEPROM_EEDBGME_OFFSET)
#define TIVA_EEPROM_PP (TIVA_EEPROM_BASE + TIVA_EEPROM_PP_OFFSET)
/* Register Bit-Field Definitions ***************************************************/
/* The following are defines for the bit fields in the EEPROM_EESIZE register. */
#define EEPROM_EESIZE_WORDCNT_M 0x0000ffff /* Number of 32-Bit Words */
#define EEPROM_EESIZE_BLKCNT_M 0x07ff0000 /* Number of 16-Word Blocks */
#define EEPROM_EESIZE_WORDCNT_S 0
#define EEPROM_EESIZE_BLKCNT_S 16
/* The following are defines for the bit fields in the EEPROM_EEBLOCK register. */
#define EEPROM_EEBLOCK_BLOCK_M 0x0000ffff /* Current Block */
#define EEPROM_EEBLOCK_BLOCK_S 0
/* The following are defines for the bit fields in the EEPROM_EEOFFSET register. */
#define EEPROM_EEOFFSET_OFFSET_M 0x0000000f /* Current Address Offset */
#define EEPROM_EEOFFSET_OFFSET_S 0
/* The following are defines for the bit fields in the EEPROM_EERDWR register. */
#define EEPROM_EERDWR_VALUE_M 0xffffffff /* EEPROM Read or Write Data */
#define EEPROM_EERDWR_VALUE_S 0
/* The following are defines for the bit fields in the EEPROM_EERDWRINC register. */
#define EEPROM_EERDWRINC_VALUE_M 0xffffffff /* EEPROM Read or Write Data with Increment */
#define EEPROM_EERDWRINC_VALUE_S 0
/* The following are defines for the bit fields in the EEPROM_EEDONE register. */
#define EEPROM_EEDONE_WORKING 0x00000001 /* EEPROM Working */
#define EEPROM_EEDONE_WKERASE 0x00000004 /* Working on an Erase */
#define EEPROM_EEDONE_WKCOPY 0x00000008 /* Working on a Copy */
#define EEPROM_EEDONE_NOPERM 0x00000010 /* Write Without Permission */
#define EEPROM_EEDONE_WRBUSY 0x00000020 /* Write Busy */
/* The following are defines for the bit fields in the EEPROM_EESUPP register. */
#define EEPROM_EESUPP_ERETRY 0x00000004 /* Erase Must Be Retried */
#define EEPROM_EESUPP_PRETRY 0x00000008 /* Programming Must Be Retried */
/* The following are defines for the bit fields in the EEPROM_EEUNLOCK register. */
#define EEPROM_EEUNLOCK_UNLOCK_M 0xffffffff /* EEPROM Unlock */
/* The following are defines for the bit fields in the EEPROM_EEPROT register. */
#define EEPROM_EEPROT_PROT_M 0x00000007 /* Protection Control */
#define EEPROM_EEPROT_PROT_RWNPW 0x00000000 /* This setting is the default. If
* there is no password, the block
* is not protected and is readable
* and writable */
#define EEPROM_EEPROT_PROT_RWPW 0x00000001 /* If there is a password, the
* block is readable or writable
* only when unlocked */
#define EEPROM_EEPROT_PROT_RONPW 0x00000002 /* If there is no password, the
* block is readable, not writable */
#define EEPROM_EEPROT_ACC 0x00000008 /* Access Control */
/* The following are defines for the bit fields in the EEPROM_EEPASS0 register. */
#define EEPROM_EEPASS0_PASS_M 0xffffffff /* Password */
#define EEPROM_EEPASS0_PASS_S 0
/* The following are defines for the bit fields in the EEPROM_EEPASS1 register. */
#define EEPROM_EEPASS1_PASS_M 0xffffffff /* Password */
#define EEPROM_EEPASS1_PASS_S 0
/* The following are defines for the bit fields in the EEPROM_EEPASS2 register. */
#define EEPROM_EEPASS2_PASS_M 0xffffffff /* Password */
#define EEPROM_EEPASS2_PASS_S 0
/* The following are defines for the bit fields in the EEPROM_EEINT register. */
#define EEPROM_EEINT_INT 0x00000001 /* Interrupt Enable */
/* The following are defines for the bit fields in the EEPROM_EEHIDE0 register. */
#define EEPROM_EEHIDE0_HN_M 0xfffffffe /* Hide Block */
/* The following are defines for the bit fields in the EEPROM_EEHIDE register. */
#define EEPROM_EEHIDE_HN_M 0xfffffffe /* Hide Block */
/* The following are defines for the bit fields in the EEPROM_EEHIDE1 register. */
#define EEPROM_EEHIDE1_HN_M 0xffffffff /* Hide Block */
/* The following are defines for the bit fields in the EEPROM_EEHIDE2 register. */
#define EEPROM_EEHIDE2_HN_M 0xffffffff /* Hide Block */
/* The following are defines for the bit fields in the EEPROM_EEDBGME register. */
#define EEPROM_EEDBGME_ME 0x00000001 /* Mass Erase */
#define EEPROM_EEDBGME_KEY_M 0xffff0000 /* Erase Key */
#define EEPROM_EEDBGME_KEY_S 16
/* The following are defines for the bit fields in the EEPROM_PP register. */
#define EEPROM_PP_SIZE_M 0x0000ffff /* EEPROM Size */
#define EEPROM_PP_SIZE_64 0x00000000 /* 64 bytes of EEPROM */
#define EEPROM_PP_SIZE_128 0x00000001 /* 128 bytes of EEPROM */
#define EEPROM_PP_SIZE_256 0x00000003 /* 256 bytes of EEPROM */
#define EEPROM_PP_SIZE_512 0x00000007 /* 512 bytes of EEPROM */
#define EEPROM_PP_SIZE_1K 0x0000000f /* 1 KB of EEPROM */
#define EEPROM_PP_SIZE_2K 0x0000001f /* 2 KB of EEPROM */
#define EEPROM_PP_SIZE_3K 0x0000003f /* 3 KB of EEPROM */
#define EEPROM_PP_SIZE_4K 0x0000007f /* 4 KB of EEPROM */
#define EEPROM_PP_SIZE_5K 0x000000ff /* 5 KB of EEPROM */
#define EEPROM_PP_SIZE_6K 0x000001ff /* 6 KB of EEPROM */
#define EEPROM_PP_SIZE_S 0
#endif /* __ARCH_ARM_SRC_TIVA_CHIP_TIVA_EEPROM_H */

292
arch/arm/src/tiva/chip/tm4c123_syscontrol.h
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@ -48,164 +48,166 @@
/* System Control Register Offsets **********************************************************/
#define TIVA_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
#define TIVA_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
#define TIVA_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
#define TIVA_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
#define TIVA_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
#define TIVA_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
#define TIVA_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
#define TIVA_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
#define TIVA_SYSCON_GPIOHBCTL_OFFSET 0x06c /* GPIO High-Performance Bus Control */
#define TIVA_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
#define TIVA_SYSCON_MOSCCTL_OFFSET 0x07c /* Main Oscillator Control */
#define TIVA_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration */
#define TIVA_SYSCON_SYSPROP_OFFSET 0x14c /* System Properties */
#define TIVA_SYSCON_PIOSCCAL_OFFSET 0x150 /* Precision Internal Oscillator Calibration */
#define TIVA_SYSCON_PIOSCSTAT_OFFSET 0x154 /* Precision Internal Oscillator Statistics */
#define TIVA_SYSCON_PLLFREQ0_OFFSET 0x160 /* PLL 0 Frequency */
#define TIVA_SYSCON_PLLFREQ1_OFFSET 0x164 /* PLL 1 Frequency */
#define TIVA_SYSCON_PLLSTAT_OFFSET 0x168 /* PLL Status */
#define TIVA_SYSCON_SLPPWRCFG_OFFSET 0x188 /* Sleep Power Configuration */
#define TIVA_SYSCON_DSLPPWRCFG_OFFSET 0x18c /* Deep-Sleep Power Configuration */
#define TIVA_SYSCON_LDOSPCTL_OFFSET 0x1b4 /* LDO Sleep Power Control */
#define TIVA_SYSCON_LDOSPCAL_OFFSET 0x1b8 /* LDO Sleep Power Calibration */
#define TIVA_SYSCON_LDODPCTL_OFFSET 0x1bc /* LDO Deep-Sleep Power Control */
#define TIVA_SYSCON_LDODPCAL_OFFSET 0x1c0 /* LDO Deep-Sleep Power Calibration */
#define TIVA_SYSCON_SDPMST_OFFSET 0x1cc /* Sleep / Deep-Sleep Power Mode Status */
#define TIVA_SYSCON_DID0_OFFSET 0x0000 /* Device Identification 0 */
#define TIVA_SYSCON_DID1_OFFSET 0x0004 /* Device Identification 1 */
#define TIVA_SYSCON_PBORCTL_OFFSET 0x0030 /* Brown-Out Reset Control */
#define TIVA_SYSCON_RIS_OFFSET 0x0050 /* Raw Interrupt Status */
#define TIVA_SYSCON_IMC_OFFSET 0x0054 /* Interrupt Mask Control */
#define TIVA_SYSCON_MISC_OFFSET 0x0058 /* Masked Interrupt Status and Clear */
#define TIVA_SYSCON_RESC_OFFSET 0x005c /* Reset Cause */
#define TIVA_SYSCON_RCC_OFFSET 0x0060 /* Run-Mode Clock Configuration */
#define TIVA_SYSCON_GPIOHBCTL_OFFSET 0x006c /* GPIO High-Performance Bus Control */
#define TIVA_SYSCON_RCC2_OFFSET 0x0070 /* Run-Mode Clock Configuration 2 */
#define TIVA_SYSCON_MOSCCTL_OFFSET 0x007c /* Main Oscillator Control */
#define TIVA_SYSCON_DSLPCLKCFG_OFFSET 0x0144 /* Deep Sleep Clock Configuration */
#define TIVA_SYSCON_SYSPROP_OFFSET 0x014c /* System Properties */
#define TIVA_SYSCON_PIOSCCAL_OFFSET 0x0150 /* Precision Internal Oscillator Calibration */
#define TIVA_SYSCON_PIOSCSTAT_OFFSET 0x0154 /* Precision Internal Oscillator Statistics */
#define TIVA_SYSCON_PLLFREQ0_OFFSET 0x0160 /* PLL 0 Frequency */
#define TIVA_SYSCON_PLLFREQ1_OFFSET 0x0164 /* PLL 1 Frequency */
#define TIVA_SYSCON_PLLSTAT_OFFSET 0x0168 /* PLL Status */
#define TIVA_SYSCON_SLPPWRCFG_OFFSET 0x0188 /* Sleep Power Configuration */
#define TIVA_SYSCON_DSLPPWRCFG_OFFSET 0x018c /* Deep-Sleep Power Configuration */
#define TIVA_SYSCON_LDOSPCTL_OFFSET 0x01b4 /* LDO Sleep Power Control */
#define TIVA_SYSCON_LDOSPCAL_OFFSET 0x01b8 /* LDO Sleep Power Calibration */
#define TIVA_SYSCON_LDODPCTL_OFFSET 0x01bc /* LDO Deep-Sleep Power Control */
#define TIVA_SYSCON_LDODPCAL_OFFSET 0x01c0 /* LDO Deep-Sleep Power Calibration */
#define TIVA_SYSCON_SDPMST_OFFSET 0x01cc /* Sleep / Deep-Sleep Power Mode Status */
#define TIVA_SYSCON_PPWD_OFFSET 0x300 /* Watchdog Timer Peripheral Present */
#define TIVA_SYSCON_PPTIMER_OFFSET 0x304 /* 16/32-Bit Timer Peripheral Present */
#define TIVA_SYSCON_PPGPIO_OFFSET 0x308 /* GPIO Peripheral Present */
#define TIVA_SYSCON_PPDMA_OFFSET 0x30c /* uDMA Peripheral Present */
#define TIVA_SYSCON_PPHIB_OFFSET 0x314 /* Hibernation Peripheral Present */
#define TIVA_SYSCON_PPUART_OFFSET 0x318 /* UART Present */
#define TIVA_SYSCON_PPSSI_OFFSET 0x31c /* SSI Peripheral Present */
#define TIVA_SYSCON_PPI2C_OFFSET 0x320 /* I2C Peripheral Present */
#define TIVA_SYSCON_PPUSB_OFFSET 0x328 /* USB Peripheral Present */
#define TIVA_SYSCON_PPCAN_OFFSET 0x334 /* CAN Peripheral Present */
#define TIVA_SYSCON_PPADC_OFFSET 0x338 /* ADC Peripheral Present */
#define TIVA_SYSCON_PPACMP_OFFSET 0x33c /* Analog Comparator Peripheral Present */
#define TIVA_SYSCON_PPPWM_OFFSET 0x340 /* Pulse Width Modulator Peripheral Present */
#define TIVA_SYSCON_PPQEI_OFFSET 0x344 /* Quadrature Encoder Peripheral Present */
#define TIVA_SYSCON_PPEEPROM_OFFSET 0x358 /* EEPROM Peripheral Present */
#define TIVA_SYSCON_PPWTIMER_OFFSET 0x35c /* 32/64-Bit Wide Timer Peripheral Present */
#define TIVA_SYSCON_PPWD_OFFSET 0x0300 /* Watchdog Timer Peripheral Present */
#define TIVA_SYSCON_PPTIMER_OFFSET 0x0304 /* 16/32-Bit Timer Peripheral Present */
#define TIVA_SYSCON_PPGPIO_OFFSET 0x0308 /* GPIO Peripheral Present */
#define TIVA_SYSCON_PPDMA_OFFSET 0x030c /* uDMA Peripheral Present */
#define TIVA_SYSCON_PPHIB_OFFSET 0x0314 /* Hibernation Peripheral Present */
#define TIVA_SYSCON_PPUART_OFFSET 0x0318 /* UART Present */
#define TIVA_SYSCON_PPSSI_OFFSET 0x031c /* SSI Peripheral Present */
#define TIVA_SYSCON_PPI2C_OFFSET 0x0320 /* I2C Peripheral Present */
#define TIVA_SYSCON_PPUSB_OFFSET 0x0328 /* USB Peripheral Present */
#define TIVA_SYSCON_PPCAN_OFFSET 0x0334 /* CAN Peripheral Present */
#define TIVA_SYSCON_PPADC_OFFSET 0x0338 /* ADC Peripheral Present */
#define TIVA_SYSCON_PPACMP_OFFSET 0x033c /* Analog Comparator Peripheral Present */
#define TIVA_SYSCON_PPPWM_OFFSET 0x0340 /* Pulse Width Modulator Peripheral Present */
#define TIVA_SYSCON_PPQEI_OFFSET 0x0344 /* Quadrature Encoder Peripheral Present */
#define TIVA_SYSCON_PPEEPROM_OFFSET 0x0358 /* EEPROM Peripheral Present */
#define TIVA_SYSCON_PPWTIMER_OFFSET 0x035c /* 32/64-Bit Wide Timer Peripheral Present */
#define TIVA_SYSCON_SRWD_OFFSET 0x500 /* Watchdog Timer Software Reset */
#define TIVA_SYSCON_SRTIMER_OFFSET 0x504 /* 16/32-Bit Timer Software Reset */
#define TIVA_SYSCON_SRGPIO_OFFSET 0x508 /* GPIO Software Reset */
#define TIVA_SYSCON_SRDMA_OFFSET 0x50c /* uDMA Software Reset */
#define TIVA_SYSCON_SRHIB_OFFSET 0x514 /* Hibernation Software Reset */
#define TIVA_SYSCON_SRUART_OFFSET 0x518 /* UART Software Reset*/
#define TIVA_SYSCON_SRSSI_OFFSET 0x51c /* SSI Software Reset */
#define TIVA_SYSCON_SRI2C_OFFSET 0x520 /* I2C Software Reset */
#define TIVA_SYSCON_SRUSB_OFFSET 0x528 /* USB Software Reset */
#define TIVA_SYSCON_SRCAN_OFFSET 0x534 /* CAN Software Reset */
#define TIVA_SYSCON_SRADC_OFFSET 0x538 /* ADC Software Reset */
#define TIVA_SYSCON_SRACMP_OFFSET 0x53c /* Analog Comparator Software Reset */
#define TIVA_SYSCON_SRPWM_OFFSET 0x540 /* Pulse Width Modulator Software Reset */
#define TIVA_SYSCON_SRQEI_OFFSET 0x544 /* Quadrature Encoder Interface Software Reset */
#define TIVA_SYSCON_SREEPROM_OFFSET 0x558 /* EEPROM Software Reset */
#define TIVA_SYSCON_SRWTIMER_OFFSET 0x55c /* 32/64-Bit Wide Timer Software Reset */
#define TIVA_SYSCON_SR_OFFSET 0x0500
#define TIVA_SYSCON_SRWD_OFFSET 0x0500 /* Watchdog Timer Software Reset */
#define TIVA_SYSCON_SRTIMER_OFFSET 0x0504 /* 16/32-Bit Timer Software Reset */
#define TIVA_SYSCON_SRGPIO_OFFSET 0x0508 /* GPIO Software Reset */
#define TIVA_SYSCON_SRDMA_OFFSET 0x050c /* uDMA Software Reset */
#define TIVA_SYSCON_SRHIB_OFFSET 0x0514 /* Hibernation Software Reset */
#define TIVA_SYSCON_SRUART_OFFSET 0x0518 /* UART Software Reset*/
#define TIVA_SYSCON_SRSSI_OFFSET 0x051c /* SSI Software Reset */
#define TIVA_SYSCON_SRI2C_OFFSET 0x0520 /* I2C Software Reset */
#define TIVA_SYSCON_SRUSB_OFFSET 0x0528 /* USB Software Reset */
#define TIVA_SYSCON_SRCAN_OFFSET 0x0534 /* CAN Software Reset */
#define TIVA_SYSCON_SRADC_OFFSET 0x0538 /* ADC Software Reset */
#define TIVA_SYSCON_SRACMP_OFFSET 0x053c /* Analog Comparator Software Reset */
#define TIVA_SYSCON_SRPWM_OFFSET 0x0540 /* Pulse Width Modulator Software Reset */
#define TIVA_SYSCON_SRQEI_OFFSET 0x0544 /* Quadrature Encoder Interface Software Reset */
#define TIVA_SYSCON_SREEPROM_OFFSET 0x0558 /* EEPROM Software Reset */
#define TIVA_SYSCON_SRWTIMER_OFFSET 0x055c /* 32/64-Bit Wide Timer Software Reset */
#define TIVA_SYSCON_RCGCWD_OFFSET 0x600 /* Watchdog Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCTIMER_OFFSET 0x604 /* 16/32-Bit Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCGPIO_OFFSET 0x608 /* GPIO Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCDMA_OFFSET 0x60c /* uDMA Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCHIB_OFFSET 0x614 /* Hibernation Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCUART_OFFSET 0x618 /* UART Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCSSI_OFFSET 0x61c /* SSI Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCI2C_OFFSET 0x620 /* I2C Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCUSB_OFFSET 0x628 /* USB Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCCAN_OFFSET 0x634 /* CAN Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCADC_OFFSET 0x638 /* ADC Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCACMP_OFFSET 0x63c /* Analog Comparator Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCPWM_OFFSET 0x640 /* Pulse Width Modulator Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCQEI_OFFSET 0x644 /* Quadrature Encoder Interface Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCEEPROM_OFFSET 0x658 /* EEPROM Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCWTIMER_OFFSET 0x65c /* 32/64-BitWide Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGC_OFFSET 0x0600
#define TIVA_SYSCON_RCGCWD_OFFSET 0x0600 /* Watchdog Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCTIMER_OFFSET 0x0604 /* 16/32-Bit Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCGPIO_OFFSET 0x0608 /* GPIO Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCDMA_OFFSET 0x060c /* uDMA Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCHIB_OFFSET 0x0614 /* Hibernation Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCUART_OFFSET 0x0618 /* UART Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCSSI_OFFSET 0x061c /* SSI Run Mode Clock Gating Control*/
#define TIVA_SYSCON_RCGCI2C_OFFSET 0x0620 /* I2C Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCUSB_OFFSET 0x0628 /* USB Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCCAN_OFFSET 0x0634 /* CAN Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCADC_OFFSET 0x0638 /* ADC Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCACMP_OFFSET 0x063c /* Analog Comparator Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCPWM_OFFSET 0x0640 /* Pulse Width Modulator Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCQEI_OFFSET 0x0644 /* Quadrature Encoder Interface Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCEEPROM_OFFSET 0x0658 /* EEPROM Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCWTIMER_OFFSET 0x065c /* 32/64-BitWide Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCWD_OFFSET 0x700 /* Watchdog Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCTIMER_OFFSET 0x704 /* 16/32-Bit Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCGPIO_OFFSET 0x708 /* GPIO Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCDMA_OFFSET 0x70c /* uDMA Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCHIB_OFFSET 0x714 /* Hibernation Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCUART_OFFSET 0x718 /* UART Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCSSI_OFFSET 0x71c /* SSI Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCI2C_OFFSET 0x720 /* I2C Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCUSB_OFFSET 0x728 /* USB Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCCAN_OFFSET 0x734 /* CAN Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCADC_OFFSET 0x738 /* ADC Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCACMP_OFFSET 0x73c /* Analog Comparator Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCPWM_OFFSET 0x740 /* PulseWidthModulator Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCQEI_OFFSET 0x744 /* Quadrature Encoder Interface Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCEEPROM_OFFSET 0x758 /* EEPROM Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCWTIMER_OFFSET 0x75c /* 32/64-BitWide Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCWD_OFFSET 0x0700 /* Watchdog Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCTIMER_OFFSET 0x0704 /* 16/32-Bit Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCGPIO_OFFSET 0x0708 /* GPIO Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCDMA_OFFSET 0x070c /* uDMA Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCHIB_OFFSET 0x0714 /* Hibernation Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCUART_OFFSET 0x0718 /* UART Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCSSI_OFFSET 0x071c /* SSI Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCI2C_OFFSET 0x0720 /* I2C Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCUSB_OFFSET 0x0728 /* USB Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCCAN_OFFSET 0x0734 /* CAN Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCADC_OFFSET 0x0738 /* ADC Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCACMP_OFFSET 0x073c /* Analog Comparator Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCPWM_OFFSET 0x0740 /* PulseWidthModulator Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCQEI_OFFSET 0x0744 /* Quadrature Encoder Interface Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCEEPROM_OFFSET 0x0758 /* EEPROM Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_SCGCWTIMER_OFFSET 0x075c /* 32/64-BitWide Timer Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCWD_OFFSET 0x800 /* Watchdog Timer Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCTIMER_OFFSET 0x804 /* Clock Gating Control */
#define TIVA_SYSCON_DCGCGPIO_OFFSET 0x808 /* GPIO Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCDMA_OFFSET 0x80c /* uDMA Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCHIB_OFFSET 0x814 /* Hibernation Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCUART_OFFSET 0x818 /* UART Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCSSI_OFFSET 0x81c /* SSI Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCI2C_OFFSET 0x820 /* I2C Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCUSB_OFFSET 0x828 /* USB Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCCAN_OFFSET 0x834 /* CAN Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCADC_OFFSET 0x838 /* ADC Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCACMP_OFFSET 0x83c /* Analog Comparator Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCPWM_OFFSET 0x840 /* Pulse Width Modulator Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCQEI_OFFSET 0x844 /* Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCEEPROM_OFFSET 0x858 /* EEPROM Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCWTIMER_OFFSET 0x85c /* 32/64-BitWide Timer Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCWD_OFFSET 0x0800 /* Watchdog Timer Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCTIMER_OFFSET 0x0804 /* Clock Gating Control */
#define TIVA_SYSCON_DCGCGPIO_OFFSET 0x0808 /* GPIO Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCDMA_OFFSET 0x080c /* uDMA Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCHIB_OFFSET 0x0814 /* Hibernation Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCUART_OFFSET 0x0818 /* UART Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCSSI_OFFSET 0x081c /* SSI Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCI2C_OFFSET 0x0820 /* I2C Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCUSB_OFFSET 0x0828 /* USB Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCCAN_OFFSET 0x0834 /* CAN Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCADC_OFFSET 0x0838 /* ADC Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCACMP_OFFSET 0x083c /* Analog Comparator Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCPWM_OFFSET 0x0840 /* Pulse Width Modulator Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCQEI_OFFSET 0x0844 /* Quadrature Encoder Interface Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCEEPROM_OFFSET 0x0858 /* EEPROM Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_DCGCWTIMER_OFFSET 0x085c /* 32/64-BitWide Timer Deep-Sleep Mode Clock Gating Control */
#define TIVA_SYSCON_PRWD_OFFSET 0xa00 /* Watchdog Timer Peripheral Ready */
#define TIVA_SYSCON_PRTIMER_OFFSET 0xa04 /* 16/32-Bit Timer Peripheral Ready */
#define TIVA_SYSCON_PRGPIO_OFFSET 0xa08 /* GPIO Peripheral Ready */
#define TIVA_SYSCON_PRDMA_OFFSET 0xa0c /* uDMA Peripheral Ready */
#define TIVA_SYSCON_PRHIB_OFFSET 0xa14 /* Hibernation Peripheral Ready */
#define TIVA_SYSCON_PRUART_OFFSET 0xa18 /* UART Peripheral Ready */
#define TIVA_SYSCON_PRSSI_OFFSET 0xa1c /* SSI Peripheral Ready */
#define TIVA_SYSCON_PRI2C_OFFSET 0xa20 /* I2C Peripheral Ready */
#define TIVA_SYSCON_PRUSB_OFFSET 0xa28 /* USB Peripheral Ready */
#define TIVA_SYSCON_PRCAN_OFFSET 0xa34 /* CAN Peripheral Ready */
#define TIVA_SYSCON_PRADC_OFFSET 0xa38 /* ADC Peripheral Ready */
#define TIVA_SYSCON_PRACMP_OFFSET 0xa3c /* Analog Comparator Peripheral Ready */
#define TIVA_SYSCON_PRPWM_OFFSET 0xa40 /* Pulse Width Modulator Peripheral Ready */
#define TIVA_SYSCON_PRQEI_OFFSET 0xa44 /* Quadrature Encoder Interface Peripheral Ready */
#define TIVA_SYSCON_PREEPROM_OFFSET 0xa58 /* EEPROM Peripheral Ready */
#define TIVA_SYSCON_PRWTIMER_OFFSET 0xa5c /* 2/64-BitWide Timer Peripheral Ready */
#define TIVA_SYSCON_PRWD_OFFSET 0x0a00 /* Watchdog Timer Peripheral Ready */
#define TIVA_SYSCON_PRTIMER_OFFSET 0x0a04 /* 16/32-Bit Timer Peripheral Ready */
#define TIVA_SYSCON_PRGPIO_OFFSET 0x0a08 /* GPIO Peripheral Ready */
#define TIVA_SYSCON_PRDMA_OFFSET 0x0a0c /* uDMA Peripheral Ready */
#define TIVA_SYSCON_PRHIB_OFFSET 0x0a14 /* Hibernation Peripheral Ready */
#define TIVA_SYSCON_PRUART_OFFSET 0x0a18 /* UART Peripheral Ready */
#define TIVA_SYSCON_PRSSI_OFFSET 0x0a1c /* SSI Peripheral Ready */
#define TIVA_SYSCON_PRI2C_OFFSET 0x0a20 /* I2C Peripheral Ready */
#define TIVA_SYSCON_PRUSB_OFFSET 0x0a28 /* USB Peripheral Ready */
#define TIVA_SYSCON_PRCAN_OFFSET 0x0a34 /* CAN Peripheral Ready */
#define TIVA_SYSCON_PRADC_OFFSET 0x0a38 /* ADC Peripheral Ready */
#define TIVA_SYSCON_PRACMP_OFFSET 0x0a3c /* Analog Comparator Peripheral Ready */
#define TIVA_SYSCON_PRPWM_OFFSET 0x0a40 /* Pulse Width Modulator Peripheral Ready */
#define TIVA_SYSCON_PRQEI_OFFSET 0x0a44 /* Quadrature Encoder Interface Peripheral Ready */
#define TIVA_SYSCON_PREEPROM_OFFSET 0x0a58 /* EEPROM Peripheral Ready */
#define TIVA_SYSCON_PRWTIMER_OFFSET 0x0a5c /* 2/64-BitWide Timer Peripheral Ready */
/* System Control Legacy Register Offsets ***************************************************/
#define TIVA_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
#define TIVA_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
#define TIVA_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
#define TIVA_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
#define TIVA_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
#define TIVA_SYSCON_DC5_OFFSET 0x020 /* Device Capabilities 5 */
#define TIVA_SYSCON_DC6_OFFSET 0x024 /* Device Capabilities 6 */
#define TIVA_SYSCON_DC7_OFFSET 0x028 /* Device Capabilities 7 */
#define TIVA_SYSCON_DC8_OFFSET 0x02c /* Device Capabilities 8 */
#define TIVA_SYSCON_DC0_OFFSET 0x0008 /* Device Capabilities 0 */
#define TIVA_SYSCON_DC1_OFFSET 0x0010 /* Device Capabilities 1 */
#define TIVA_SYSCON_DC2_OFFSET 0x0014 /* Device Capabilities 2 */
#define TIVA_SYSCON_DC3_OFFSET 0x0018 /* Device Capabilities 3 */
#define TIVA_SYSCON_DC4_OFFSET 0x001c /* Device Capabilities 4 */
#define TIVA_SYSCON_DC5_OFFSET 0x0020 /* Device Capabilities 5 */
#define TIVA_SYSCON_DC6_OFFSET 0x0024 /* Device Capabilities 6 */
#define TIVA_SYSCON_DC7_OFFSET 0x0028 /* Device Capabilities 7 */
#define TIVA_SYSCON_DC8_OFFSET 0x002c /* Device Capabilities 8 */
#define TIVA_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
#define TIVA_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
#define TIVA_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2 */
#define TIVA_SYSCON_SRCR0_OFFSET 0x0040 /* Software Reset Control 0 */
#define TIVA_SYSCON_SRCR1_OFFSET 0x0044 /* Software Reset Control 1 */
#define TIVA_SYSCON_SRCR2_OFFSET 0x0048 /* Software Reset Control 2 */
#define TIVA_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_RCGC0_OFFSET 0x0100 /* Run Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_RCGC1_OFFSET 0x0104 /* Run Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_RCGC2_OFFSET 0x0108 /* Run Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_SCGC0_OFFSET 0x0110 /* Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_SCGC1_OFFSET 0x0114 /* Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_SCGC2_OFFSET 0x0118 /* Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_DCGC0_OFFSET 0x0120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_DCGC1_OFFSET 0x0124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_DCGC2_OFFSET 0x0128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_DC9_OFFSET 0x190 /* Device Capabilities */
#define TIVA_SYSCON_NVMSTAT_OFFSET 0x1a0 /* Non-Volatile Memory Information */
#define TIVA_SYSCON_DC9_OFFSET 0x0190 /* Device Capabilities */
#define TIVA_SYSCON_NVMSTAT_OFFSET 0x01a0 /* Non-Volatile Memory Information */
/* System Control Register Addresses ********************************************************/
@ -252,6 +254,7 @@
#define TIVA_SYSCON_PPEEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_PPEEPROM_OFFSET)
#define TIVA_SYSCON_PPWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_PPWTIMER_OFFSET)
#define TIVA_SYSCON_SR_BASE (TIVA_SYSCON_BASE + TIVA_SYSCON_SR_OFFSET)
#define TIVA_SYSCON_SRWD (TIVA_SYSCON_BASE + TIVA_SYSCON_SRWD_OFFSET)
#define TIVA_SYSCON_SRTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_SRTIMER_OFFSET)
#define TIVA_SYSCON_SRGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_SRGPIO_OFFSET)
@ -269,6 +272,7 @@
#define TIVA_SYSCON_SREEPROM (TIVA_SYSCON_BASE + TIVA_SYSCON_SREEPROM_OFFSET)
#define TIVA_SYSCON_SRWTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_SRWTIMER_OFFSET)
#define TIVA_SYSCON_RCGC_BASE (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC_OFFSET)
#define TIVA_SYSCON_RCGCWD (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCWD_OFFSET)
#define TIVA_SYSCON_RCGCTIMER (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCTIMER_OFFSET)
#define TIVA_SYSCON_RCGCGPIO (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGCGPIO_OFFSET)

69
arch/arm/src/tiva/chip/tm4c129_syscontrol.h
View File

@ -118,6 +118,8 @@
#define TIVA_SYSCON_PPEMAC_OFFSET 0x039c /* Ethernet MAC Peripheral Present */
#define TIVA_SYSCON_PPPRB_OFFSET 0x03a0 /* Power Regulator Bus Peripheral Present */
#define TIVA_SYSCON_PPHIM_OFFSET 0x03a4 /* Human Interface Master Peripheral Present */
#define TIVA_SYSCON_SR_OFFSET 0x0500
#define TIVA_SYSCON_SRWD_OFFSET 0x0500 /* Watchdog Timer Software Reset */
#define TIVA_SYSCON_SRTIMER_OFFSET 0x0504 /* 16/32-Bit Timer Software Reset */
#define TIVA_SYSCON_SRGPIO_OFFSET 0x0508 /* GPIO Software Reset */
@ -140,6 +142,8 @@
#define TIVA_SYSCON_SRLCD_OFFSET 0x0590 /* LCD Controller Software Reset */
#define TIVA_SYSCON_SROWIRE_OFFSET 0x0598 /* 1-Wire Software Reset */
#define TIVA_SYSCON_SREMAC_OFFSET 0x059c /* Ethernet MAC Software Reset */
#define TIVA_SYSCON_RCGC_OFFSET 0x0600
#define TIVA_SYSCON_RCGCWD_OFFSET 0x0600 /* Watchdog Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCTIMER_OFFSET 0x0604 /* 16/32-Bit Timer Run Mode Clock Gating Control */
#define TIVA_SYSCON_RCGCGPIO_OFFSET 0x0608 /* GPIO Run Mode Clock Gating Control */
@ -258,6 +262,36 @@
#define TIVA_SYSCON_CCMCGREQ_OFFSET 0x0204 /* Cryptographic Modules Clock Gating Request */
/* System Control Legacy Register Offsets ***************************************************/
#define TIVA_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
#define TIVA_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
#define TIVA_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
#define TIVA_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
#define TIVA_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
#define TIVA_SYSCON_DC5_OFFSET 0x020 /* Device Capabilities 5 */
#define TIVA_SYSCON_DC6_OFFSET 0x024 /* Device Capabilities 6 */
#define TIVA_SYSCON_DC7_OFFSET 0x028 /* Device Capabilities 7 */
#define TIVA_SYSCON_DC8_OFFSET 0x02c /* Device Capabilities 8 */
#define TIVA_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
#define TIVA_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
#define TIVA_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2 */
#define TIVA_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define TIVA_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define TIVA_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define TIVA_SYSCON_DC9_OFFSET 0x190 /* Device Capabilities */
/* System Control Register Addresses ********************************************************/
/* System Control Registers (System Control Offset) */
@ -331,6 +365,8 @@
#define TIVA_SYSCON_PPEMAC (TIVA_SYSCON_BASE+TIVA_SYSCON_PPEMAC_OFFSET)
#define TIVA_SYSCON_PPPRB (TIVA_SYSCON_BASE+TIVA_SYSCON_PPPRB_OFFSET)
#define TIVA_SYSCON_PPHIM (TIVA_SYSCON_BASE+TIVA_SYSCON_PPHIM_OFFSET)
#define TIVA_SYSCON_SR_BASE (TIVA_SYSCON_BASE+TIVA_SYSCON_SR_OFFSET)
#define TIVA_SYSCON_SRWD (TIVA_SYSCON_BASE+TIVA_SYSCON_SRWD_OFFSET)
#define TIVA_SYSCON_SRTIMER (TIVA_SYSCON_BASE+TIVA_SYSCON_SRTIMER_OFFSET)
#define TIVA_SYSCON_SRGPIO (TIVA_SYSCON_BASE+TIVA_SYSCON_SRGPIO_OFFSET)
@ -353,6 +389,8 @@
#define TIVA_SYSCON_SRLCD (TIVA_SYSCON_BASE+TIVA_SYSCON_SRLCD_OFFSET)
#define TIVA_SYSCON_SROWIRE (TIVA_SYSCON_BASE+TIVA_SYSCON_SROWIRE_OFFSET)
#define TIVA_SYSCON_SREMAC (TIVA_SYSCON_BASE+TIVA_SYSCON_SREMAC_OFFSET)
#define TIVA_SYSCON_RCGC_BASE (TIVA_SYSCON_BASE+TIVA_SYSCON_RCGC_OFFSET)
#define TIVA_SYSCON_RCGCWD (TIVA_SYSCON_BASE+TIVA_SYSCON_RCGCWD_OFFSET)
#define TIVA_SYSCON_RCGCTIMER (TIVA_SYSCON_BASE+TIVA_SYSCON_RCGCTIMER_OFFSET)
#define TIVA_SYSCON_RCGCGPIO (TIVA_SYSCON_BASE+TIVA_SYSCON_RCGCGPIO_OFFSET)
@ -471,6 +509,36 @@
#define TIVA_SYSCON_CCMCGREQ (TIVA_CCM_BASE+TIVA_SYSCON_CCMCGREQ_OFFSET)
/* System Control Legacy Register Addresses *************************************************/
#define TIVA_SYSCON_DC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC0_OFFSET)
#define TIVA_SYSCON_DC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC1_OFFSET)
#define TIVA_SYSCON_DC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC2_OFFSET)
#define TIVA_SYSCON_DC3 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC3_OFFSET)
#define TIVA_SYSCON_DC4 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC4_OFFSET)
#define TIVA_SYSCON_DC5 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC5_OFFSET)
#define TIVA_SYSCON_DC6 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC6_OFFSET)
#define TIVA_SYSCON_DC7 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC7_OFFSET)
#define TIVA_SYSCON_DC8 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC8_OFFSET)
#define TIVA_SYSCON_SRCR0 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR0_OFFSET)
#define TIVA_SYSCON_SRCR1 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR1_OFFSET)
#define TIVA_SYSCON_SRCR2 (TIVA_SYSCON_BASE + TIVA_SYSCON_SRCR2_OFFSET)
#define TIVA_SYSCON_RCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC0_OFFSET)
#define TIVA_SYSCON_RCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC1_OFFSET)
#define TIVA_SYSCON_RCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_RCGC2_OFFSET)
#define TIVA_SYSCON_SCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC0_OFFSET)
#define TIVA_SYSCON_SCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC1_OFFSET)
#define TIVA_SYSCON_SCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_SCGC2_OFFSET)
#define TIVA_SYSCON_DCGC0 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC0_OFFSET)
#define TIVA_SYSCON_DCGC1 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC1_OFFSET)
#define TIVA_SYSCON_DCGC2 (TIVA_SYSCON_BASE + TIVA_SYSCON_DCGC2_OFFSET)
#define TIVA_SYSCON_DC9 (TIVA_SYSCON_BASE + TIVA_SYSCON_DC9_OFFSET)
/* System Control Register Bit Definitions **************************************************/
/* System Control Registers (System Control Offset) */
@ -1084,7 +1152,6 @@
# define SYSCON_PPI2C_P8 (1 << 8) /* Bit 8: I2C Module 8 Present */
# define SYSCON_PPI2C_P9 (1 << 9) /* Bit 9: I2C Module 9 Present */
/* USB Peripheral Present */
#define SYSCON_PPUSB_P0 (1 << 0) /* Bit 0: USB Module Present */

681
arch/arm/src/tiva/tiva_eeprom.c Normal file
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@ -0,0 +1,681 @@
/****************************************************************************
* arch/arm/src/tiva/tiva_eeprom.c
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Shirshak Sengupta <sgshirshak@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <errno.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/mtd/mtd.h>
#include "up_arch.h"
#include "chip.h"
#include "chip/tiva_syscontrol.h"
#include "tiva_eeprom.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* This macro extracts the array index out of the peripheral number. */
#define SYSCTL_PERIPH_INDEX(a) (((a) >> 28) & 0xf)
/* This macro constructs the peripheral bit mask from the peripheral number. */
#define SYSCTL_PERIPH_MASK(a) (((a) & 0xffff) << (((a) & 0x001f0000) >> 16))
#define SYSCTL_PERIPH_EEPROM0 0xf0005800 /* REVISIT: What is this? */
/* Macros for hardware access, both direct and via the bit-band region. */
#define PERIPHADDR(x, b) \
(((unsigned long)(x) & 0xf0000000) | 0x02000000 | \
(((unsigned long)(x) & 0x000fffff) << 5) | ((b) << 2))
/* Useful macros to extract the number of EEPROM blocks available on the
* target device and the total EEPROM storage in bytes from the EESIZE
* register.
*/
#define BLOCKS_FROM_EESIZE(x) (((x) & EEPROM_EESIZE_BLKCNT_M) >> \
EEPROM_EESIZE_BLKCNT_S)
#define SIZE_FROM_EESIZE(x) ((((x) & EEPROM_EESIZE_WORDCNT_M) >> \
EEPROM_EESIZE_WORDCNT_S) * 4)
/* Useful macro to extract the offset from a linear address. */
#define EEPROM_ADDR2OFFSET(x) (((x) >> 2) & 0x0f)
/* The key value required to initiate a mass erase. */
#define EEPROM_MASS_ERASE_KEY ((uint32_t)0xE37B << EEPROM_EEDBGME_KEY_S)
#define EEPROM_ADDR2BLOCK(addr) ((addr) >> 6)
/****************************************************************************
* Private Types
****************************************************************************/
/* This type represents the state of the MTD device. The struct mtd_dev_s
* must appear at the beginning of the definition so that you can freely
* cast between pointers to struct mtd_dev_s and struct tiva_dev_s.
*/
struct tiva_dev_s
{
struct mtd_dev_s mtd;
/* Other implementation specific data may follow here */
};
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* MTD driver methods */
static int tiva_eeprom_erase(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks);
static ssize_t tiva_eeprom_bread(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR uint8_t *buf);
static ssize_t tiva_eeprom_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR const uint8_t *buf);
static ssize_t tiva_eeprom_read(FAR struct mtd_dev_s *dev, off_t offset,
size_t nbytes, FAR uint8_t *buf);
#ifdef CONFIG_MTD_BYTE_WRITE
static ssize_t tiva_eeprom_write(FAR struct mtd_dev_s *dev, off_t offset,
size_t nbytes, FAR const uint8_t *buf);
#endif
static int tiva_eeprom_ioctl(FAR struct mtd_dev_s *dev, int cmd,
unsigned long arg);
/****************************************************************************
* Private Data
****************************************************************************/
/* This structure holds the state of the MTD driver */
static struct tiva_dev_s g_eeprom_dev =
{
{
tiva_eeprom_erase,
tiva_eeprom_bread,
tiva_eeprom_bwrite,
tiva_eeprom_read,
#ifdef CONFIG_MTD_BYTE_WRITE
tiva_eeprom_write,
#endif
tiva_eeprom_ioctl
},
/* Initialization of any other implementation specific data goes here */
};
/* An array that maps the "peripheral set" number (which is stored in the
* upper nibble of the SYSCTL_PERIPH_* defines) to the SYSCTL_RCGC? register
* that controls the run-mode enable for that peripheral.
*/
static const unsigned long g_pulrcgc_regs[] =
{
TIVA_SYSCON_RCGC0,
TIVA_SYSCON_RCGC1,
TIVA_SYSCON_RCGC2
};
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: tiva_delay
*
* Description:
* Wait a small amount of time. The total delay is about 3 * delay cycles.
*
****************************************************************************/
static inline void tiva_delay(uint32_t delay)
{
__asm__ __volatile__("1:\n"
"\tsubs %0, #1\n"
"\tbne 1b\n"
: "=r"(delay) : "r"(delay));
}
/****************************************************************************
* Name: tiva_eeprom_enable
*
* Description:
* Enables the EEPROM peripheral.
*
* This function enables peripherals. At power-up, all peripherals
* are disabled; they must be enabled in order to operate or respond to
* register reads/writes.
*
* NOTE: It takes five clock cycles after the write to enable a peripheral
* before the the peripheral is actually enabled. During this time, attempts
* to access the peripheral result in a bus fault. Care should be taken
* to ensure that the peripheral is not accessed during this brief time
* period.
*
* Input Parameters:
* peripheral - The peripheral to enable.
*
* Returned Value:
* None.
*
****************************************************************************/
static void tiva_eeprom_enable(unsigned long peripheral)
{
uintptr_t regaddr;
uint32_t regval;
/* See if the peripheral index is 15, indicating a peripheral that is
* accessed via the SYSCTL_RCGCperiph registers.
*/
if ((peripheral & 0xf0000000) == 0xf0000000)
{
/* Enable this peripheral. */
regaddr = PERIPHADDR(TIVA_SYSCON_RCGC_BASE + ((peripheral & 0xff00) >> 8),
peripheral & 0xff);
putreg32(1, regaddr);
}
else
{
/* Enable this peripheral. */
regaddr = g_pulrcgc_regs[SYSCTL_PERIPH_INDEX(peripheral)];
regval = getreg32(regaddr);
regval |= SYSCTL_PERIPH_MASK(peripheral);
putreg32(regval, regaddr);
}
}
/****************************************************************************
* Name: tiva_eeprom_reset
*
* Description:
* Performs a software reset of the EEPROM peripheral.
*
* This function performs a software reset of the specified peripheral. An
* individual peripheral reset signal is asserted for a brief period and then
* de-asserted, returning the internal state of the peripheral to its reset
* condition.
*
* Input Parameters:
* peripheral - The peripheral to reset.
*
* Returned Value:
* None.
*
****************************************************************************/
static void tiva_eeprom_reset(uint32_t peripheral)
{
volatile uint_fast8_t delay;
uintptr_t regaddr;
/* Put the peripheral into the reset state. */
regaddr = PERIPHADDR(TIVA_SYSCON_SR_BASE + ((peripheral & 0xff00) >> 8),
peripheral & 0xff);
putreg32(1, regaddr);
/* Delay for a little bit. */
for (delay = 0; delay < 16; delay++)
{
}
/* Take the peripheral out of the reset state. */
putreg32(0, regaddr);
}
/****************************************************************************
* Name: tiva_eeprom_waitdone
*
* Description:
* Block until the EEPROM peripheral is not busy.
*
****************************************************************************/
static void tiva_eeprom_waitdone(void)
{
/* Is the EEPROM still busy? */
while (getreg32(TIVA_EEPROM_EEDONE) & EEPROM_EEDONE_WORKING)
{
/* Spin while EEPROM is busy. */
}
}
/****************************************************************************
* Name:tiva_eeprom_sectormask_set
*
* Description:
* This function implements a workaround for a bug in Blizzard rev A silicon.
* It ensures that only the 1KB flash sector containing a given EEPROM
* address is erased if an erase/copy operation is required as a result of
* a following EEPROM write.
*
****************************************************************************/
#if 0 /* Not used */
static void tiva_eeprom_sectormask_set(uint32_t address)
{
uint32_t mask;
/* Determine which page contains the passed EEPROM address. The 2KB EEPROM
* is implemented in 16KB of flash with each 1KB sector of flash holding
* values for 32 consecutive EEPROM words (or 128 bytes).
*/
mask = ~(1 << (address >> 7));
tiva_delay(10);
putreg32(3, 0x400fd0fc);
tiva_delay(10);
putreg32(mask, 0x400ae2c0);
tiva_delay(10);
putreg32(0, 0x400fd0fc);
tiva_delay(10);
}
#endif
/****************************************************************************
* Name: tiva_eeprom_sectormask_clear
*
* Description:
* Clear the FSM sector erase mask to ensure that any following main array
* flash erase operations operate as expected.
*
****************************************************************************/
#if 0 /* Not used */
static void tiva_eeprom_sectormask_clear(void)
{
tiva_delay(10);
putreg32(3, 0x400fd0fc);
tiva_delay(10);
putreg32(0, 0x400ae2c0);
tiva_delay(10);
putreg32(0, 0x400fd0fc);
tiva_delay(10);
}
#endif
/****************************************************************************
* Name: tiva_eeprom_write
*
* Description:
* Writes data to the EEPROM.
*
* This function may be called to write data into the EEPROM at a given
* word-aligned address. The call is synchronous and returns only after
* all data has been written or an error occurs.
*
* Input Parameters:
* data - Points to the first word of data to write to the EEPROM.
* address - Defines the byte address within the EEPROM that the data
* is to be written to. This value must be a multiple of 4.
* count - defines the number of bytes of data that is to be written.
* This value must be a multiple of 4.
*
* Returned Value:
* Returns 0 on success or non-zero values on failure. Failure codes
* are logical OR combinations of EEPROM_RC_WRBUSY, EEPROM_RC_NOPERM,
* EEPROM_RC_WKCOPY, EEPROM_RC_WKERASE, and EEPROM_RC_WORKING.
*
****************************************************************************/
#ifdef CONFIG_MTD_BYTE_WRITE
static ssize_t tiva_eeprom_write(FAR struct mtd_dev_s *dev, off_t offset,
size_t nbytes, FAR const uint8_t *buf)
{
FAR uint32_t *data = (uint32_t*)buf;
size_t remaining;
uint32_t status;
uint32_t regval;
do
{
/* Read the status. */
status = getreg32(TIVA_EEPROM_EEDONE);
}
while (status & EEPROM_EEDONE_WORKING);
/* Set the block and offset appropriately to program the first word. */
putreg32(EEPROM_ADDR2BLOCK(offset), TIVA_EEPROM_EEBLOCK);
putreg32(EEPROM_ADDR2OFFSET(offset), TIVA_EEPROM_EEOFFSET);
/* Convert the byte count to a word count. */
remaining = nbytes >> 2;
nbytes &= ~3;;
/* Write each word in turn. */
while (remaining)
{
/* Write the next word through the autoincrementing register. */
putreg32(*data, TIVA_EEPROM_EERDWRINC);
/* Wait a few cycles. In some cases, the WRBUSY bit is not set
* immediately and this prevents us from dropping through the polling
* loop before the bit is set.
*/
tiva_delay(10);
/* Wait for the write to complete. */
do
{
/* Read the status. */
status = getreg32(TIVA_EEPROM_EEDONE);
}
while (status & EEPROM_EEDONE_WORKING);
/* Make sure we completed the write without errors. Note that we
* must check this per-word because write permission can be set per
* block resulting in only a section of the write not being performed.
*/
if (status & EEPROM_EEDONE_NOPERM)
{
return status;
}
/* Move on to the next word. */
data++;
remaining--;
/* Do we need to move to the next block? This is the case if the
* offset register has just wrapped back to 0. Note that we only
* write the block register if we have more data to read. If this
* register is written, the hardware expects a read or write operation
* next. If a mass erase is requested instead, the mass erase will
* fail.
*/
if (remaining > 0 && (getreg32(TIVA_EEPROM_EEOFFSET) == 0))
{
regval = getreg32(TIVA_EEPROM_EEBLOCK);
putreg32(regval + 1, TIVA_EEPROM_EEBLOCK);
}
}
#if 0
/* Clear the sector protection bits to prevent possible problems when
* programming the main flash array later.
*/
if (CLASS_IS_TM4C123 && REVISION_IS_A0)
{
tiva_eeprom_sectormask_clear();
}
#endif
/* Return the current status to the caller. */
return nbytes;
}
#endif
/****************************************************************************
* Name: tiva_eeprom_read
*
* Description:
* Reads data from the EEPROM.
*
* This function may be called to read a number of words of data from a
* word-aligned address within the EEPROM. Data read is copied into the
* buffer pointed to by the \e data parameter.
*
* Input Parameters:
* data - A pointer to storage for the data read from the EEPROM.
* This pointer must point to at least 'count' bytes of available
* memory.
* address - The byte address within the EEPROM from which data is
* to be read. This value must be a multiple of 4.
* count - The number of bytes of data to read from the EEPROM.
* This value must be a multiple of 4.
*
* Returned Value:
* None.
*
****************************************************************************/
static ssize_t tiva_eeprom_read(FAR struct mtd_dev_s *dev, off_t offset,
size_t nbytes, FAR uint8_t *buf)
{
FAR uint32_t *data = (uint32_t*)buf;
size_t remaining;
uint32_t regval;
/* Set the block and offset appropriately to read the first word. */
putreg32(EEPROM_ADDR2BLOCK(offset), TIVA_EEPROM_EEBLOCK);
putreg32(EEPROM_ADDR2OFFSET(offset), TIVA_EEPROM_EEOFFSET);
/* Convert the byte count to a word count. */
remaining = nbytes >> 2;
nbytes &= ~3;
/* Read each word in turn. */
while (remaining > 0)
{
/* Read the next word through the auto-incrementing register. */
*data = getreg32(TIVA_EEPROM_EERDWRINC);
/* Move on to the next word. */
data++;
remaining--;
/* Do we need to move to the next block? This is the case if the
* offset register has just wrapped back to 0. Note that we only
* write the block register if we have more data to read. If this
* register is written, the hardware expects a read or write operation
* next. If a mass erase is requested instead, the mass erase will
* fail.
*/
if (remaining > 0 && (getreg32(TIVA_EEPROM_EEOFFSET) == 0))
{
regval = getreg32(TIVA_EEPROM_EEBLOCK);
putreg32(regval + 1, TIVA_EEPROM_EEBLOCK);
}
}
return nbytes;
}
/****************************************************************************
* Unimplemented Methods
****************************************************************************/
static int tiva_eeprom_erase(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks)
{
return -ENOSYS;
}
static ssize_t tiva_eeprom_bread(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR uint8_t *buf)
{
return -ENOSYS;
}
ssize_t tiva_eeprom_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR const uint8_t *buf)
{
return -ENOSYS;
}
static int tiva_eeprom_ioctl(FAR struct mtd_dev_s *dev, int cmd,
unsigned long arg)
{
return -ENOSYS;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: tiva_eeprom_initialize
*
* Description:
* Performs any necessary recovery in case of power failures during write.
*
* This function must be called after tiva_eeprom_enable() and before
* the EEPROM is accessed. It is used to check for errors in the EEPROM state
* such as from power failure during a previous write operation. The function
* detects these errors and performs as much recovery as possible.
*
* If -ENODEV is returned, the EEPROM was unable to recover its
* state. If power is stable when this occurs, this indicates a fatal
* error and is likely an indication that the EEPROM memory has exceeded its
* specified lifetime write/erase specification. If the supply voltage is
* unstable when this return code is observed, retrying the operation once the
* voltage is stabilized may clear the error.
*
* Failure to call this function after a reset may lead to incorrect operation
* or permanent data loss if the EEPROM is later written.
*
* Returned Value:
* Returns OK if no errors were detected or -ENODEV if the EEPROM
* peripheral cannot currently recover from an interrupted write or erase
* operation.
*
****************************************************************************/
int tiva_eeprom_initialize(void)
{
uint32_t status;
tiva_eeprom_enable(SYSCTL_PERIPH_EEPROM0);
/* Insert a small delay (6 cycles + call overhead) to guard against the
* possibility that this function is called immediately after the EEPROM
* peripheral is enabled. Without this delay, there is a slight chance
* that the first EEPROM register read will fault if you are using a
* compiler with a ridiculously good optimizer!
*/
tiva_delay(2);
/* Make sure the EEPROM has finished any ongoing processing. */
tiva_eeprom_waitdone();
/* Read the EESUPP register to see if any errors have been reported. */
status = getreg32(TIVA_EEPROM_EESUPP);
/* Did an error of some sort occur during initialization? */
if (status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY))
{
return -ENODEV;
}
/* Perform a second EEPROM reset. */
tiva_eeprom_reset(SYSCTL_PERIPH_EEPROM0);
/* Wait for the EEPROM to complete its reset processing once again. */
tiva_delay(2);
tiva_eeprom_waitdone();
/* Read EESUPP once again to determine if any error occurred. */
status = getreg32(TIVA_EEPROM_EESUPP);
/* Was an error reported following the second reset? */
if (status & (EEPROM_EESUPP_PRETRY | EEPROM_EESUPP_ERETRY))
{
return -ENODEV;
}
/* The EEPROM does not indicate that any error occurred. */
return OK;
}
/****************************************************************************
* Name: tiva_eeprom_instance
*
* Description:
* Create and initialize an MTD device instance. MTD devices are not
* registered in the file system, but are created as instances that can
* be bound to other functions (such as a block or character driver front
* end).
*
****************************************************************************/
FAR struct mtd_dev_s *tiva_eeprom_instance(void)
{
/* Return the implementation-specific state structure as the MTD device */
return (FAR struct mtd_dev_s *)&g_eeprom_dev;
}

94
arch/arm/src/tiva/tiva_eeprom.h Normal file
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@ -0,0 +1,94 @@
/****************************************************************************
* arch/arm/src/tiva/tiva_eeprom.h
*
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
* Author: Shirshak Sengupta <sgshirshak@gmail.com>
* Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_TIVA_TIVA_EEPROM_H
#define __ARCH_ARM_SRC_TIVA_TIVA_EEPROM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include "chip/tiva_eeprom.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: tiva_eeprom_initialize
*
* Description:
* Performs any necessary recovery in case of power failures during write.
*
* This function must be called after tiva_eeprom_enable() and before
* the EEPROM is accessed. It is used to check for errors in the EEPROM state
* such as from power failure during a previous write operation. The function
* detects these errors and performs as much recovery as possible.
*
* If -ENODEV is returned, the EEPROM was unable to recover its
* state. If power is stable when this occurs, this indicates a fatal
* error and is likely an indication that the EEPROM memory has exceeded its
* specified lifetime write/erase specification. If the supply voltage is
* unstable when this return code is observed, retrying the operation once the
* voltage is stabilized may clear the error.
*
* Failure to call this function after a reset may lead to incorrect operation
* or permanent data loss if the EEPROM is later written.
*
* Returned Value:
* Returns OK if no errors were detected or -ENODEV if the EEPROM
* peripheral cannot currently recover from an interrupted write or erase
* operation.
*
****************************************************************************/
int tiva_eeprom_initialize(void);
/****************************************************************************
* Name: tiva_eeprom_instance
*
* Description:
* Create and initialize an MTD device instance. MTD devices are not
* registered in the file system, but are created as instances that can
* be bound to other functions (such as a block or character driver front
* end).
*
****************************************************************************/
struct mtd_dev_s; /* Forward reference */
FAR struct mtd_dev_s *tiva_eeprom_instance(void);
#endif /* __ARCH_ARM_SRC_TIVA_TIVA_EEPROM_H */

19
arch/arm/src/tiva/tiva_start.c
View File

@ -52,20 +52,9 @@
#include "tiva_lowputc.h"
#include "tiva_syscontrol.h"
#include "tiva_userspace.h"
#include "tiva_eeprom.h"
#include "tiva_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
@ -160,6 +149,12 @@ void __start(void)
tiva_boardinitialize();
showprogress('F');
#ifdef CONFIG_TIVA_EEPROM
/*Initialize the EEPROM */
tiva_eeprom_initialize();
#endif
/* Then start NuttX */
showprogress('\r');

8
arch/arm/src/tiva/tiva_syscontrol.c
View File

@ -78,14 +78,6 @@
#define SLOW_OSCDELAY (4*1024)
#define PLLLOCK_DELAY (32*1024)
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/