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Correct some typos int he MPADDRCS register address definitions

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This commit is contained in:
Gregory Nutt 2013-08-02 12:06:11 -06:00
parent b00d72a7f2
commit 08a1ff5c79
1 changed files with 25 additions and 25 deletions
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50
arch/arm/src/sama5/chip/sam_mpddrc.h
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@ -81,31 +81,31 @@
/* MPDDRC Register Addresses ********************************************************/
#define SAM_MPDDRC_MR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_MR_OFFSET)
#define SAM_MPDDRC_RTR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_RTR_OFFSET)
#define SAM_MPDDRC_CR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_CR_OFFSET)
#define SAM_MPDDRC_TPR0 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_TPR0_OFFSET)
#define SAM_MPDDRC_TPR1 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_TPR1_OFFSET)
#define SAM_MPDDRC_TPR2 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_TPR2_OFFSET)
#define SAM_MPDDRC_LPR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_LPR_OFFSET)
#define SAM_MPDDRC_MD (SAM_MPDDRC_OFFSET+SAM_MPDDRC_MD_OFFSET)
#define SAM_MPDDRC_HS (SAM_MPDDRC_OFFSET+SAM_MPDDRC_HS_OFFSET)
#define SAM_MPDDRC_LPDDR2_LPR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_LPDDR2_LPR_OFFSET)
#define SAM_MPDDRC_LPDDR2_CALMR4 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_LPDDR2_CALMR4_OFFSET)
#define SAM_MPDDRC_LPDDR2_TIMCAL (SAM_MPDDRC_OFFSET+SAM_MPDDRC_LPDDR2_TIMCAL_OFFSET)
#define SAM_MPDDRC_IO_CALIBR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_IO_CALIBR_OFFSET)
#define SAM_MPDDRC_OCMS (SAM_MPDDRC_OFFSET+SAM_MPDDRC_OCMS_OFFSET)
#define SAM_MPDDRC_OCMS_KEY1 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_OCMS_KEY1_OFFSET)
#define SAM_MPDDRC_OCMS_KEY2 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_OCMS_KEY2_OFFSET)
#define SAM_MPDDRC_DLL_MOR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_MOR_OFFSET)
#define SAM_MPDDRC_DLL_SOR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SOR_OFFSET)
#define SAM_MPDDRC_DLL_MS (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_MS_OFFSET)
#define SAM_MPDDRC_DLL_SS0 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SS0_OFFSET)
#define SAM_MPDDRC_DLL_SS1 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SS1_OFFSET)
#define SAM_MPDDRC_DLL_SS2 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SS2_OFFSET)
#define SAM_MPDDRC_DLL_SS3 (SAM_MPDDRC_OFFSET+SAM_MPDDRC_DLL_SS3_OFFSET)
#define SAM_MPDDRC_WPCR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_WPCR_OFFSET)
#define SAM_MPDDRC_WPSR (SAM_MPDDRC_OFFSET+SAM_MPDDRC_WPSR_OFFSET)
#define SAM_MPDDRC_MR (SAM_MPDDRC_VBASE+SAM_MPDDRC_MR_OFFSET)
#define SAM_MPDDRC_RTR (SAM_MPDDRC_VBASE+SAM_MPDDRC_RTR_OFFSET)
#define SAM_MPDDRC_CR (SAM_MPDDRC_VBASE+SAM_MPDDRC_CR_OFFSET)
#define SAM_MPDDRC_TPR0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_TPR0_OFFSET)
#define SAM_MPDDRC_TPR1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_TPR1_OFFSET)
#define SAM_MPDDRC_TPR2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_TPR2_OFFSET)
#define SAM_MPDDRC_LPR (SAM_MPDDRC_VBASE+SAM_MPDDRC_LPR_OFFSET)
#define SAM_MPDDRC_MD (SAM_MPDDRC_VBASE+SAM_MPDDRC_MD_OFFSET)
#define SAM_MPDDRC_HS (SAM_MPDDRC_VBASE+SAM_MPDDRC_HS_OFFSET)
#define SAM_MPDDRC_LPDDR2_LPR (SAM_MPDDRC_VBASE+SAM_MPDDRC_LPDDR2_LPR_OFFSET)
#define SAM_MPDDRC_LPDDR2_CALMR4 (SAM_MPDDRC_VBASE+SAM_MPDDRC_LPDDR2_CALMR4_OFFSET)
#define SAM_MPDDRC_LPDDR2_TIMCAL (SAM_MPDDRC_VBASE+SAM_MPDDRC_LPDDR2_TIMCAL_OFFSET)
#define SAM_MPDDRC_IO_CALIBR (SAM_MPDDRC_VBASE+SAM_MPDDRC_IO_CALIBR_OFFSET)
#define SAM_MPDDRC_OCMS (SAM_MPDDRC_VBASE+SAM_MPDDRC_OCMS_OFFSET)
#define SAM_MPDDRC_OCMS_KEY1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_OCMS_KEY1_OFFSET)
#define SAM_MPDDRC_OCMS_KEY2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_OCMS_KEY2_OFFSET)
#define SAM_MPDDRC_DLL_MOR (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_MOR_OFFSET)
#define SAM_MPDDRC_DLL_SOR (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SOR_OFFSET)
#define SAM_MPDDRC_DLL_MS (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_MS_OFFSET)
#define SAM_MPDDRC_DLL_SS0 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SS0_OFFSET)
#define SAM_MPDDRC_DLL_SS1 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SS1_OFFSET)
#define SAM_MPDDRC_DLL_SS2 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SS2_OFFSET)
#define SAM_MPDDRC_DLL_SS3 (SAM_MPDDRC_VBASE+SAM_MPDDRC_DLL_SS3_OFFSET)
#define SAM_MPDDRC_WPCR (SAM_MPDDRC_VBASE+SAM_MPDDRC_WPCR_OFFSET)
#define SAM_MPDDRC_WPSR (SAM_MPDDRC_VBASE+SAM_MPDDRC_WPSR_OFFSET)
/* MPDDRC Register Bit Definitions **************************************************/