Add clock initialization logic for the Nucleus2g boad
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2741 42af7a65-404d-4744-a932-0658087f49c3
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@ -51,8 +51,9 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
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# Required LPC17xx files
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CHIP_ASRCS =
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CHIP_CSRCS = lpc17_allocateheap.c lpc17_gpio.c lpc17_gpioint.c lpc17_irq.c \
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lpc17_lowputc.c lpc17_serial.c lpc17_start.c lpc17_timerisr.c
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CHIP_CSRCS = lpc17_allocateheap.c lpc17_clockconfig.c lpc17_gpio.c \
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lpc17_gpioint.c lpc17_irq.c lpc17_lowputc.c lpc17_serial.c \
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lpc17_start.c lpc17_timerisr.c
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# Configuration-dependent LPC17xx files
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206
arch/arm/src/lpc17xx/lpc17_clockconfig.c
Executable file
206
arch/arm/src/lpc17xx/lpc17_clockconfig.c
Executable file
@ -0,0 +1,206 @@
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/****************************************************************************
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* arch/arm/src/lpc17xx/lpc17_clockconfig.c
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* arch/arm/src/chip/lpc17_clockconfig.c
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include "up_arch.h"
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#include "up_internal.h"
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#include "lpc17_internal.h"
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#include "lpc17_syscon.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/************************************************************************************
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* Name: lpc17_clockconfig
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*
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* Description:
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* Called to initialize the LPC17xx. This does whatever setup is needed to put the
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* SoC in a usable state. This includes the initialization of clocking using the
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* settings in board.h.
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*
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************************************************************************************/
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void lpc17_clockconfig(void)
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{
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/* Enable the main oscillator (or not) and the frequency range of the main oscillator */
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putreg32(BOARD_SCS_VALUE, LPC17_SYSCON_SCS);
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/* Wait for the main oscillator to be ready. */
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#ifdef CONFIG_LPC17_MAINOSC
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while ((getreg32(LPC17_SYSCON_SCS) & SYSCON_SCS_OSCSTAT) == 0);
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#endif
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/* Setup up the divider value for the CPU clock. The output of the divider is CCLK.
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* The input to the divider (PLLCLK) is equal to SYSCLK unless PLL0 is enabled. CCLK
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* will be further divided to produce peripheral clocks, but that peripheral clock
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* setup is performed in the peripheral device drivers. Here only CCLK is
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* configured.
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*/
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putreg32(BOARD_CCLKCFG_VALUE, LPC17_SYSCON_CCLKCFG);
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/* PLL0 is used to generate the CPU clock divider input (PLLCLK). */
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#if CONFIG_LPC17_PLL0
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/* Select the PLL0 source clock, multiplier, and pre-divider values. NOTE that
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* a special "feed" sequence must be written to the PLL0FEED register in order
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* for changes to the PLL0CFG register to take effect.
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*/
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putreg32(BOARD_CLKSRCSEL_VALUE, LPC17_SYSCON_CLKSRCSEL);
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putreg32(BOARD_PLL0CFG_VALUE, LPC17_SYSCON_PLL0CFG);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
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* PLL0FEED register in order for changes to the PLL0CON register to take effect.
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*/
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putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL0CON);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Wait for PLL0 to lock */
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & SYSCON_PLL0STAT_PLOCK) == 0);
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/* Enable and connect PLL0 */
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putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL0CON);
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putreg32(0xaa, LPC17_SYSCON_PLL0FEED);
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putreg32(0x55, LPC17_SYSCON_PLL0FEED);
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_SYSCON_PLL0STAT) & (SYSCON_PLL0STAT_PLLE|SYSCON_PLL0STAT_PLLC)) == 0);
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#endif
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/* PLL1 receives its clock input from the main oscillator only and can be used to
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* provide a fixed 48 MHz clock only to the USB subsystem (if that clock cannot be
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* obtained from PLL0).
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*/
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#ifdef CONFIG_LPC17_PLL1
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/* Select the PLL1 multiplier, and pre-divider values. NOTE that a special "feed"
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* sequence must be written to the PLL1FEED register in order for changes to the
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* PLL1CFG register to take effect.
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*/
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putreg32(BOARD_PLL1CFG_VALUE, LPC17_SYSCON_PLL1CFG);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Enable the PLL. NOTE that a special "feed" sequence must be written to the
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* PLL1FEED register in order for changes to the PLL1CON register to take effect.
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*/
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putreg32(SYSCON_PLLCON_PLLE, LPC17_SYSCON_PLL1CON);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Wait for PLL1 to lock */
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & SYSCON_PLL1STAT_PLOCK) == 0);
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/* Enable and connect PLL1 */
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putreg32(SYSCON_PLLCON_PLLE|SYSCON_PLLCON_PLLC, LPC17_SYSCON_PLL1CON);
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putreg32(0xaa, LPC17_SYSCON_PLL1FEED);
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putreg32(0x55, LPC17_SYSCON_PLL1FEED);
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/* Wait for PLL to report that it is connected and enabled */
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while ((getreg32(LPC17_SYSCON_PLL1STAT) & (SYSCON_PLL1STAT_PLLE|SYSCON_PLL1STAT_PLLC)) == 0);
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#else
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/* Otherwise, setup up the USB clock divider to generate the USB clock from PLL0 */
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putreg32(BOARD_USBCLKCFG_VALUE, LPC17_SYSCON_USBCLKCFG);
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#endif
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/* Disable all peripheral clocks. They must be configured by each device driver
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* when the device driver is initialized.
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*/
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putreg32(0, LPC17_SYSCON_PCLKSEL0);
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putreg32(0, LPC17_SYSCON_PCLKSEL1);
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/* Disable power to all peripherals. They must be re-powered one at a time by each
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* device driver when the driver is initialized.
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*/
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putreg32(0, LPC17_SYSCON_PCONP);
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/* Disable CLKOUT */
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putreg32(0, LPC17_SYSCON_CLKOUTCFG);
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/* Configure FLASH */
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#ifdef CONFIG_LP17_FLASH
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putreg32(BOARD_FLASHCFG_VALUE, LPC17_SYSCON_FLASHCFG);
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#endif
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}
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@ -213,8 +213,8 @@
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#define SYSCON_CLKSRCSEL_SHIFT (0) /* Bits 0-1: Clock selection */
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#define SYSCON_CLKSRCSEL_MASK (3 << SYSCON_CLKSRCSEL_SHIFT)
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# define SYSCON_CLKSRCSEL_INTRC (0 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = internal RC oscillator */
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# define SYSCON_CLKSRCSEL_RTC (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */
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# define SYSCON_CLKSRCSEL_MAIN (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */
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# define SYSCON_CLKSRCSEL_MAIN (1 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = main oscillator */
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# define SYSCON_CLKSRCSEL_RTC (2 << SYSCON_CLKSRCSEL_SHIFT) /* PLL0 source = RTC oscillator */
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/* Bits 2-31: Reserved */
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/* Clocking and power control - Phase locked loops */
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@ -42,6 +42,7 @@
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#include <stdint.h>
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#include <time.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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@ -286,6 +286,9 @@ Nucleus 2G Configuration Options
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the delay actually is 100 seconds.
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Individual subsystems can be enabled:
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CONFIG_LPC17_MAINOSC=y
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CONFIG_LPC17_PLL0=y
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CONFIG_LPC17_PLL1=n
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CONFIG_LPC17_ETHERNET=n
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CONFIG_LPC17_USBHOST=n
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CONFIG_LPC17_USBOTG=n
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@ -315,6 +318,7 @@ Nucleus 2G Configuration Options
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CONFIG_LPC17_ADC=n
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CONFIG_LPC17_DAC=n
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CONFIG_LPC17_GPDMA=n
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CONFIG_LP17_FLASH=n
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LPC17xx specific device driver settings
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@ -48,9 +48,78 @@
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* NOTE: The following definitions require lpc17_syscon.h. It is not included here
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* because the including C file may not have that file in its include path.
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*/
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#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */
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#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */
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#define BOARD_RTCCLK_FREQUENCY (32000) /* RTC oscillator frequency */
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#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
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/* This is the clock setup we configure for:
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*
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* SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source
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* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1
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* CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6
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*/
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#define LPC17_CCLK 80000000 /* 80Mhz*/
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/* Select the main oscillator as the frequency source. SYSCLK is then the frequency
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* of the main osciallator.
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*/
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#undef CONFIG_LPC17_MAINOSC
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#define CONFIG_LPC17_MAINOSC 1
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#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN
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/* Select the main oscillator and CCLK divider. The output of the divider is CCLK.
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* The input to the divider (PLLCLK) will be determined by the PLL output.
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*/
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#define BOARD_CCLKCFG_DIVIDER 6
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#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT)
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/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK).
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*
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* Source clock: Main oscillator
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* PLL0 Multiplier value (M): 20
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* PLL0 Pre-divider value (N): 1
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*/
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#undef CONFIG_LPC17_PLL0
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#define CONFIG_LPC17_PLL0 1
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#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN
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#define BOARD_PLL0CFG_MSEL 20
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#define BOARD_PLL0CFG_NSEL 1
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#define BOARD_PLL0CFG_VALUE \
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(((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \
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((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT))
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/* PLL1 -- Not used. */
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#undef CONFIG_LPC17_PLL0
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#define BOARD_PLL1CFG_MSEL 36
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#define BOARD_PLL1CFG_NSEL 1
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#define BOARD_PLL1CFG_VALUE \
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(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
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((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
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/* USB divider. This divder is used when PLL1 is not enabled to get the USB clock
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* from PLL0:
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*
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* USBCLK = PLL0CLK / 10 = 48MHz
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*/
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#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10
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/* FLASH Configuration */
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#undef CONFIG_LP17_FLASH
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#define CONFIG_LP17_FLASH 1
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#define BOARD_FLASHCFG_VALUE 0x0000303a
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/* LED definitions ******************************************************************/
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@ -101,6 +101,7 @@ CONFIG_LPC17_BUILDROOT=y
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# Individual subsystems can be enabled:
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#
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# Individual subsystems can be enabled:
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# (MAINOSC, PLL0, PLL1 and FLASH are controlled in board.h)
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CONFIG_LPC17_ETHERNET=n
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CONFIG_LPC17_USBHOST=n
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CONFIG_LPC17_USBOTG=n
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