TMS570: Add a little more IRQ/FIQ logic
This commit is contained in:
Gregory Nutt
parent
caad954b01
commit
092c681157
@ -238,6 +238,7 @@ config ARCH_CHIP_TMS570
|
||||
select ARCH_HAVE_LOWVECTORS
|
||||
select ARCH_HAVE_RAMFUNCS
|
||||
select ARMV7R_MEMINIT
|
||||
select ARMV7R_HAVE_DECODEFIQ
|
||||
---help---
|
||||
TI TMS570 family
|
||||
|
||||
|
||||
@ -885,7 +885,7 @@ arm_vectorfiq:
|
||||
stmia r0, {r1-r4}
|
||||
#endif
|
||||
|
||||
/* Then call the IRQ handler with interrupts disabled. */
|
||||
/* Then call the FIQ handler with interrupts disabled. */
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
|
||||
@ -172,9 +172,14 @@ config ARMV7R_OABI_TOOLCHAIN
|
||||
Most of the older buildroot toolchains are OABI and are named
|
||||
arm-nuttx-elf- vs. arm-nuttx-eabi-
|
||||
|
||||
config ARMV7R_HAVE_DECODEFIQ
|
||||
bool
|
||||
default n
|
||||
|
||||
config ARMV7R_DECODEFIQ
|
||||
bool "FIQ Handler"
|
||||
default n
|
||||
depends on ARMV7R_HAVE_DECODEFIQ
|
||||
---help---
|
||||
Select this option if your platform supports the function
|
||||
arm_decodefiq().
|
||||
|
||||
@ -112,8 +112,8 @@ up_fullcontextrestore:
|
||||
vmsr fpscr, r2 /* Restore the FPCSR */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
/* For the kernel build, we need to be able to transition gracefully
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* For the protected build, we need to be able to transition gracefully
|
||||
* between kernel- and user-mode tasks. Here we do that with a system
|
||||
* call; the system call will execute in kernel mode and but can return
|
||||
* to either user or kernel mode.
|
||||
|
||||
@ -45,7 +45,7 @@
|
||||
#include "up_internal.h"
|
||||
|
||||
#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
|
||||
defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS)
|
||||
defined(CONFIG_BUILD_PROTECTED)) && !defined(CONFIG_DISABLE_SIGNALS)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -67,7 +67,7 @@
|
||||
* Name: up_signal_dispatch
|
||||
*
|
||||
* Description:
|
||||
* In this kernel mode build, this function will be called to execute a
|
||||
* In the protected mode build, this function will be called to execute a
|
||||
* a signal handler in user-space. When the signal is delivered, a
|
||||
* kernel-mode stub will first run to perform some housekeeping functions.
|
||||
* This kernel-mode stub will then be called transfer control to the user
|
||||
@ -116,4 +116,4 @@ void up_signal_dispatch(_sa_sigaction_t sighand, int signo,
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* (CONFIG_BUILD_PROTECTED || CONFIG_BUILD_KERNEL) && !CONFIG_DISABLE_SIGNALS */
|
||||
#endif /* (CONFIG_BUILD_PROTECTED || CONFIG_BUILD_PROTECTED) && !CONFIG_DISABLE_SIGNALS */
|
||||
|
||||
@ -160,7 +160,7 @@ static void dispatch_syscall(void)
|
||||
uint32_t *arm_syscall(uint32_t *regs)
|
||||
{
|
||||
uint32_t cmd;
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
uint32_t cpsr;
|
||||
#endif
|
||||
|
||||
@ -217,7 +217,7 @@ uint32_t *arm_syscall(uint32_t *regs)
|
||||
*/
|
||||
|
||||
regs[REG_PC] = rtcb->xcp.syscall[index].sysreturn;
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
regs[REG_CPSR] = rtcb->xcp.syscall[index].cpsr;
|
||||
#endif
|
||||
/* The return value must be in R0-R1. dispatch_syscall() temporarily
|
||||
@ -254,7 +254,7 @@ uint32_t *arm_syscall(uint32_t *regs)
|
||||
* R1 = restoreregs
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
case SYS_context_restore:
|
||||
{
|
||||
/* Replace 'regs' with the pointer to the register set in
|
||||
@ -280,7 +280,7 @@ uint32_t *arm_syscall(uint32_t *regs)
|
||||
* R3 = argv
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
case SYS_task_start:
|
||||
{
|
||||
/* Set up to return to the user-space _start function in
|
||||
@ -313,7 +313,7 @@ uint32_t *arm_syscall(uint32_t *regs)
|
||||
* R2 = arg
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_DISABLE_PTHREAD)
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_PTHREAD)
|
||||
case SYS_pthread_start:
|
||||
{
|
||||
/* Set up to return to the user-space pthread start-up function in
|
||||
@ -334,7 +334,7 @@ uint32_t *arm_syscall(uint32_t *regs)
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_DISABLE_SIGNALS)
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_SIGNALS)
|
||||
/* R0=SYS_signal_handler: This a user signal handler callback
|
||||
*
|
||||
* void signal_handler(_sa_sigaction_t sighand, int signo,
|
||||
@ -399,7 +399,7 @@ uint32_t *arm_syscall(uint32_t *regs)
|
||||
break;
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_BUILD_KERNEL) && !defined(CONFIG_DISABLE_SIGNALS)
|
||||
#if defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_DISABLE_SIGNALS)
|
||||
/* R0=SYS_signal_handler_return: This a user signal handler callback
|
||||
*
|
||||
* void signal_handler_return(void);
|
||||
@ -465,12 +465,12 @@ uint32_t *arm_syscall(uint32_t *regs)
|
||||
/* Setup to return to dispatch_syscall in privileged mode. */
|
||||
|
||||
rtcb->xcp.syscall[index].sysreturn = regs[REG_PC];
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
rtcb->xcp.syscall[index].cpsr = regs[REG_CPSR];
|
||||
#endif
|
||||
|
||||
regs[REG_PC] = (uint32_t)dispatch_syscall;
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
cpsr = regs[REG_CPSR] & ~PSR_MODE_MASK;
|
||||
regs[REG_CPSR] = cpsr | PSR_MODE_SVC;
|
||||
#endif
|
||||
|
||||
@ -128,7 +128,7 @@ arm_vectorirq:
|
||||
ldr r0, .Lirqtmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_IRQ, r4=spsr_IRQ */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
* USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -204,7 +204,7 @@ arm_vectorirq:
|
||||
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
|
||||
msr spsr, r1 /* Set the return mode SPSR */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Are we leaving in user mode? If so then we need to restore the
|
||||
* values of USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -265,7 +265,7 @@ arm_vectorsvc:
|
||||
mov r3, r14 /* Save r14 as the PC as well */
|
||||
mrs r4, spsr /* Get the saved CPSR */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
* USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -333,7 +333,7 @@ arm_vectorsvc:
|
||||
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
|
||||
msr spsr, r1 /* Set the return mode SPSR */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Are we leaving in user mode? If so then we need to restore the
|
||||
* values of USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -407,7 +407,7 @@ arm_vectordata:
|
||||
ldr r0, .Ldaborttmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_ABT, r4=spsr_ABT */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
* USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -477,7 +477,7 @@ arm_vectordata:
|
||||
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
|
||||
msr spsr_cxsf, r1 /* Set the return mode SPSR */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Are we leaving in user mode? If so then we need to restore the
|
||||
* values of USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -553,7 +553,7 @@ arm_vectorprefetch:
|
||||
ldr r0, .Lpaborttmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_ABT, r4=spsr_ABT */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
* USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -623,7 +623,7 @@ arm_vectorprefetch:
|
||||
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
|
||||
msr spsr_cxsf, r1 /* Set the return mode SPSR */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Are we leaving in user mode? If so then we need to restore the
|
||||
* values of USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -696,7 +696,7 @@ arm_vectorundefinsn:
|
||||
ldr r0, .Lundeftmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_UND, r4=spsr_UND */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
* USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -764,7 +764,7 @@ arm_vectorundefinsn:
|
||||
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
|
||||
msr spsr_cxsf, r1 /* Set the return mode SPSR */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Are we leaving in user mode? If so then we need to restore the
|
||||
* values of USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
@ -839,7 +839,7 @@ arm_vectorfiq:
|
||||
ldr r0, .Lfiqtmp /* Points to temp storage */
|
||||
ldmia r0, {r3, r4} /* Recover r3=lr_SVC, r4=spsr_SVC */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Did we enter from user mode? If so then we need get the values of
|
||||
* USER mode rr13(sp) and r14(lr).
|
||||
*/
|
||||
@ -885,7 +885,7 @@ arm_vectorfiq:
|
||||
stmia r0, {r1-r4}
|
||||
#endif
|
||||
|
||||
/* Then call the IRQ handler with interrupts disabled. */
|
||||
/* Then call the FIQ handler with interrupts disabled. */
|
||||
|
||||
mov fp, #0 /* Init frame pointer */
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
@ -915,7 +915,7 @@ arm_vectorfiq:
|
||||
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
|
||||
msr spsr, r1 /* Set the return mode SPSR */
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* Are we leaving in user mode? If so then we need to restore the
|
||||
* values of USER mode r13(sp) and r14(lr).
|
||||
*/
|
||||
|
||||
@ -54,11 +54,11 @@
|
||||
|
||||
/* Configuration ********************************************************************/
|
||||
/* This logic uses one system call for the syscall return. So a minimum of one
|
||||
* syscall values must be reserved. If CONFIG_BUILD_KERNEL is defined, then four
|
||||
* syscall values must be reserved. If CONFIG_BUILD_PROTECTED is defined, then four
|
||||
* more syscall values must be reserved.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
# ifndef CONFIG_SYS_RESERVED
|
||||
# error "CONFIG_SYS_RESERVED must be defined to have the value 6"
|
||||
# elif CONFIG_SYS_RESERVED != 6
|
||||
@ -81,7 +81,7 @@
|
||||
|
||||
#define SYS_syscall_return (0)
|
||||
|
||||
#ifdef CONFIG_BUILD_KERNEL
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
/* SYS call 1:
|
||||
*
|
||||
* void up_fullcontextrestore(uint32_t *restoreregs) noreturn_function;
|
||||
@ -120,7 +120,7 @@
|
||||
|
||||
#define SYS_signal_handler_return (5)
|
||||
|
||||
#endif /* CONFIG_BUILD_KERNEL */
|
||||
#endif /* CONFIG_BUILD_PROTECTED */
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
|
||||
@ -53,6 +53,9 @@
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************************/
|
||||
|
||||
#define VIM_REGNDX(ch) ((ch) >> 5)
|
||||
#define VIM_REGBIT(ch) ((ch) & 31)
|
||||
|
||||
/* Register Offsets *********************************************************************************/
|
||||
|
||||
/* Register Offsets relative to the VIM Parity Frame */
|
||||
@ -66,24 +69,30 @@
|
||||
|
||||
#define TMS570_VIM_IRQINDEX_OFFSET 0x0000 /* IRQ Index Offset Vector Register */
|
||||
#define TMS570_VIM_FIQINDEX_OFFSET 0x0004 /* FIQ Index Offset Vector Register */
|
||||
#define TMS570_VIM_FIRQPR0_OFFSET 0x0010 /* FIQ/IRQ Program Control Register 0 */
|
||||
#define TMS570_VIM_FIRQPR1_OFFSET 0x0014 /* FIQ/IRQ Program Control Register 1 */
|
||||
#define TMS570_VIM_FIRQPR2_OFFSET 0x0018 /* FIQ/IRQ Program Control Register 2 */
|
||||
#define TMS570_VIM_INTREQ0_OFFSET 0x0020 /* Pending Interrupt Read Location Register 0 */
|
||||
#define TMS570_VIM_INTREQ1_OFFSET 0x0024 /* Pending Interrupt Read Location Register 1 */
|
||||
#define TMS570_VIM_INTREQ2_OFFSET 0x0028 /* Pending Interrupt Read Location Register 2 */
|
||||
#define TMS570_VIM_REQENASET0_OFFSET 0x0030 /* Interrupt Enable Set Register 0 */
|
||||
#define TMS570_VIM_REQENASET1_OFFSET 0x0034 /* Interrupt Enable Set Register 1 */
|
||||
#define TMS570_VIM_REQENASET2_OFFSET 0x0038 /* Interrupt Enable Set Register 2 */
|
||||
#define TMS570_VIM_REQENACLR0_OFFSET 0x0040 /* Interrupt Enable Clear Register 0 */
|
||||
#define TMS570_VIM_REQENACLR1_OFFSET 0x0044 /* Interrupt Enable Clear Register 1 */
|
||||
#define TMS570_VIM_REQENACLR2_OFFSET 0x0048 /* Interrupt Enable Clear Register 2 */
|
||||
#define TMS570_VIM_WAKEENASET0_OFFSET 0x0050 /* Wake-up Enable Set Register 0 */
|
||||
#define TMS570_VIM_WAKEENASET1_OFFSET 0x0054 /* Wake-up Enable Set Register 1 */
|
||||
#define TMS570_VIM_WAKEENASET2_OFFSET 0x0058 /* Wake-up Enable Set Register 2 */
|
||||
#define TMS570_VIM_WAKEENACLR0_OFFSET 0x0060 /* Wake-up Enable Clear Register 0 */
|
||||
#define TMS570_VIM_WAKEENACLR1_OFFSET 0x0064 /* Wake-up Enable Clear Register 1 */
|
||||
#define TMS570_VIM_WAKEENACLR2_OFFSET 0x0068 /* Wake-up Enable Clear Register 2 */
|
||||
#define TMS570_VIM_FIRQPR_OFFSET(n) (0x0010 + ((n) << 2))
|
||||
# define TMS570_VIM_FIRQPR0_OFFSET 0x0010 /* FIQ/IRQ Program Control Register 0 */
|
||||
# define TMS570_VIM_FIRQPR1_OFFSET 0x0014 /* FIQ/IRQ Program Control Register 1 */
|
||||
# define TMS570_VIM_FIRQPR2_OFFSET 0x0018 /* FIQ/IRQ Program Control Register 2 */
|
||||
#define TMS570_VIM_INTREQ_OFFSET(n) (0x0020 + ((n) << 2))
|
||||
# define TMS570_VIM_INTREQ0_OFFSET 0x0020 /* Pending Interrupt Read Location Register 0 */
|
||||
# define TMS570_VIM_INTREQ1_OFFSET 0x0024 /* Pending Interrupt Read Location Register 1 */
|
||||
# define TMS570_VIM_INTREQ2_OFFSET 0x0028 /* Pending Interrupt Read Location Register 2 */
|
||||
#define TMS570_VIM_REQENASET_OFFSET(n) (0x0030 + ((n) << 2))
|
||||
# define TMS570_VIM_REQENASET0_OFFSET 0x0030 /* Interrupt Enable Set Register 0 */
|
||||
# define TMS570_VIM_REQENASET1_OFFSET 0x0034 /* Interrupt Enable Set Register 1 */
|
||||
# define TMS570_VIM_REQENASET2_OFFSET 0x0038 /* Interrupt Enable Set Register 2 */
|
||||
#define TMS570_VIM_REQENACLR_OFFSET(n) (0x0040 + ((n) << 2))
|
||||
# define TMS570_VIM_REQENACLR0_OFFSET 0x0040 /* Interrupt Enable Clear Register 0 */
|
||||
# define TMS570_VIM_REQENACLR1_OFFSET 0x0044 /* Interrupt Enable Clear Register 1 */
|
||||
# define TMS570_VIM_REQENACLR2_OFFSET 0x0048 /* Interrupt Enable Clear Register 2 */
|
||||
#define TMS570_VIM_WAKEENASET_OFFSET(n) (0x0050 + ((n) << 2))
|
||||
# define TMS570_VIM_WAKEENASET0_OFFSET 0x0050 /* Wake-up Enable Set Register 0 */
|
||||
# define TMS570_VIM_WAKEENASET1_OFFSET 0x0054 /* Wake-up Enable Set Register 1 */
|
||||
# define TMS570_VIM_WAKEENASET2_OFFSET 0x0058 /* Wake-up Enable Set Register 2 */
|
||||
#define TMS570_VIM_WAKEENACLR_OFFSET(n) (0x0060 + ((n) << 2))
|
||||
# define TMS570_VIM_WAKEENACLR0_OFFSET 0x0060 /* Wake-up Enable Clear Register 0 */
|
||||
# define TMS570_VIM_WAKEENACLR1_OFFSET 0x0064 /* Wake-up Enable Clear Register 1 */
|
||||
# define TMS570_VIM_WAKEENACLR2_OFFSET 0x0068 /* Wake-up Enable Clear Register 2 */
|
||||
#define TMS570_VIM_IRQVECREG_OFFSET 0x0070 /* IRQ Interrupt Vector Register */
|
||||
#define TMS570_VIM_FIQVECREG_OFFSET 0x0074 /* FIQ Interrupt Vector Register */
|
||||
#define TMS570_VIM_CAPEVT_OFFSET 0x0078 /* Capture Event Register */
|
||||
@ -106,24 +115,30 @@
|
||||
|
||||
#define TMS570_VIM_IRQINDEX (TMS570_VIM_BASE+TMS570_VIM_IRQINDEX_OFFSET)
|
||||
#define TMS570_VIM_FIQINDEX (TMS570_VIM_BASE+TMS570_VIM_FIQINDEX_OFFSET)
|
||||
#define TMS570_VIM_FIRQPR0 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR0_OFFSET)
|
||||
#define TMS570_VIM_FIRQPR1 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR1_OFFSET)
|
||||
#define TMS570_VIM_FIRQPR2 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR2_OFFSET)
|
||||
#define TMS570_VIM_INTREQ0 (TMS570_VIM_BASE+TMS570_VIM_INTREQ0_OFFSET)
|
||||
#define TMS570_VIM_INTREQ1 (TMS570_VIM_BASE+TMS570_VIM_INTREQ1_OFFSET)
|
||||
#define TMS570_VIM_INTREQ2 (TMS570_VIM_BASE+TMS570_VIM_INTREQ2_OFFSET)
|
||||
#define TMS570_VIM_REQENASET0 (TMS570_VIM_BASE+TMS570_VIM_REQENASET0_OFFSET)
|
||||
#define TMS570_VIM_REQENASET1 (TMS570_VIM_BASE+TMS570_VIM_REQENASET1_OFFSET)
|
||||
#define TMS570_VIM_REQENASET2 (TMS570_VIM_BASE+TMS570_VIM_REQENASET2_OFFSET)
|
||||
#define TMS570_VIM_REQENACLR0 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR0_OFFSET)
|
||||
#define TMS570_VIM_REQENACLR1 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR1_OFFSET)
|
||||
#define TMS570_VIM_REQENACLR2 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR2_OFFSET)
|
||||
#define TMS570_VIM_WAKEENASET0 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET0_OFFSET)
|
||||
#define TMS570_VIM_WAKEENASET1 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET1_OFFSET)
|
||||
#define TMS570_VIM_WAKEENASET2 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET2_OFFSET)
|
||||
#define TMS570_VIM_WAKEENACLR0 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR0_OFFSET)
|
||||
#define TMS570_VIM_WAKEENACLR1 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR1_OFFSET)
|
||||
#define TMS570_VIM_WAKEENACLR2 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR2_OFFSET)
|
||||
#define TMS570_VIM_FIRQPR(n) (TMS570_VIM_BASE+TMS570_VIM_FIRQPR_OFFSET(n))
|
||||
# define TMS570_VIM_FIRQPR0 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR0_OFFSET)
|
||||
# define TMS570_VIM_FIRQPR1 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR1_OFFSET)
|
||||
# define TMS570_VIM_FIRQPR2 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR2_OFFSET)
|
||||
#define TMS570_VIM_INTREQ(n) (TMS570_VIM_BASE+TMS570_VIM_INTREQ_OFFSET(n))
|
||||
# define TMS570_VIM_INTREQ0 (TMS570_VIM_BASE+TMS570_VIM_INTREQ0_OFFSET)
|
||||
# define TMS570_VIM_INTREQ1 (TMS570_VIM_BASE+TMS570_VIM_INTREQ1_OFFSET)
|
||||
# define TMS570_VIM_INTREQ2 (TMS570_VIM_BASE+TMS570_VIM_INTREQ2_OFFSET)
|
||||
#define TMS570_VIM_REQENASET(n) (TMS570_VIM_BASE+TMS570_VIM_REQENASET_OFFSET(n))
|
||||
# define TMS570_VIM_REQENASET0 (TMS570_VIM_BASE+TMS570_VIM_REQENASET0_OFFSET)
|
||||
# define TMS570_VIM_REQENASET1 (TMS570_VIM_BASE+TMS570_VIM_REQENASET1_OFFSET)
|
||||
# define TMS570_VIM_REQENASET2 (TMS570_VIM_BASE+TMS570_VIM_REQENASET2_OFFSET)
|
||||
#define TMS570_VIM_REQENACLR(n) (TMS570_VIM_BASE+TMS570_VIM_REQENACLR_OFFSET(n))
|
||||
# define TMS570_VIM_REQENACLR0 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR0_OFFSET)
|
||||
# define TMS570_VIM_REQENACLR1 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR1_OFFSET)
|
||||
# define TMS570_VIM_REQENACLR2 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR2_OFFSET)
|
||||
#define TMS570_VIM_WAKEENASET(n) (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET_OFFSET(n))
|
||||
# define TMS570_VIM_WAKEENASET0 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET0_OFFSET)
|
||||
# define TMS570_VIM_WAKEENASET1 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET1_OFFSET)
|
||||
# define TMS570_VIM_WAKEENASET2 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET2_OFFSET)
|
||||
#define TMS570_VIM_WAKEENACLR(n) (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR_OFFSET(n))
|
||||
# define TMS570_VIM_WAKEENACLR0 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR0_OFFSET)
|
||||
# define TMS570_VIM_WAKEENACLR1 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR1_OFFSET)
|
||||
# define TMS570_VIM_WAKEENACLR2 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR2_OFFSET)
|
||||
#define TMS570_VIM_IRQVECREG (TMS570_VIM_BASE+TMS570_VIM_IRQVECREG_OFFSET)
|
||||
#define TMS570_VIM_FIQVECREG (TMS570_VIM_BASE+TMS570_VIM_FIQVECREG_OFFSET)
|
||||
#define TMS570_VIM_CAPEVT (TMS570_VIM_BASE+TMS570_VIM_CAPEVT_OFFSET)
|
||||
|
||||
@ -40,6 +40,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
@ -49,6 +50,8 @@
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "chip/tms570_vim.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
@ -86,8 +89,23 @@ void up_irqinitialize(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Set all interrupts to the default priority */
|
||||
#warning Missing logic
|
||||
/* Assign all channels to IRQs */
|
||||
|
||||
putreg32(0, TMS570_VIM_FIRQPR0);
|
||||
putreg32(0, TMS570_VIM_FIRQPR1);
|
||||
putreg32(0, TMS570_VIM_FIRQPR2);
|
||||
#ifdef TMS570_VIM_FIRQPR3
|
||||
putreg32(0, TMS570_VIM_FIRQPR3);
|
||||
#endif
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0xfffffffc, TMS570_VIM_REQENACLR0);
|
||||
putreg32(0xffffffff, TMS570_VIM_REQENACLR1);
|
||||
putreg32(0xffffffff, TMS570_VIM_REQENACLR2);
|
||||
#ifdef TMS570_VIM_REQENACLR3
|
||||
putreg32(0xffffffff, TMS570_VIM_REQENACLR3);
|
||||
#endif
|
||||
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
@ -109,31 +127,163 @@ void up_irqinitialize(void)
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
* Name: arm_decodeirq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
* This function is called from the IRQ vector handler in arm_vectors.S.
|
||||
* At this point, the interrupt has been taken and the registers have
|
||||
* been saved on the stack. This function simply needs to determine the
|
||||
* the irq number of the interrupt and then to call arm_doirq to dispatch
|
||||
* the interrupt.
|
||||
*
|
||||
* Input parameters:
|
||||
* regs - A pointer to the register save area on the stack.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
uint32_t *arm_decodeirq(uint32_t *regs)
|
||||
{
|
||||
#warning Missing logic
|
||||
#warning Missing Logic
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_decodefiq
|
||||
*
|
||||
* Description:
|
||||
* This function is called from the FIQ vector handler in arm_vectors.S.
|
||||
* At this point, the interrupt has been taken and the registers have
|
||||
* been saved on the stack. This function simply needs to determine the
|
||||
* the irq number of the interrupt and then to call arm_doirq to dispatch
|
||||
* the interrupt.
|
||||
*
|
||||
* Input parameters:
|
||||
* regs - A pointer to the register save area on the stack.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARMV7R_HAVE_DECODEFIQ
|
||||
uint32_t *arm_decodefiq(FAR uint32_t *regs)
|
||||
{
|
||||
#warning Missing Logic
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ or FIQ specified by 'channel'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int channel)
|
||||
{
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t bitmask;
|
||||
unsigned int regndx;
|
||||
|
||||
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS)
|
||||
|
||||
/* Offset to account for the "phantom" vector */
|
||||
|
||||
channel++;
|
||||
regndx = VIM_REGNDX(channel);
|
||||
channel = VIM_REGBIT(channel);
|
||||
bitmask = (1 << channel);
|
||||
|
||||
/* Disable the IRQ/FIQ by setting the corresponding REQENACLR bit. */
|
||||
|
||||
regaddr = TMS570_VIM_REQENACLR(regndx);
|
||||
regval = getreg32(regaddr);
|
||||
regaddr |= bitmask;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
* Enable the IRQ specified by 'channel'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
void up_enable_irq(int channel)
|
||||
{
|
||||
#warning Missing logic
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t bitmask;
|
||||
unsigned int regndx;
|
||||
|
||||
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS)
|
||||
|
||||
/* Offset to account for the "phantom" vector */
|
||||
|
||||
channel++;
|
||||
regndx = VIM_REGNDX(channel);
|
||||
channel = VIM_REGBIT(channel);
|
||||
bitmask = (1 << channel);
|
||||
|
||||
#ifdef CONFIG_ARMV7R_HAVE_DECODEFIQ
|
||||
/* Select IRQ (vs FIQ) by clearing the corresponding FIRQPR bit */
|
||||
|
||||
regaddr = TMS570_VIM_FIRQPR(regndx);
|
||||
regval = getreg32(regaddr);
|
||||
regaddr &= ~bitmask;
|
||||
putreg32(regval, regaddr);
|
||||
#endif
|
||||
|
||||
/* Enable the IRQ by setting the corresponding REQENASET bit. */
|
||||
|
||||
regaddr = TMS570_VIM_REQENASET(regndx);
|
||||
regval = getreg32(regaddr);
|
||||
regaddr |= bitmask;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_fiq
|
||||
*
|
||||
* Description:
|
||||
* Enable the FIQ specified by 'channel'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARMV7R_HAVE_DECODEFIQ
|
||||
void up_enable_fiq(int channel)
|
||||
{
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t bitmask;
|
||||
unsigned int regndx;
|
||||
|
||||
DEBUGASSERT(channel >= 0 && channel < TMS570_IRQ_NCHANNELS)
|
||||
|
||||
/* Offset to account for the "phantom" vector */
|
||||
|
||||
channel++;
|
||||
regndx = VIM_REGNDX(channel);
|
||||
channel = VIM_REGBIT(channel);
|
||||
bitmask = (1 << channel);
|
||||
|
||||
/* Select FIQ (vs IRQ) by setting the corresponding FIRQPR bit */
|
||||
|
||||
regaddr = TMS570_VIM_FIRQPR(regndx);
|
||||
regval = getreg32(regaddr);
|
||||
regaddr &= ~bitmask;
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
/* Enable the FIQ by setting the corresponding REQENASET bit. */
|
||||
|
||||
regaddr = TMS570_VIM_REQENASET(regndx);
|
||||
regval = getreg32(regaddr);
|
||||
regaddr |= bitmask;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ack_irq
|
||||
*
|
||||
@ -159,7 +309,7 @@ void up_ack_irq(int irq)
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
int up_prioritize_irq(int irq, int priority)
|
||||
int up_prioritize_irq(int channel, int priority)
|
||||
{
|
||||
#warning Missing logic
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user