From 0968f6fec178b69be5b9f4a45ff7fb263bf8f388 Mon Sep 17 00:00:00 2001 From: patacongo Date: Sat, 26 Sep 2009 20:35:45 +0000 Subject: [PATCH] Add IRQ and SYSTICK logic git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2099 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/src/stm32/Make.defs | 4 +- arch/arm/src/stm32/stm32_dgbmcu.h | 8 +- arch/arm/src/stm32/stm32_internal.h | 6 + arch/arm/src/stm32/stm32_irq.c | 464 +++++++++++++++++++++++++++ arch/arm/src/stm32/stm32_memorymap.h | 5 + arch/arm/src/stm32/stm32_timerisr.c | 142 ++++++++ 6 files changed, 623 insertions(+), 6 deletions(-) create mode 100644 arch/arm/src/stm32/stm32_irq.c create mode 100644 arch/arm/src/stm32/stm32_timerisr.c diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 9662e1889e..1536d86191 100755 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -45,5 +45,5 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \ up_usestack.c up_doirq.c up_hardfault.c up_svcall.c CHIP_ASRCS = -CHIP_CSRCS = stm32_start.c stm32_lowputc.c stm32_serial.c -# stm32_irq.c stm32_gpio.c stm32_timerisr.c stm32_spi.c stm32_dumpgpio.c +CHIP_CSRCS = stm32_start.c stm32_irq.c stm32_timerisr.c stm32_lowputc.c stm32_serial.c +# stm32_gpio.c stm32_spi.c stm32_dumpgpio.c diff --git a/arch/arm/src/stm32/stm32_dgbmcu.h b/arch/arm/src/stm32/stm32_dgbmcu.h index 77657fcf00..7757452f20 100644 --- a/arch/arm/src/stm32/stm32_dgbmcu.h +++ b/arch/arm/src/stm32/stm32_dgbmcu.h @@ -70,10 +70,10 @@ #define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */ #define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignement */ #define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT) -# define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */ -# define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */ -# define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ -# define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ +# define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */ +# define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */ +# define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ +# define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ #define DBGMCU_CR_IWDGSTOP (1 << 8) /* Bit 8: Independent Watchdog stopped when core is halted */ #define DBGMCU_CR_WWDGSTOP (1 << 9) /* Bit 9: Window Watchdog stopped when core is halted */ #define DBGMCU_CR_TIM1STOP (1 << 10) /* Bit 10: TIM1 stopped when core is halted */ diff --git a/arch/arm/src/stm32/stm32_internal.h b/arch/arm/src/stm32/stm32_internal.h index 0df3b20dda..10e8da0d63 100755 --- a/arch/arm/src/stm32/stm32_internal.h +++ b/arch/arm/src/stm32/stm32_internal.h @@ -50,6 +50,12 @@ * Definitions ************************************************************************************/ +/* NVIC priority levels */ + +#define NVIC_SYSH_PRIORITY_MIN 0xff /* All bits set in minimum priority */ +#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */ +#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */ + /* Bit-encoded input to stm32_configgpio() *******************************************/ /* Encoding: diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c new file mode 100644 index 0000000000..75e160a50a --- /dev/null +++ b/arch/arm/src/stm32/stm32_irq.c @@ -0,0 +1,464 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_irq.c + * arch/arm/src/chip/stm32_irq.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include + +#include +#include +#include + +#include "nvic.h" +#include "up_arch.h" +#include "os_internal.h" +#include "up_internal.h" +#include "stm32_internal.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* Enable NVIC debug features that are probably only desireable during + * bringup + */ + +#undef LM2S_IRQ_DEBUG + +/* Get a 32-bit version of the default priority */ + +#define DEFPRIORITY32 \ + (NVIC_SYSH_PRIORITY_DEFAULT << 24 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 16 |\ + NVIC_SYSH_PRIORITY_DEFAULT << 8 |\ + NVIC_SYSH_PRIORITY_DEFAULT) + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +uint32 *current_regs; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_dumpnvic + * + * Description: + * Dump some interesting NVIC registers + * + ****************************************************************************/ + +#if defined(LM2S_IRQ_DEBUG) && defined (CONFIG_DEBUG) +static void stm32_dumpnvic(const char *msg, int irq) +{ + irqstate_t flags; + + flags = irqsave(); + slldbg("NVIC (%s, irq=%d):\n", msg, irq); + slldbg(" INTCTRL: %08x VECTAB: %08x\n", + getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB)); +#if 0 + slldbg(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x SYSTICK: %08x\n", + getreg32(NVIC_SYSHCON_MEMFAULTENA), getreg32(NVIC_SYSHCON_BUSFAULTENA), + getreg32(NVIC_SYSHCON_USGFAULTENA), getreg32(NVIC_SYSTICK_CTRL_ENABLE)); +#endif + slldbg(" IRQ ENABLE: %08x %08x\n", + getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE)); + slldbg(" SYSH_PRIO: %08x %08x %08x\n", + getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY), + getreg32(NVIC_SYSH12_15_PRIORITY)); + slldbg(" IRQ PRIO: %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY), + getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY), + getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY)); + slldbg(" %08x %08x %08x %08x\n", + getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY), + getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY)); + irqrestore(flags); +} +#else +# define stm32_dumpnvic(msg, irq) +#endif + +/**************************************************************************** + * Name: stm32_nmi, stm32_mpu, stm32_busfault, stm32_usagefault, stm32_pendsv, + * stm32_dbgmonitor, stm32_pendsv, stm32_reserved + * + * Description: + * Handlers for various execptions. None are handled and all are fatal + * error conditions. The only advantage these provided over the default + * unexpected interrupt handler is that they provide a diagnostic output. + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG +static int stm32_nmi(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! NMI received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int stm32_mpu(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! MPU interrupt received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int stm32_busfault(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Bus fault recived\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int stm32_usagefault(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Usage fault received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int stm32_pendsv(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! PendSV received\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int stm32_dbgmonitor(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Debug Monitor receieved\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} + +static int stm32_reserved(int irq, FAR void *context) +{ + (void)irqsave(); + dbg("PANIC!!! Reserved interrupt\n"); + PANIC(OSERR_UNEXPECTEDISR); + return 0; +} +#endif + +/**************************************************************************** + * Name: lml3s_irqinfo + * + * Description: + * Given an IRQ number, provide the register and bit setting to enable or + * disable the irq. + * + ****************************************************************************/ + +static int lml3s_irqinfo(int irq, uint32 *regaddr, uint32 *bit) +{ + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); + + /* Check for external interrupt */ + + if (irq >= STM32_IRQ_INTERRUPTS) + { + if (irq < STM32_IRQ_INTERRUPTS + 32) + { + *regaddr = NVIC_IRQ0_31_ENABLE; + *bit = 1 << (irq - STM32_IRQ_INTERRUPTS); + } + else if (irq < NR_IRQS) + { + *regaddr = NVIC_IRQ32_63_ENABLE; + *bit = 1 << (irq - STM32_IRQ_INTERRUPTS - 32); + } + else + { + return ERROR; /* Invalid interrupt */ + } + } + + /* Handler processor exceptions. Only a few can be disabled */ + + else + { + *regaddr = NVIC_SYSHCON; + if (irq == STM32_IRQ_MPU) + { + *bit = NVIC_SYSHCON_MEMFAULTENA; + } + else if (irq == STM32_IRQ_BUSFAULT) + { + *bit = NVIC_SYSHCON_BUSFAULTENA; + } + else if (irq == STM32_IRQ_USAGEFAULT) + { + *bit = NVIC_SYSHCON_USGFAULTENA; + } + else if (irq == STM32_IRQ_SYSTICK) + { + *regaddr = NVIC_SYSTICK_CTRL; + *bit = NVIC_SYSTICK_CTRL_ENABLE; + } + else + { + return ERROR; /* Invalid or unsupported exception */ + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Disable all interrupts */ + + putreg32(0, NVIC_IRQ0_31_ENABLE); + putreg32(0, NVIC_IRQ32_63_ENABLE); + + /* Set all interrrupts (and exceptions) to the default priority */ + + putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY); + + putreg32(DEFPRIORITY32, NVIC_IRQ0_3_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ4_7_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ8_11_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ12_15_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ16_19_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ20_23_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ24_27_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ28_31_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ32_35_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ36_39_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ40_43_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ44_47_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ48_51_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ52_55_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ56_59_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ60_63_PRIORITY); + putreg32(DEFPRIORITY32, NVIC_IRQ64_67_PRIORITY); + + /* currents_regs is non-NULL only while processing an interrupt */ + + current_regs = NULL; + + /* Initialize support for GPIO interrupts if included in this build */ + +#ifndef CONFIG_STM32_DISABLE_GPIO_IRQS +#ifdef CONFIG_HAVE_WEAKFUNCTIONS + if (gpio_irqinitialize != NULL) +#endif + { + gpio_irqinitialize(); + } +#endif + + /* Attach the SVCall and Hard Fault exception handlers. The SVCall + * exception is used for performing context switches; The Hard Fault + * must also be caught because a SVCall may show up as a Hard Fault + * under certain conditions. + */ + + irq_attach(STM32_IRQ_SVCALL, up_svcall); + irq_attach(STM32_IRQ_HARDFAULT, up_hardfault); + + /* Set the priority of the SVCall interrupt */ + +#ifdef CONFIG_ARCH_IRQPRIO +/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */ +#endif + + /* Attach all other processor exceptions (except reset and sys tick) */ + +#ifdef CONFIG_DEBUG + irq_attach(STM32_IRQ_NMI, stm32_nmi); + irq_attach(STM32_IRQ_MPU, stm32_mpu); + irq_attach(STM32_IRQ_BUSFAULT, stm32_busfault); + irq_attach(STM32_IRQ_USAGEFAULT, stm32_usagefault); + irq_attach(STM32_IRQ_PENDSV, stm32_pendsv); + irq_attach(STM32_IRQ_DBGMONITOR, stm32_dbgmonitor); + irq_attach(STM32_IRQ_RESERVED, stm32_reserved); +#endif + + stm32_dumpnvic("inital", NR_IRQS); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + + /* Initialize FIQs */ + +#ifdef CONFIG_ARCH_FIQ + up_fiqinitialize(); +#endif + + /* And finally, enable interrupts */ + + setbasepri(NVIC_SYSH_PRIORITY_MAX); + irqrestore(0); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + uint32 regaddr; + uint32 regval; + uint32 bit; + + if (lml3s_irqinfo(irq, ®addr, &bit) == 0) + { + /* Clear the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval &= ~bit; + putreg32(regval, regaddr); + } + stm32_dumpnvic("disable", irq); +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + uint32 regaddr; + uint32 regval; + uint32 bit; + + if (lml3s_irqinfo(irq, ®addr, &bit) == 0) + { + /* Set the appropriate bit in the register to enable the interrupt */ + + regval = getreg32(regaddr); + regval |= bit; + putreg32(regval, regaddr); + } + stm32_dumpnvic("enable", irq); +} + +/**************************************************************************** + * Name: up_maskack_irq + * + * Description: + * Mask the IRQ and acknowledge it + * + ****************************************************************************/ + +void up_maskack_irq(int irq) +{ + up_disable_irq(irq); +} + +/**************************************************************************** + * Name: up_prioritize_irq + * + * Description: + * Set the priority of an IRQ. + * + * Since this API is not supported on all architectures, it should be + * avoided in common implementations where possible. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQPRIO +int up_prioritize_irq(int irq, int priority) +{ + uint32 regaddr; + uint32 regval; + int shift; + + DEBUGASSERT(irq >= STM32_IRQ_MPU && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); + + if (irq < STM32_IRQ_INTERRUPTS) + { + irq -= 4; + regaddr = NVIC_SYSH_PRIORITY(irq); + } + else + { + irq -= STM32_IRQ_INTERRUPTS; + regaddr = NVIC_IRQ_PRIORITY(irq); + } + + regval = getreg32(regaddr); + shift = ((irq & 3) << 3); + regval &= ~(0xff << shift); + regval |= (priority << shift); + putreg32(regval, regaddr); + + stm32_dumpnvic("prioritize", irq); + return OK; +} +#endif diff --git a/arch/arm/src/stm32/stm32_memorymap.h b/arch/arm/src/stm32/stm32_memorymap.h index 3aaca34977..0f271e44e0 100755 --- a/arch/arm/src/stm32/stm32_memorymap.h +++ b/arch/arm/src/stm32/stm32_memorymap.h @@ -122,6 +122,11 @@ /* 0x40023400 - 0x40027fff: Reserved */ #define STM32_ETHERNET_BASE 0x40028000 /* 0x40028000 - 0x40029fff: Ethernet */ /* 0x40030000 - 0x4fffffff: Reserved */ + +/* Other registers */ + +#define STM32_NVIC_BASE 0xe000e000 /* 0xe000e00-0xe000efff: Nested Vectored Interrupt Controller */ +#define STM32_DEBUGMCU_BASE 0xe0042000 /************************************************************************************ * Public Types diff --git a/arch/arm/src/stm32/stm32_timerisr.c b/arch/arm/src/stm32/stm32_timerisr.c new file mode 100644 index 0000000000..d254483910 --- /dev/null +++ b/arch/arm/src/stm32/stm32_timerisr.c @@ -0,0 +1,142 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_timerisr.c + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include + +#include "nvic.h" +#include "clock_internal.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "chip.h" +#include "stm32_internal.h" + +/**************************************************************************** + * Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * The timer counts at the rate SYSCLK_FREQUENCY as defined in the board.h + * header file. + */ + +#define SYSTICK_RELOAD ((SYSCLK_FREQUENCY / CLK_TCK) - 1) + +/* The size of the reload field is 24 bits. Verify taht the reload value + * will fit in the reload register. + */ + +#if SYSTICK_RELOAD > 0x00ffffff +# error SYSTICK_RELOAD exceeds the range of the RELOAD register +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Global Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: up_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +int up_timerisr(int irq, uint32 *regs) +{ + /* Process timer interrupt */ + + sched_process_timer(); + return 0; +} + +/**************************************************************************** + * Function: up_timerinit + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timerinit(void) +{ + uint32 regval; + + /* Set the SysTick interrupt to the default priority */ + + regval = getreg32(NVIC_SYSH12_15_PRIORITY); + regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK; + regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT); + putreg32(regval, NVIC_SYSH12_15_PRIORITY); + + /* Configure SysTick to interrupt at the requested rate */ + + putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)up_timerisr); + + /* Enable SysTick interrupts */ + + putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL); + + /* And enable the timer interrupt */ + + up_enable_irq(STM32_IRQ_SYSTICK); +}