Basic page allocation logic
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2874 42af7a65-404d-4744-a932-0658087f49c3
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@ -8,7 +8,7 @@
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<tr align="center" bgcolor="#e4e4e4">
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<td>
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<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
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<p>Last Updated: August 18, 2010</p>
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<p>Last Updated: August 21, 2010</p>
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</td>
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</tr>
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</table>
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@ -1008,6 +1008,7 @@
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This port uses the
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<a href="http://wiki.neurostechnology.com/index.php/Developer_Welcome">Neuros OSD</a>
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with a GNU arm-elf toolchain* under Linux or Cygwin.
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The port was performed using the OSD v1.0, development board.
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</p>
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<ul>
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<p>
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@ -164,7 +164,7 @@ struct xcptcontext
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*/
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#ifdef CONFIG_PAGING
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uint32_t far;
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uintptr_t far;
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#endif
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};
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#endif
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@ -282,6 +282,124 @@
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#ifndef __ASSEMBLY__
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/* ARMv4/ARMv5 operation: Invalidate TLB
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* ARM926EJ-S operation: Invalidate set-associative
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* Data: Should be zero
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*/
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static inline void tlb_invalidate(void)
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{
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unsigned int sbz = 0;
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__asm__ __volatile__
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(
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"\tmcr p15, 0, %0, c8, c7, 0"
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:
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: "r" (sbz)
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: "memory");
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}
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/* ARMv4/ARMv5 operation: Invalidate TLB single entry (MVA)
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* ARM926EJ-S operation: Invalidate single entry
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* Data: MVA
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*/
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static inline void tlb_invalidate_single(unsigned int mva)
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{
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mva &= 0xfffffc00;
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__asm__ __volatile__
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(
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"mcr p15, 0, %0, c8, c7, 1"
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:
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: "r" (mva)
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: "memory");
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}
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/* ARMv4/ARMv5 operation: Invalidate instruction TLB
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* ARM926EJ-S operation: Invalidate set-associative TLB
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* Data: Should be zero
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*/
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static inline void tlb_instr_invalidate(void)
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{
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unsigned int sbz = 0;
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__asm__ __volatile__
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(
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"\tmcr p15, 0, %0, c8, c5, 0"
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:
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: "r" (sbz)
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: "memory");
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}
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/* ARMv4/ARMv5 operation: Invalidate instruction TLB single entry (MVA)
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* ARM926EJ-S operation: Invalidate single entry
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* Data: MVA
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*/
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static inline void tlb_inst_invalidate_single(unsigned int mva)
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{
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mva &= 0xfffffc00;
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__asm__ __volatile__
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(
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"mcr p15, 0, %0, c8, c5, 1"
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:
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: "r" (mva)
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: "memory");
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}
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/* ARMv4/ARMv5 operation: Invalidate data TLB
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* ARM926EJ-S operation: Invalidate set-associative TLB
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* Data: Should be zero
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*/
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static inline void tlb_data_invalidate(void)
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{
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unsigned int sbz = 0;
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__asm__ __volatile__
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(
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"\tmcr p15, 0, %0, c8, c6, 0"
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:
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: "r" (sbz)
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: "memory");
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}
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/* ARMv4/ARMv5 operation: Invalidate data TLB single entry (MVA)
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* ARM926EJ-S operation: Invalidate single entry
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* Data: MVA
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*/
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static inline void tlb_data_invalidate_single(unsigned int mva)
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{
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mva &= 0xfffffc00;
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__asm__ __volatile__
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(
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"mcr p15, 0, %0, c8, c6, 1"
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:
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: "r" (mva)
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: "memory");
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}
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#endif /* __ASSEMBLY__ */
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/****************************************************************************
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* Public Variables
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_COMMON_ARM_H */
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@ -52,69 +52,94 @@
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/* Configuration ************************************************************/
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#ifdef CONFIG_PAGING
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/* Sanity check -- we cannot be using a ROM page table and supporting on-
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* demand paging.
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*/
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# ifdef CONFIG_ARCH_ROMPGTABLE
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# error "Cannot support both CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE"
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# endif
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/* Page Size Selections ***************************************************/
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/* Sanity check -- we cannot be using a ROM page table and supporting on-
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* demand paging.
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*/
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/* Create some friendly definitions to handle some differences between
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* small and tiny pages.
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*/
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#ifdef CONFIG_ARCH_ROMPGTABLE
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# error "Cannot support both CONFIG_PAGING and CONFIG_ARCH_ROMPGTABLE"
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#endif
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# if CONFIG_PAGING_PAGESIZE == 1024
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/* Page Size Selections *****************************************************/
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/* Number of pages in an L2 table per L1 entry */
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/* Create some friendly definitions to handle some differences between
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* small and tiny pages.
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*/
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# define PTE_NPAGES PTE_TINY_NPAGES
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#if CONFIG_PAGING_PAGESIZE == 1024
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/* L2 Page table address */
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/* Number of pages in an L2 table per L1 entry */
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# define PG_L2_BASE_PADDR PGTABLE_FINE_BASE_PADDR
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# define PG_L2_BASE_VADDR PGTABLE_FINE_BASE_VADDR
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# define PTE_NPAGES PTE_TINY_NPAGES
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/* MMU Flags for each memory region */
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/* L2 Page table address */
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW)
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# define PG_L2_BASE_PADDR PGTABLE_FINE_BASE_PADDR
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# define PG_L2_BASE_VADDR PGTABLE_FINE_BASE_VADDR
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# elif CONFIG_PAGING_PAGESIZE == 4096
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/* MMU Flags for each memory region */
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/* Number of pages in an L2 table per L1 entry */
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_FINE|PMD_BIT4)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_TINY|PTE_EXT_AP_UNO_SRW)
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# define PTE_NPAGES PTE_SMALL_NPAGES
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#elif CONFIG_PAGING_PAGESIZE == 4096
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/* L2 Page table address */
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/* Number of pages in an L2 table per L1 entry */
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# define PG_L2_BASE_PADDR PGTABLE_COARSE_BASE_PADDR
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# define PG_L2_BASE_VADDR PGTABLE_COARSE_BASE_VADDR
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# define PTE_NPAGES PTE_SMALL_NPAGES
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/* MMU Flags for each memory region. */
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/* L2 Page table address */
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
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# define PG_L2_BASE_PADDR PGTABLE_COARSE_BASE_PADDR
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# define PG_L2_BASE_VADDR PGTABLE_COARSE_BASE_VADDR
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# else
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# error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
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# endif
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/* MMU Flags for each memory region. */
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#define PT_SIZE (PTE_NPAGES * 4)
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# define MMU_L1_TEXTFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_TEXTFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRO|PTE_CACHEABLE)
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# define MMU_L1_DATAFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_DATAFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW|PTE_CACHEABLE|PTE_BUFFERABLE)
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# define MMU_L1_PGTABFLAGS (PMD_TYPE_COARSE|PMD_BIT4)
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# define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL|PTE_SMALL_AP_UNO_SRW)
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/* We position the data section PTEs just after the text section PTE's */
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#else
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# error "Need extended definitions for CONFIG_PAGING_PAGESIZE"
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#endif
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#define PG_L2_DATA_PADDR (PG_L2_BASE_PADDR + 4*PG_TEXT_NPAGES)
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#define PG_L2_DATA_VADDR (PG_L2_BASE_VADDR + 4*PG_TEXT_NPAGES)
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#define PT_SIZE (4*PTE_NPAGES)
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/* We position the locked region PTEs at the beginning of L2 page
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* table.
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*/
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#define PG_L2_LOCKED_PADDR PG_L2_BASE_PADDR
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#define PG_L2_LOCKED_VADDR PG_L2_BASE_VADDR
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#define PG_L2_LOCKED_SIZE (4*CONFIG_PAGING_NLOCKED)
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/* We position the paged region PTEs immediately after the locked
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* region PTEs.
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*/
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#define PG_L2_PAGED_PADDR (PG_L2_BASE_PADDR + PG_L2_LOCKED_SIZE)
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#define PG_L2_PAGED_VADDR (PG_L2_BASE_VADDR + PG_L2_LOCKED_SIZE)
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#define PG_L2_PAGED_SIZE (4*CONFIG_PAGING_NPAGED)
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/* This describes the overall text region */
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#define PG_L2_TEXT_PADDR PG_L2_LOCKED_PADDR
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#define PG_L2_TEXT_VADDR PG_L2_LOCKED_VADDR
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#define PG_L2_TEXT_SIZE (PG_L2_LOCKED_SIZE + PG_L2_PAGED_SIZE)
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/* We position the data section PTEs just after the text region PTE's */
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#define PG_L2_DATA_PADDR (PG_L2_BASE_PADDR + PG_L2_TEXT_SIZE)
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#define PG_L2_DATA_VADDR (PG_L2_BASE_VADDR + PG_L2_TEXT_SIZE)
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#define PG_L2_DATA_SIZE (4*PG_DATA_NPAGES)
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/* Page Table Info: The number of pages in the in the page table
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* (PG_PGTABLE_NPAGES). We position the pagetable PTEs just after
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@ -122,21 +147,139 @@
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*/
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#define PG_PGTABLE_NPAGES (PGTABLE_SIZE >> PAGESHIFT)
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#define PG_L2_PGTABLE_PADDR (PG_L2_DATA_PADDR + 4*PG_DATA_NPAGES)
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#define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + 4*PG_DATA_NPAGES)
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#define PG_L2_PGTABLE_PADDR (PG_L2_DATA_PADDR + PG_L2_DATA_SIZE)
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#define PG_L2_PGTABLE_VADDR (PG_L2_DATA_VADDR + PG_L2_DATA_SIZE)
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#define PG_L2_PGTABLE_SIZE (4*PG_DATA_NPAGES)
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/* This is the total number of pages used in the initial page table setup
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* in up_head.S
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/* Vector mapping. One page is required to map the vector table. The
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* vector table could lie in at virtual address zero (or at the start
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* of RAM which is aliased to address zero on the ea3131) or at virtual
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* address 0xfff00000. We only have logic here to support the former
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* case.
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*
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* NOTE: If the vectors are at address zero, the page table will be
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* forced to the highest RAM addresses. If the vectors are at 0xfff0000,
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* then the page table is forced to the beginning of RAM.
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*
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* When the vectors are at the beginning of RAM, they will probably overlap
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* the first page of the locked text region. In any other case, the
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* configuration must set CONFIG_PAGING_VECPPAGE to provide the physical
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* address of the page to use for the vectors.
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*
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* When the vectors overlap the first page of the locked text region (the
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* only case in use so far), then the text page will be temporarily be made
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* writable in order to copy the vectors.
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*
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* PG_VECT_PBASE - This the physical address of the page in memory to be
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* mapped to the vector address.
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* PG_L2_VECT_PADDR - This is the physical address of the L2 page table
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* entry to use for the vector mapping.
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* PG_L2_VECT_VADDR - This is the virtual address of the L2 page table
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* entry to use for the vector mapping.
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*/
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#define PG_STATIC_NPAGES (PG_TEXT_NPAGES + PG_DATA_PAGES + PG_PGTABLE_NPAGES)
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/* Case 1: The configuration tells us everything */
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#if defined(CONFIG_PAGING_VECPPAGE)
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# define PG_VECT_PBASE CONFIG_PAGING_VECPPAGE
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# define PG_L2_VECT_PADDR CONFIG_PAGING_VECL2PADDR
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# define PG_L2_VECT_VADDR CONFIG_PAGING_VECL2VADDR
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/* Case 2: Vectors are in low memory and the locked text region starts at
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* the begin of SRAM (which will be aliased to address 0x00000000)
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*/
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#elif defined(CONFIG_ARCH_LOWVECTORS) && !defined(CONFIG_PAGING_LOCKED_PBASE)
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# define PG_VECT_PBASE PG_LOCKED_PBASE
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# define PG_L2_VECT_PADDR PG_L2_LOCKED_PADDR
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# define PG_L2_VECT_VADDR PG_L2_LOCKED_VADDR
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/* Case 3: High vectors or the locked region is not at the beginning or SRAM */
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#else
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# error "Logic missing for high vectors in this case"
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#endif
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/* This is the total number of pages used in the text/data mapping: */
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#define PG_TOTAL_NPAGES (PG_TEXT_NPAGES + PG_DATA_PAGES + PG_PGTABLE_NPAGES)
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#if PG_TOTAL_NPAGES >PG_RAM_PAGES
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# error "Total pages required exceeds RAM size"
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#endif
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/* For page managment purposes, the following summarize the "heap" of
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* free pages
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* free pages, operations on free pages and the L2 page table.
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*
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* PG_POOL_L2NDX(va) - Converts a virtual address in the paged SRAM
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* region into a index into the paged region of
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* the L2 page table.
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* PG_POOL_L2OFFSET(va) - Converts a virtual address in the paged SRAM
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* region into a byte offset into the paged
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* region of the L2 page table.
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* PG_POOL_L2VADDR(va) - Converts a virtual address in the paged SRAM
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* region into the virtual address of the
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* corresponding PTE entry.
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*
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* PG_POOL_L1VBASE - The virtual address of the start of the L1
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* page table range corresponding to the first
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* virtual address of the paged text region.
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* PG_POOL_L1VEND - The virtual address of the end+1 of the L1
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* page table range corresponding to the last
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* virtual address+1 of the paged text region.
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*
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* PG_POOL_VA2L2NDX(va) - Converts a virtual address within the paged
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* text region to the most compact possible
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* representation. Each PAGESIZE of address
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* corresponds to 1 index in the L2 page table;
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* Index 0 corresponds to the first L2 page table
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* entry for the first page in the virtual paged
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* text address space.
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* PG_POOL_NDX2VA(ndx) - Performs the opposite conversion.. convests
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* an index into a virtual address in the paged
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* text region (the address at the beginning of
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* the page).
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* PG_POOL_MAXL2NDX - This is the maximum value+1 of such an index.
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* PG_POOL_NDX2L2VADDR(ndx) - Converts an index to the corresponding address
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* in the L1 page table entry.
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* PG_POOL_VA2L2VADDR(va) - Converts a virtual address within the paged
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* text region to the corresponding address in
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* the L2 page table entry.
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*
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* PG_POOL_PGPADDR(ndx) - Converts an index into the corresponding
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* (physical) address of the backing page memory.
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* PG_POOL_PGVADDR(ndx) - Converts an index into the corresponding
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* (virtual)address of the backing page memory.
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*
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* PG_POOL_VIRT2PHYS(va) - Convert a virtual address within the paged
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* text region into a physical address.
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* PG_POOL_PHYS2VIRT(va) - Convert a physical address within the paged
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* text region into a virtual address.
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*
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* These are used as follows: If a miss occurs at some virtual address, va,
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* A new page index, ndx, is allocated. PG_POOL_PGPADDR(i) converts the index
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* into the physical address of the page memory; PG_POOL_L2VADDR(va) converts
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* the virtual address in the L2 page table there the new mapping will be
|
||||
* written.
|
||||
*/
|
||||
|
||||
#define PG_POOL_FIRSTPAGE PG_STATIC_NPAGES
|
||||
#define PG_POOL_NPAGES CONFIG_PAGING_NLOCKED
|
||||
#define PG_POOL_L2NDX(va) ((va) - PG_PAGED_VBASE) >> PAGESHIFT)
|
||||
#define PG_POOL_L2OFFSET(va) (PG_POOL_L2NDX(va) << 2)
|
||||
#define PG_POOL_L2VADDR(va) (PG_L2_PAGED_VADDR + PG_POOL_L2OFFSET(va))
|
||||
|
||||
#define PG_POOL_L1VBASE (PGTABLE_BASE_VADDR + ((PG_PAGED_VBASE >> 20) << 2))
|
||||
#define PG_POOL_L1VEND (PG_POOL_L1VBASE + (CONFIG_PAGING_NPAGED << 2))
|
||||
|
||||
#define PG_POOL_VA2L2NDX(va) (((va) - PG_PAGED_VBASE) >> PAGESHIFT)
|
||||
#define PG_POOL_NDX2VA(ndx) (((ndx) << PAGESHIFT) + PG_PAGED_VBASE)
|
||||
#define PG_POOL_MAXL2NDX PG_POOL_VA2L2NDX(PG_PAGED_VEND)
|
||||
#define PG_POOL_NDX2L2VADDR(ndx) (PG_L2_PAGED_VADDR + ((ndx) << 2))
|
||||
#define PG_POOL_VA2L2VADDR(va) PG_POOL_NDX2L2VADDR(PG_POOL_VA2L2NDX(va))
|
||||
|
||||
#define PG_POOL_PGPADDR(ndx) (PG_PAGED_PBASE + ((ndx) << PAGESHIFT))
|
||||
#define PG_POOL_PGVADDR(ndx) (PG_PAGED_VBASE + ((ndx) << PAGESHIFT))
|
||||
|
||||
#define PG_POOL_VIRT2PHYS(va) ((va) + (PG_PAGED_PBASE - PG_PAGED_VBASE))
|
||||
#define PG_POOL_PHYS2VIRT(pa) ((pa) + (PG_PAGED_VBASE - PG_PAGED_PBASE))
|
||||
|
||||
#endif /* CONFIG_PAGING */
|
||||
|
||||
@ -144,7 +287,7 @@
|
||||
* Assembly Macros
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __ASSEMBLY
|
||||
#ifdef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pg_map
|
||||
@ -209,6 +352,7 @@
|
||||
cmp \npages, #0
|
||||
bgt 1b
|
||||
.endm
|
||||
#endif /* CONFIG_PAGING */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pg_span
|
||||
@ -291,13 +435,13 @@
|
||||
.endm
|
||||
|
||||
#endif /* CONFIG_PAGING */
|
||||
#endif /* __ASSEMBLY */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#endif /* __ASSEMBLY */
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_ARM_PG_MACROS_H */
|
||||
|
||||
@ -40,22 +40,72 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/sched.h>
|
||||
#include <nuttx/page.h>
|
||||
|
||||
#ifdef CONFIG_PAGING
|
||||
|
||||
#include <nuttx/page.h>
|
||||
#include "pg_macros.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
#if CONFIG_PAGING_NPAGED < 256
|
||||
typedef uint8_t pgndx_t;
|
||||
#elif CONFIG_PAGING_NPAGED < 65536
|
||||
typedef uint16_t pgndx_t;
|
||||
#else
|
||||
typedef uint32_t pgndx_t;
|
||||
#endif
|
||||
|
||||
#if PG_POOL_MAXL1NDX < 256
|
||||
typedef uint8_t L1ndx_t;
|
||||
#elif PG_POOL_MAXL1NDX < 65536
|
||||
typedef uint16_t L1ndx_t;
|
||||
#else
|
||||
typedef uint32_t L1ndx_t;
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* Free pages in memory are managed by indices ranging from up to
|
||||
* CONFIG_PAGING_NPAGED. Initially all pages are free so the page can be
|
||||
* simply allocated in order: 0, 1, 2, ... . After all CONFIG_PAGING_NPAGED
|
||||
* pages have be filled, then they are blindly freed and re-used in the
|
||||
* same order 0, 1, 2, ... because we don't know any better. No smart "least
|
||||
* recently used" kind of logic is supported.
|
||||
*/
|
||||
|
||||
static pgndx_t g_pgndx;
|
||||
|
||||
/* After CONFIG_PAGING_NPAGED have been allocated, the pages will be re-used.
|
||||
* In order to re-used the page, we will have un-map the page from its previous
|
||||
* mapping. In order to that, we need to be able to map a physical address to
|
||||
* to an index into the PTE where it was mapped. The following table supports
|
||||
* this backward lookup - it is indexed by the page number index, and holds
|
||||
* another index to the mapped virtual page.
|
||||
*/
|
||||
|
||||
static L1ndx_t g_ptemap[CONFIG_PAGING_NPAGED];
|
||||
|
||||
/* The contents of g_ptemap[] are not valid until g_pgndx has wrapped at
|
||||
* least one time.
|
||||
*/
|
||||
|
||||
static bool g_pgwrap;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
@ -108,8 +158,74 @@
|
||||
|
||||
int up_allocpage(FAR _TCB *tcb, FAR void **vpage)
|
||||
{
|
||||
# warning "Not implemented"
|
||||
return -ENOSYS;
|
||||
uintptr_t vaddr;
|
||||
uintptr_t paddr;
|
||||
uint32_t *pte;
|
||||
unsigned int pgndx;
|
||||
unsigned int l2ndx;
|
||||
|
||||
/* Since interrupts are disabled, we don't need to anything special. */
|
||||
|
||||
DEBUGASSERT(tcb && vpage);
|
||||
|
||||
/* Get the virtual address that caused the fault */
|
||||
|
||||
vaddr = tcb->xcp.far;
|
||||
DEBUGASSERT(vaddr >= PG_PAGED_VBASE && vaddr < PG_PAGED_VEND);
|
||||
|
||||
/* Verify that this virtual address was previously unmapped */
|
||||
|
||||
#if CONFIG_DEBUG
|
||||
pte = (uint32_t*)PG_POOL_L2VADDR(vaddr);
|
||||
DEBUGASSERT(*pte == 0);
|
||||
#endif
|
||||
|
||||
/* Allocate page memory to back up the mapping. Start by getting the
|
||||
* index of the next page that we are going to allocate.
|
||||
*/
|
||||
|
||||
pgndx = g_pgndx++;
|
||||
if (p_pgndx >= CONFIG_PAGING)
|
||||
{
|
||||
g_pgndx = 0;
|
||||
g_pgwrap = true;
|
||||
}
|
||||
|
||||
/* Then convert the index to a (physical) page address. */
|
||||
|
||||
paddr = PG_POOL_PGPADDR(pgndx);
|
||||
|
||||
/* Was this physical page previously mapped? If so, then we need to un-map
|
||||
* it.
|
||||
*/
|
||||
|
||||
if (g_pgwrap)
|
||||
{
|
||||
/* Yes.. Get a pointer to the L2 entry corresponding to the previous
|
||||
* mapping -- then zero it!
|
||||
*/
|
||||
|
||||
l2ndx = g_ptemap[pgndx];
|
||||
pte = (uint32_t*)PG_POOL_NDX2L2VADDR(l2ndx);
|
||||
*pte = 0;
|
||||
|
||||
/* Invalidate the TLB corresponding to the virtual address */
|
||||
|
||||
tlb_inst_invalidate_single(PG_POOL_NDX2VA(l2ndx))
|
||||
}
|
||||
|
||||
/* Now setup up the new mapping. Get a pointer to the L2 entry
|
||||
* corresponding to the new mapping. Then set it map to the newly
|
||||
* allocated page address.
|
||||
*/
|
||||
|
||||
pte = (uint32_t*)PG_POOL_VA2L2VADDR(va)
|
||||
*pte = (paddr | MMU_L2_TEXTFLAGS);
|
||||
|
||||
/* Finally, return the virtual address of allocated page */
|
||||
|
||||
*vpage = (void*)PG_POOL_PHYS2VIRT(paddr);
|
||||
return OK;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PAGING */
|
||||
|
||||
@ -350,13 +350,13 @@ __start:
|
||||
|
||||
#ifdef CONFIG_PAGING
|
||||
.Ltxtspan:
|
||||
.long PG_L2_BASE_PADDR /* Physical address of L2 table */
|
||||
.long PG_LOCKED_VBASE /* Virtual address of locked base */
|
||||
.long PG_L2_TEXT_PADDR /* Physical address of L2 table */
|
||||
.long PG_TEXT_VBASE /* Virtual address of text base */
|
||||
.long PG_TEXT_NPAGES /* Total mapped text pages */
|
||||
.long MMU_L1_TEXTFLAGS /* L1 MMU flags to use */
|
||||
|
||||
.Ltxtmap:
|
||||
.long PG_L2_BASE_PADDR /* Physical address of L2 table */
|
||||
.long PG_L2_LOCKED_PADDR /* Physical address of L2 table */
|
||||
.long PG_LOCKED_PBASE /* Physical address of locked base */
|
||||
.long CONFIG_PAGING_NLOCKED /* Number of pages in the locked region */
|
||||
.long MMU_L2_TEXTFLAGS /* L2 MMU flags to use */
|
||||
|
||||
@ -79,14 +79,18 @@
|
||||
* initialization
|
||||
*
|
||||
* Assumptions:
|
||||
* - Called early in the platform initializatin sequence so that no special
|
||||
* - Called early in the platform initialization sequence so that no special
|
||||
* concurrency protection is required.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_pginitialize(void)
|
||||
{
|
||||
# warning "Not implemented"
|
||||
/* None needed at present. This file is just retained in case the need
|
||||
* arises in the future. Nothing calls up_pginitialize() now. If needed,
|
||||
* if should be called early in up_boot.c to assure that all paging is
|
||||
* ready.
|
||||
*/
|
||||
}
|
||||
|
||||
#endif /* CONFIG_PAGING */
|
||||
|
||||
@ -123,8 +123,8 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_PAGING_LOCKED_PBASE) && defined(CONFIG_PAGING_LOCKED_VBASE)
|
||||
# define PG_LOCKED_PBASE CONFIG_PAGING_LOCKED_PBASE
|
||||
# define PG_LOCKED_VBASE CONFIG_PAGING_LOCKED_VBASE
|
||||
# define PG_PAGED_PBASE CONFIG_PAGING_LOCKED_PBASE
|
||||
# define PG_PAGED_VBASE CONFIG_PAGING_LOCKED_VBASE
|
||||
#else
|
||||
# define PG_PAGED_PBASE PG_LOCKED_PEND
|
||||
# define PG_PAGED_VBASE PG_LOCKED_VEND
|
||||
@ -133,10 +133,16 @@
|
||||
#define PG_PAGED_PEND (PG_PAGED_PBASE + PG_PAGED_SIZE)
|
||||
#define PG_PAGED_VEND (PG_PAGED_VBASE + PG_PAGED_SIZE)
|
||||
|
||||
/* Size of the overall text section */
|
||||
/* Size and description of the overall text section. The number of
|
||||
* pages in the text section is the sum of the number of pages in
|
||||
* both the locked and paged regions. The base of the text section
|
||||
* is the base of the locked region.
|
||||
*/
|
||||
|
||||
#define PG_TEXT_NPAGES (CONFIG_PAGING_NLOCKED + CONFIG_PAGING_NPAGED)
|
||||
#define PG_TEXT_SIZE (PG_TEXT_NPAGES << PAGESHIFT)
|
||||
#define PG_TEXT_PBASE PG_LOCKED_PBASE
|
||||
#define PG_TEXT_VBASE PG_LOCKED_VBASE
|
||||
|
||||
/* CONFIG_PAGING_NDATA - This is the number of data pages in the memory
|
||||
* map. The data region will extend to the end of RAM unless overridden
|
||||
|
||||
Loading…
Reference in New Issue
Block a user