From 09f3e9ce5c42ffbd4e3a86f75cf46f8361b5ff92 Mon Sep 17 00:00:00 2001 From: Mateusz Szafoni Date: Thu, 19 Oct 2017 20:07:04 +0000 Subject: [PATCH] Merged in raiden00/nuttx (pull request #513) Master * stm32f33xxx_adc.c: fix some warnings and compilation error when extsel not in use * nucleo-f334r8/adc: change serial console to USART2 (STLINK COM) Approved-by: Gregory Nutt --- arch/arm/src/stm32/stm32f33xxx_adc.c | 97 +++++++++++++++++++++------- configs/nucleo-f334r8/adc/defconfig | 4 +- 2 files changed, 75 insertions(+), 26 deletions(-) diff --git a/arch/arm/src/stm32/stm32f33xxx_adc.c b/arch/arm/src/stm32/stm32f33xxx_adc.c index 10bfccc527..a240de4799 100644 --- a/arch/arm/src/stm32/stm32f33xxx_adc.c +++ b/arch/arm/src/stm32/stm32f33xxx_adc.c @@ -315,6 +315,30 @@ (ADC2_SMP17 << ADC_SMPR2_SMP17_SHIFT) | \ (ADC2_SMP18 << ADC_SMPR2_SMP18_SHIFT)) +/* Last bit of the extsel fields indicate if external trigger is in use */ + +#define HAVE_EXTSEL_MASK (1<<8) + +#if defined(ADC1_HAVE_TIMER) || defined(ADC1_HAVE_HRTIM) || defined(ADC1_HAVE_EXTI) +# define ADC1_HAVE_EXTSEL 1 +#else +# undef ADC1_HAVE_EXTSEL +#endif + +#if defined(ADC2_HAVE_TIMER) || defined(ADC2_HAVE_HRTIM) || defined(ADC2_HAVE_EXTI) +# define ADC2_HAVE_EXTSEL 1 +#else +# undef ADC2_HAVE_EXTSEL +#endif + +#if defined(ADC1_HAVE_EXTSEL) || defined(ADC2_HAVE_EXTSEL) +# define ADC_HAVE_EXTSEL +#endif + +#if defined(ADC1_HAVE_JEXTSEL) || defined(ADC2_HAVE_JEXTSEL) +# define ADC_HAVE_JEXTSEL +#endif + /**************************************************************************** * Private Types ****************************************************************************/ @@ -324,7 +348,7 @@ struct stm32_dev_s { FAR const struct adc_callback_s *cb; -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ uint8_t irq; /* Interrupt generated by this ADC block */ #endif uint8_t nchannels; /* Number of channels */ @@ -340,15 +364,19 @@ struct stm32_dev_s uint8_t trigger; /* Timer trigger channel: 0=CC1, 1=CC2, 2=CC3, * 3=CC4, 4=TRGO */ #endif -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ xcpt_t isr; /* Interrupt handler for this ADC block */ #endif uint32_t base; /* Base address of registers unique to this ADC * block */ - uint32_t smp1; /* Sample time part 1 */ - uint32_t smp2; /* Sample time part 2 */ + uint32_t smp1; /* Sample time part 1 */ + uint32_t smp2; /* Sample time part 2 */ +#ifdef ADC_HAVE_EXTSEL uint32_t extsel; /* EXTSEL value used by this ADC block */ +#endif +#ifdef ADC_HAVE_JEXTSEL uint32_t jextsel; /* JEXTSEL value used by this ADC block */ +#endif #ifdef ADC_HAVE_TIMER uint32_t tbase; /* Base address of timer used by this ADC block */ uint32_t pclck; /* The PCLK frequency that drives this timer */ @@ -457,7 +485,7 @@ static const struct adc_ops_s g_adcops = #ifdef CONFIG_STM32_ADC1 static struct stm32_dev_s g_adcpriv1 = { -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #endif @@ -465,8 +493,12 @@ static struct stm32_dev_s g_adcpriv1 = .base = STM32_ADC1_BASE, .smp1 = ADC1_SMPR1, .smp2 = ADC1_SMPR2, - .extsel = ADC1_EXTSEL_VALUE, - .jextsel = ADC1_JEXTSEL_VALUE, +#if defined(ADC1_HAVE_EXTSEL) + .extsel = ADC1_EXTSEL_VALUE | HAVE_EXTSEL_MASK, +#endif +#if defined(ADC1_HAVE_JEXTSEL) + .jextsel = ADC1_JEXTSEL_VALUE | HAVE_EXTSEL_MASK, +#endif #ifdef ADC1_HAVE_TIMER .trigger = CONFIG_STM32_ADC1_TIMTRIG, .tbase = ADC1_TIMER_BASE, @@ -491,7 +523,7 @@ static struct adc_dev_s g_adcdev1 = #ifdef CONFIG_STM32_ADC2 static struct stm32_dev_s g_adcpriv2 = { -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ .irq = STM32_IRQ_ADC12, .isr = adc12_interrupt, #endif @@ -499,8 +531,12 @@ static struct stm32_dev_s g_adcpriv2 = .base = STM32_ADC2_BASE, .smp1 = ADC2_SMPR1, .smp2 = ADC2_SMPR2, - .extsel = ADC2_EXTSEL_VALUE, - .jextsel = ADC2_JEXTSEL_VALUE, +#ifdef ADC2_HAVE_EXTSEL + .extsel = ADC2_EXTSEL_VALUE | HAVE_EXTSEL_MASK, +#endif +#ifdef ADC2_HAVE_JEXTSEL + .jextsel = ADC2_JEXTSEL_VALUE | HAVE_EXTSEL_MASK, +#endif #ifdef ADC2_HAVE_TIMER .trigger = CONFIG_STM32_ADC2_TIMTRIG, .tbase = ADC2_TIMER_BASE, @@ -1416,7 +1452,7 @@ static void adc_reset(FAR struct adc_dev_s *dev) adc_modifyreg(priv, STM32_ADC_CFGR_OFFSET, clrbits, setbits); -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ /* Enable interrupt flags, but disable overrun interrupt */ clrbits = ADC_IER_OVR; @@ -1488,16 +1524,27 @@ static void adc_reset(FAR struct adc_dev_s *dev) * position. */ - ainfo("Initializing timers extsel = 0x%08x nad jextsel = 0x%08x\n", - priv->extsel, priv->jextsel); +#ifdef ADC_HAVE_EXTSEL + if (priv->extsel & HAVE_EXTSEL_MASK) + { + ainfo("Initializing extsel = 0x%08x\n", (priv->extsel & ~HAVE_EXTSEL_MASK)); - adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, - ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK, - ADC_EXTREG_EXTEN_DEFAULT | priv->extsel); + adc_modifyreg(priv, STM32_ADC_EXTREG_OFFSET, + ADC_EXTREG_EXTEN_MASK | ADC_EXTREG_EXTSEL_MASK, + ADC_EXTREG_EXTEN_DEFAULT | (priv->extsel & ~HAVE_EXTSEL_MASK)); + } +#endif - adc_modifyreg(priv, STM32_ADC_JEXTREG_OFFSET, - ADC_JEXTREG_JEXTEN_MASK | ADC_JEXTREG_JEXTSEL_MASK, - ADC_JEXTREG_JEXTEN_DEFAULT | priv->jextsel); +#ifdef ADC_HAVE_JEXTSEL + if (priv->jextsel & HAVE_EXTSEL_MASK) + { + ainfo("Initializing jextsel = 0x%08x\n", (priv->jextsel & ~HAVE_EXTSEL_MASK)); + + adc_modifyreg(priv, STM32_ADC_JEXTREG_OFFSET, + ADC_JEXTREG_JEXTEN_MASK | ADC_JEXTREG_JEXTSEL_MASK, + ADC_JEXTREG_JEXTEN_DEFAULT | (priv->jextsel & ~HAVE_EXTSEL_MASK)); + } +#endif #ifdef ADC_HAVE_TIMER if (priv->tbase != 0) @@ -1555,12 +1602,14 @@ static void adc_reset(FAR struct adc_dev_s *dev) static int adc_setup(FAR struct adc_dev_s *dev) { +#ifndef CONFIG_STM32_ADC_NOIRQ FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; +#endif int ret; /* Attach the ADC interrupt */ -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ret = irq_attach(priv->irq, priv->isr, NULL); if (ret < 0) { @@ -1575,7 +1624,7 @@ static int adc_setup(FAR struct adc_dev_s *dev) /* Enable the ADC interrupt */ -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ ainfo("Enable the ADC interrupt: irq=%d\n", priv->irq); up_enable_irq(priv->irq); #endif @@ -1604,7 +1653,7 @@ static void adc_shutdown(FAR struct adc_dev_s *dev) /* Disable ADC interrupts and detach the ADC interrupt handler */ -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ up_disable_irq(priv->irq); irq_detach(priv->irq); #endif @@ -1779,7 +1828,7 @@ static int adc_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg) * ****************************************************************************/ -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc_interrupt(FAR struct adc_dev_s *dev) { FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv; @@ -1866,7 +1915,7 @@ static int adc_interrupt(FAR struct adc_dev_s *dev) * ****************************************************************************/ -#ifdef CONFIG_STM32_ADC_NOIRQ +#ifndef CONFIG_STM32_ADC_NOIRQ static int adc12_interrupt(int irq, FAR void *context, FAR void *arg) { #ifdef CONFIG_STM32_ADC1 diff --git a/configs/nucleo-f334r8/adc/defconfig b/configs/nucleo-f334r8/adc/defconfig index cd28a4d6bf..b96e5cbf3c 100644 --- a/configs/nucleo-f334r8/adc/defconfig +++ b/configs/nucleo-f334r8/adc/defconfig @@ -93,10 +93,10 @@ CONFIG_STM32_ADC1=y CONFIG_STM32_DMA1=y CONFIG_STM32_JTAG_SW_ENABLE=y CONFIG_STM32_PWR=y -CONFIG_STM32_USART1=y +CONFIG_STM32_USART2=y CONFIG_TASK_NAME_SIZE=0 CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=512 -CONFIG_USART1_SERIAL_CONSOLE=y +CONFIG_USART2_SERIAL_CONSOLE=y CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_USERMAIN_STACKSIZE=1024 CONFIG_WDOG_INTRESERVE=0