arch/intel64: select the system clock source with choice option

this will make it easier to add other sources as system clock

Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>

arch/x86_64/src/intel64/CMakeLists.txt

@@ -53,10 +53,12 @@ if(CONFIG_MULTBOOT2_FB_TERM)
   list(APPEND SRCS intel64_mbfb.c)
 endif()
 
-if(CONFIG_SCHED_TICKLESS)
-  list(APPEND SRCS intel64_tickless.c)
-else()
-  list(APPEND SRCS intel64_timerisr.c)
+if(CONFIG_ARCH_INTEL64_HAVE_TSC)
+  if(CONFIG_SCHED_TICKLESS)
+    list(APPEND SRCS intel64_tsc_tickless.c)
+  else()
+    list(APPEND SRCS intel64_tsc_timerisr.c)
+  endif()
 endif()
 
 if(CONFIG_INTEL64_HPET)

arch/x86_64/src/intel64/Kconfig

@@ -18,13 +18,31 @@ config ARCH_CHIP_INTEL64_CUSTOM
 
 endchoice # "Intel64 Chip Selection"
 
-config ARCH_INTEL64_HAVE_TSC_DEADLINE
+config ARCH_INTEL64_HAVE_TSC
+	bool
+
+choice
+	prompt "System Timer Source"
+	default ARCH_INTEL64_TSC_DEADLINE
+	---help---
+		Choose which hardware resource will drive NuttX
+		system time
+
+config ARCH_INTEL64_TSC_DEADLINE
 	bool "TSC DEADLINE timer support"
-	default y
+	select ARCH_INTEL64_HAVE_TSC
 	---help---
 		Select to enable the use of TSC DEADLINE timer of x86_64
 
-if ARCH_INTEL64_HAVE_TSC_DEADLINE
+config ARCH_INTEL64_TSC
+	bool "TSC APIC timer support"
+	select ARCH_INTEL64_HAVE_TSC
+	---help---
+		Select to enable the use of TSC APIC timer of x86_64
+
+endchoice # System Timer Source
+
+if ARCH_INTEL64_TSC_DEADLINE
 
 config ARCH_INTEL64_CORE_FREQ_KHZ
 	int "CPU Core frequency in kHz"
@@ -35,7 +53,7 @@ config ARCH_INTEL64_CORE_FREQ_KHZ
 
 endif
 
-if !ARCH_INTEL64_HAVE_TSC_DEADLINE
+if ARCH_INTEL64_TSC
 
 config ARCH_INTEL64_APIC_FREQ_KHZ
 	int "APIC timer frequency in kHz"

arch/x86_64/src/intel64/Make.defs

@@ -52,12 +52,12 @@ ifeq ($(CONFIG_MULTBOOT2_FB_TERM),y)
 CHIP_CSRCS += intel64_mbfb.c
 endif
 
-ifneq ($(CONFIG_SCHED_TICKLESS),y)
-CHIP_CSRCS += intel64_timerisr.c
-endif
-
+ifeq ($(CONFIG_ARCH_INTEL64_HAVE_TSC),y)
 ifeq ($(CONFIG_SCHED_TICKLESS),y)
-CHIP_CSRCS += intel64_tickless.c
+CHIP_CSRCS += intel64_tsc_tickless.c
+else
+CHIP_CSRCS += intel64_tsc_timerisr.c
+endif
 endif
 
 ifeq ($(CONFIG_INTEL64_HPET),y)

arch/x86_64/src/intel64/intel64_check_capability.c

@@ -63,7 +63,7 @@ void x86_64_check_and_enable_capability(void)
 
   /* Check timer availability */
 
-#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE
+#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE
   require |= X86_64_CPUID_01_TSCDEA;
 #endif
 

arch/x86_64/src/intel64/intel64_tsc_tickless.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/x86_64/src/intel64/intel64_tickless.c
+ * arch/x86_64/src/intel64/intel64_tsc_tickless.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -92,7 +92,7 @@ void up_mask_tmr(void)
 {
   /* Disable TSC Deadline interrupt */
 
-#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE
+#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE
   write_msr(MSR_X2APIC_LVTT, TMR_IRQ | MSR_X2APIC_LVTT_TSC_DEADLINE |
             (1 << 16));
 #else
@@ -108,7 +108,7 @@ void up_unmask_tmr(void)
 {
   /* Enable TSC Deadline interrupt */
 
-#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE
+#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE
   write_msr(MSR_X2APIC_LVTT, TMR_IRQ | MSR_X2APIC_LVTT_TSC_DEADLINE);
 #else
   write_msr(MSR_X2APIC_LVTT, TMR_IRQ);

arch/x86_64/src/intel64/intel64_tsc_timerisr.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * arch/x86_64/src/intel64/intel64_timerisr.c
+ * arch/x86_64/src/intel64/intel64_tsc_timerisr.c
  *
  * Licensed to the Apache Software Foundation (ASF) under one or more
  * contributor license agreements.  See the NOTICE file distributed with
@@ -75,7 +75,7 @@ void apic_timer_set(unsigned long timeout_ns)
 {
   unsigned long long ticks =
     (unsigned long long)timeout_ns * x86_64_timer_freq / NS_PER_SEC;
-#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE
+#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE
     write_msr(MSR_IA32_TSC_DEADLINE, rdtsc() + ticks);
 #else
     write_msr(MSR_X2APIC_TMICT, ticks);
@@ -120,7 +120,7 @@ void up_timer_initialize(void)
 
   irq_attach(IRQ0, (xcpt_t)intel64_timerisr, NULL);
 
-#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE
+#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE
   vector |= MSR_X2APIC_LVTT_TSC_DEADLINE;
 #endif
 

boards/x86_64/intel64/qemu-intel64/src/qemu_freq.c

@@ -71,7 +71,7 @@ extern unsigned long x86_64_timer_freq;
 
 void x86_64_timer_calibrate_freq(void)
 {
-#ifdef CONFIG_ARCH_INTEL64_HAVE_TSC_DEADLINE
+#ifdef CONFIG_ARCH_INTEL64_TSC_DEADLINE
 
   unsigned long crystal_freq;
   unsigned long numerator;
@@ -91,7 +91,7 @@ void x86_64_timer_calibrate_freq(void)
       x86_64_timer_freq = crystal_freq / denominator * numerator;
     }
 
-#else
+#elif defined(CONFIG_ARCH_INTEL64_TSC)
   x86_64_timer_freq = CONFIG_ARCH_INTEL64_APIC_FREQ_KHZ * 1000L;
 #endif
 }