diff --git a/arch/arm/src/s32k1xx/s32k11x/s32k11x_clocknames.h b/arch/arm/src/s32k1xx/s32k11x/s32k11x_clocknames.h index e2fb7f1feb..78751c617d 100644 --- a/arch/arm/src/s32k1xx/s32k11x/s32k11x_clocknames.h +++ b/arch/arm/src/s32k1xx/s32k11x/s32k11x_clocknames.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k11x/s32k11x_clocknames.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -50,105 +50,93 @@ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_CLOCKNAMES_H #define __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_CLOCKNAMES_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ enum clock_names_e { /* Main clocks */ - CORE_CLK = 0, /* Core clock */ - BUS_CLK = 1, /* Bus clock */ - SLOW_CLK = 2, /* Slow clock */ - CLKOUT_CLK = 3, /* CLKOUT clock */ + CORE_CLK = 0, /* Core clock */ + BUS_CLK = 1, /* Bus clock */ + SLOW_CLK = 2, /* Slow clock */ + CLKOUT_CLK = 3, /* CLKOUT clock */ /* Other internal clocks used by peripherals. */ - SIRC_CLK = 4, /* SIRC clock */ - FIRC_CLK = 5, /* FIRC clock */ - SOSC_CLK = 6, /* SOSC clock */ - RTC_CLKIN_CLK = 8, /* RTC_CLKIN clock */ - SCG_CLKOUT_CLK = 9, /* SCG CLK_OUT clock */ - SIRCDIV1_CLK = 10, /* SIRCDIV1 functional clock */ - SIRCDIV2_CLK = 11, /* SIRCDIV2 functional clock */ - FIRCDIV1_CLK = 12, /* FIRCDIV1 functional clock */ - FIRCDIV2_CLK = 13, /* FIRCDIV2 functional clock */ - SOSCDIV1_CLK = 14, /* SOSCDIV1 functional clock */ - SOSCDIV2_CLK = 15, /* SOSCDIV2 functional clock */ + SIRC_CLK = 4, /* SIRC clock */ + FIRC_CLK = 5, /* FIRC clock */ + SOSC_CLK = 6, /* SOSC clock */ + RTC_CLKIN_CLK = 8, /* RTC_CLKIN clock */ + SCG_CLKOUT_CLK = 9, /* SCG CLK_OUT clock */ + SIRCDIV1_CLK = 10, /* SIRCDIV1 functional clock */ + SIRCDIV2_CLK = 11, /* SIRCDIV2 functional clock */ + FIRCDIV1_CLK = 12, /* FIRCDIV1 functional clock */ + FIRCDIV2_CLK = 13, /* FIRCDIV2 functional clock */ + SOSCDIV1_CLK = 14, /* SOSCDIV1 functional clock */ + SOSCDIV2_CLK = 15, /* SOSCDIV2 functional clock */ - SCG_END_OF_CLOCKS = 18, /* End of SCG clocks */ + SCG_END_OF_CLOCKS = 18, /* End of SCG clocks */ /* SIM clocks */ - SIM_FTM0_CLOCKSEL = 21, /* FTM0 External Clock Pin Select */ - SIM_FTM1_CLOCKSEL = 22, /* FTM1 External Clock Pin Select */ - SIM_CLKOUTSELL = 23, /* CLKOUT Select */ - SIM_RTCCLK_CLK = 24, /* RTCCLK clock */ - SIM_LPO_CLK = 25, /* LPO clock */ - SIM_LPO_1K_CLK = 26, /* LPO 1KHz clock */ - SIM_LPO_32K_CLK = 27, /* LPO 32KHz clock */ - SIM_LPO_128K_CLK = 28, /* LPO 128KHz clock */ - SIM_EIM_CLK = 29, /* EIM clock source */ - SIM_ERM_CLK = 30, /* ERM clock source */ - SIM_DMA_CLK = 31, /* DMA clock source */ - SIM_MPU_CLK = 32, /* MPU clock source */ - SIM_MSCM_CLK = 33, /* MSCM clock source */ - SIM_END_OF_CLOCKS = 34, /* End of SIM clocks */ + SIM_FTM0_CLOCKSEL = 21, /* FTM0 External Clock Pin Select */ + SIM_FTM1_CLOCKSEL = 22, /* FTM1 External Clock Pin Select */ + SIM_CLKOUTSELL = 23, /* CLKOUT Select */ + SIM_RTCCLK_CLK = 24, /* RTCCLK clock */ + SIM_LPO_CLK = 25, /* LPO clock */ + SIM_LPO_1K_CLK = 26, /* LPO 1KHz clock */ + SIM_LPO_32K_CLK = 27, /* LPO 32KHz clock */ + SIM_LPO_128K_CLK = 28, /* LPO 128KHz clock */ + SIM_EIM_CLK = 29, /* EIM clock source */ + SIM_ERM_CLK = 30, /* ERM clock source */ + SIM_DMA_CLK = 31, /* DMA clock source */ + SIM_MPU_CLK = 32, /* MPU clock source */ + SIM_MSCM_CLK = 33, /* MSCM clock source */ + SIM_END_OF_CLOCKS = 34, /* End of SIM clocks */ - CMP0_CLK = 41, /* CMP0 clock source */ - CRC0_CLK = 42, /* CRC0 clock source */ - DMAMUX0_CLK = 43, /* DMAMUX0 clock source */ - PORTA_CLK = 44, /* PORTA clock source */ - PORTB_CLK = 45, /* PORTB clock source */ - PORTC_CLK = 46, /* PORTC clock source */ - PORTD_CLK = 47, /* PORTD clock source */ - PORTE_CLK = 48, /* PORTE clock source */ - RTC0_CLK = 49, /* RTC0 clock source */ - PCC_END_OF_BUS_CLOCKS = 50, /* End of BUS clocks */ - FlexCAN0_CLK = 51, /* FlexCAN0 clock source */ - PDB0_CLK = 52, /* PDB0 clock source */ - PCC_END_OF_SYS_CLOCKS = 53, /* End of SYS clocks */ - FTFC0_CLK = 54, /* FTFC0 clock source */ - PCC_END_OF_SLOW_CLOCKS = 55, /* End of SLOW clocks */ - FTM0_CLK = 56, /* FTM0 clock source */ - FTM1_CLK = 57, /* FTM1 clock source */ - PCC_END_OF_ASYNCH_DIV1_CLOCKS= 58, /* End of ASYNCH DIV1 clocks */ - ADC0_CLK = 59, /* ADC0 clock source */ - FLEXIO0_CLK = 60, /* FLEXIO0 clock source */ - LPI2C0_CLK = 61, /* LPI2C0 clock source */ - LPIT0_CLK = 62, /* LPIT0 clock source */ - LPSPI0_CLK = 63, /* LPSPI0 clock source */ - LPSPI1_CLK = 64, /* LPSPI1 clock source */ - LPTMR0_CLK = 65, /* LPTMR0 clock source */ - LPUART0_CLK = 66, /* LPUART0 clock source */ - LPUART1_CLK = 67, /* LPUART1 clock source */ - PCC_END_OF_ASYNCH_DIV2_CLOCKS= 68, /* End of ASYNCH DIV2 clocks */ - PCC_END_OF_CLOCKS = 69, /* End of PCC clocks */ - CLOCK_NAME_COUNT = 70, /* The total number of entries */ + CMP0_CLK = 41, /* CMP0 clock source */ + CRC0_CLK = 42, /* CRC0 clock source */ + DMAMUX0_CLK = 43, /* DMAMUX0 clock source */ + PORTA_CLK = 44, /* PORTA clock source */ + PORTB_CLK = 45, /* PORTB clock source */ + PORTC_CLK = 46, /* PORTC clock source */ + PORTD_CLK = 47, /* PORTD clock source */ + PORTE_CLK = 48, /* PORTE clock source */ + RTC0_CLK = 49, /* RTC0 clock source */ + PCC_END_OF_BUS_CLOCKS = 50, /* End of BUS clocks */ + FLEXCAN0_CLK = 51, /* FlexCAN0 clock source */ + PDB0_CLK = 52, /* PDB0 clock source */ + PCC_END_OF_SYS_CLOCKS = 53, /* End of SYS clocks */ + FTFC0_CLK = 54, /* FTFC0 clock source */ + PCC_END_OF_SLOW_CLOCKS = 55, /* End of SLOW clocks */ + FTM0_CLK = 56, /* FTM0 clock source */ + FTM1_CLK = 57, /* FTM1 clock source */ + PCC_END_OF_ASYNCH_DIV1_CLOCKS = 58, /* End of ASYNCH DIV1 clocks */ + ADC0_CLK = 59, /* ADC0 clock source */ + FLEXIO0_CLK = 60, /* FLEXIO0 clock source */ + LPI2C0_CLK = 61, /* LPI2C0 clock source */ + LPIT0_CLK = 62, /* LPIT0 clock source */ + LPSPI0_CLK = 63, /* LPSPI0 clock source */ + LPSPI1_CLK = 64, /* LPSPI1 clock source */ + LPTMR0_CLK = 65, /* LPTMR0 clock source */ + LPUART0_CLK = 66, /* LPUART0 clock source */ + LPUART1_CLK = 67, /* LPUART1 clock source */ + PCC_END_OF_ASYNCH_DIV2_CLOCKS = 68, /* End of ASYNCH DIV2 clocks */ + PCC_END_OF_CLOCKS = 69, /* End of PCC clocks */ + CLOCK_NAME_COUNT = 70, /* The total number of entries */ }; -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - #endif /* __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_CLOCKNAMES_H */ diff --git a/arch/arm/src/s32k1xx/s32k14x/s32k14x_clocknames.h b/arch/arm/src/s32k1xx/s32k14x/s32k14x_clocknames.h index 742374120b..41b310a82f 100644 --- a/arch/arm/src/s32k1xx/s32k14x/s32k14x_clocknames.h +++ b/arch/arm/src/s32k1xx/s32k14x/s32k14x_clocknames.h @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/s32k1xx/s32k14x/s32k14x_clocknames.h * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -50,136 +50,124 @@ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ #ifndef __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_CLOCKNAMES_H #define __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_CLOCKNAMES_H -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ +/**************************************************************************** * Public Types - ************************************************************************************/ + ****************************************************************************/ enum clock_names_e { /* Main clocks */ - CORE_CLK = 0, /* Core clock */ - BUS_CLK = 1, /* Bus clock */ - SLOW_CLK = 2, /* Slow clock */ - CLKOUT_CLK = 3, /* CLKOUT clock */ + CORE_CLK = 0, /* Core clock */ + BUS_CLK = 1, /* Bus clock */ + SLOW_CLK = 2, /* Slow clock */ + CLKOUT_CLK = 3, /* CLKOUT clock */ /* Other internal clocks used by peripherals */ - SIRC_CLK = 4, /* SIRC clock */ - FIRC_CLK = 5, /* FIRC clock */ - SOSC_CLK = 6, /* SOSC clock */ - SPLL_CLK = 7, /* SPLL clock */ - RTC_CLKIN_CLK = 8, /* RTC_CLKIN clock */ - SCG_CLKOUT_CLK = 9, /* SCG CLK_OUT clock */ - SIRCDIV1_CLK = 10, /* SIRCDIV1 functional clock */ - SIRCDIV2_CLK = 11, /* SIRCDIV2 functional clock */ - FIRCDIV1_CLK = 12, /* FIRCDIV1 functional clock */ - FIRCDIV2_CLK = 13, /* FIRCDIV2 functional clock */ - SOSCDIV1_CLK = 14, /* SOSCDIV1 functional clock */ - SOSCDIV2_CLK = 15, /* SOSCDIV2 functional clock */ - SPLLDIV1_CLK = 16, /* SPLLDIV1 functional clock */ - SPLLDIV2_CLK = 17, /* SPLLDIV2 functional clock */ + SIRC_CLK = 4, /* SIRC clock */ + FIRC_CLK = 5, /* FIRC clock */ + SOSC_CLK = 6, /* SOSC clock */ + SPLL_CLK = 7, /* SPLL clock */ + RTC_CLKIN_CLK = 8, /* RTC_CLKIN clock */ + SCG_CLKOUT_CLK = 9, /* SCG CLK_OUT clock */ + SIRCDIV1_CLK = 10, /* SIRCDIV1 functional clock */ + SIRCDIV2_CLK = 11, /* SIRCDIV2 functional clock */ + FIRCDIV1_CLK = 12, /* FIRCDIV1 functional clock */ + FIRCDIV2_CLK = 13, /* FIRCDIV2 functional clock */ + SOSCDIV1_CLK = 14, /* SOSCDIV1 functional clock */ + SOSCDIV2_CLK = 15, /* SOSCDIV2 functional clock */ + SPLLDIV1_CLK = 16, /* SPLLDIV1 functional clock */ + SPLLDIV2_CLK = 17, /* SPLLDIV2 functional clock */ - SCG_END_OF_CLOCKS = 18, /* End of SCG clocks */ + SCG_END_OF_CLOCKS = 18, /* End of SCG clocks */ /* SIM clocks */ - SIM_FTM0_CLOCKSEL = 21, /* FTM0 External Clock Pin Select */ - SIM_FTM1_CLOCKSEL = 22, /* FTM1 External Clock Pin Select */ - SIM_FTM2_CLOCKSEL = 23, /* FTM2 External Clock Pin Select */ - SIM_FTM3_CLOCKSEL = 24, /* FTM3 External Clock Pin Select */ - SIM_FTM4_CLOCKSEL = 25, /* FTM4 External Clock Pin Select */ - SIM_FTM5_CLOCKSEL = 26, /* FTM5 External Clock Pin Select */ - SIM_FTM6_CLOCKSEL = 27, /* FTM6 External Clock Pin Select */ - SIM_FTM7_CLOCKSEL = 28, /* FTM7 External Clock Pin Select */ - SIM_CLKOUTSELL = 29, /* CLKOUT Select */ - SIM_RTCCLK_CLK = 30, /* RTCCLK clock */ - SIM_LPO_CLK = 31, /* LPO clock */ - SIM_LPO_1K_CLK = 32, /* LPO 1KHz clock */ - SIM_LPO_32K_CLK = 33, /* LPO 32KHz clock */ - SIM_LPO_128K_CLK = 34, /* LPO 128KHz clock */ - SIM_EIM_CLK = 35, /* EIM clock source */ - SIM_ERM_CLK = 36, /* ERM clock source */ - SIM_DMA_CLK = 37, /* DMA clock source */ - SIM_MPU_CLK = 38, /* MPU clock source */ - SIM_MSCM_CLK = 39, /* MSCM clock source */ - QSPI_MODULE_SFIF_CLK_HYP = 40, /* QSPI module SFIF clock source */ - QSPI_MODULE_CLK = 41, /* QSPI module clock source */ - QSPI_MODULE_CLK_SFIF = 42, /* QSPI module clock source SFIF */ - QSPI_MODULE_CLK_2XSFIF = 43, /* QSPI module clock source 2XSFIF*/ - SIM_END_OF_CLOCKS = 44, /* End of SIM clocks */ + SIM_FTM0_CLOCKSEL = 21, /* FTM0 External Clock Pin Select */ + SIM_FTM1_CLOCKSEL = 22, /* FTM1 External Clock Pin Select */ + SIM_FTM2_CLOCKSEL = 23, /* FTM2 External Clock Pin Select */ + SIM_FTM3_CLOCKSEL = 24, /* FTM3 External Clock Pin Select */ + SIM_FTM4_CLOCKSEL = 25, /* FTM4 External Clock Pin Select */ + SIM_FTM5_CLOCKSEL = 26, /* FTM5 External Clock Pin Select */ + SIM_FTM6_CLOCKSEL = 27, /* FTM6 External Clock Pin Select */ + SIM_FTM7_CLOCKSEL = 28, /* FTM7 External Clock Pin Select */ + SIM_CLKOUTSELL = 29, /* CLKOUT Select */ + SIM_RTCCLK_CLK = 30, /* RTCCLK clock */ + SIM_LPO_CLK = 31, /* LPO clock */ + SIM_LPO_1K_CLK = 32, /* LPO 1KHz clock */ + SIM_LPO_32K_CLK = 33, /* LPO 32KHz clock */ + SIM_LPO_128K_CLK = 34, /* LPO 128KHz clock */ + SIM_EIM_CLK = 35, /* EIM clock source */ + SIM_ERM_CLK = 36, /* ERM clock source */ + SIM_DMA_CLK = 37, /* DMA clock source */ + SIM_MPU_CLK = 38, /* MPU clock source */ + SIM_MSCM_CLK = 39, /* MSCM clock source */ + QSPI_MODULE_SFIF_CLK_HYP = 40, /* QSPI module SFIF clock source */ + QSPI_MODULE_CLK = 41, /* QSPI module clock source */ + QSPI_MODULE_CLK_SFIF = 42, /* QSPI module clock source SFIF */ + QSPI_MODULE_CLK_2XSFIF = 43, /* QSPI module clock source 2XSFIF */ + SIM_END_OF_CLOCKS = 44, /* End of SIM clocks */ - CMP0_CLK = 45, /* CMP0 clock source */ - CRC0_CLK = 46, /* CRC0 clock source */ - DMAMUX0_CLK = 47, /* DMAMUX0 clock source */ - EWM0_CLK = 48, /* EWM0 clock source */ - PORTA_CLK = 49, /* PORTA clock source */ - PORTB_CLK = 50, /* PORTB clock source */ - PORTC_CLK = 51, /* PORTC clock source */ - PORTD_CLK = 52, /* PORTD clock source */ - PORTE_CLK = 53, /* PORTE clock source */ - RTC0_CLK = 54, /* RTC0 clock source */ - SAI0_CLK = 55, /* SAI0 clock source */ - SAI1_CLK = 56, /* SAI1 clock source */ - PCC_END_OF_BUS_CLOCKS = 57, /* End of BUS clocks */ - FlexCAN0_CLK = 58, /* FlexCAN0 clock source */ - FlexCAN1_CLK = 59, /* FlexCAN1 clock source */ - FlexCAN2_CLK = 60, /* FlexCAN2 clock source */ - PDB0_CLK = 61, /* PDB0 clock source */ - PDB1_CLK = 62, /* PDB1 clock source */ - PCC_END_OF_SYS_CLOCKS = 63, /* End of SYS clocks */ - FTFC0_CLK = 64, /* FTFC0 clock source */ - PCC_END_OF_SLOW_CLOCKS = 65, /* End of SLOW clocks */ - ENET0_CLK = 66, /* ENET0 clock source */ - FTM0_CLK = 67, /* FTM0 clock source */ - FTM1_CLK = 68, /* FTM1 clock source */ - FTM2_CLK = 69, /* FTM2 clock source */ - FTM3_CLK = 70, /* FTM3 clock source */ - FTM4_CLK = 71, /* FTM4 clock source */ - FTM5_CLK = 72, /* FTM5 clock source */ - FTM6_CLK = 73, /* FTM6 clock source */ - FTM7_CLK = 74, /* FTM7 clock source */ - PCC_END_OF_ASYNCH_DIV1_CLOCKS = 75, /* End of ASYNCH DIV1 clocks */ - ADC0_CLK = 76, /* ADC0 clock source */ - ADC1_CLK = 77, /* ADC1 clock source */ - FLEXIO0_CLK = 78, /* FLEXIO0 clock source */ - LPI2C0_CLK = 79, /* LPI2C0 clock source */ - LPI2C1_CLK = 80, /* LPI2C1 clock source */ - LPIT0_CLK = 81, /* LPIT0 clock source */ - LPSPI0_CLK = 82, /* LPSPI0 clock source */ - LPSPI1_CLK = 83, /* LPSPI1 clock source */ - LPSPI2_CLK = 84, /* LPSPI2 clock source */ - LPTMR0_CLK = 85, /* LPTMR0 clock source */ - LPUART0_CLK = 86, /* LPUART0 clock source */ - LPUART1_CLK = 87, /* LPUART1 clock source */ - LPUART2_CLK = 88, /* LPUART2 clock source */ - QSPI0_CLK = 89, /* QSPI0 clock source */ - PCC_END_OF_ASYNCH_DIV2_CLOCKS = 90, /* End of ASYNCH DIV2 clocks */ - PCC_END_OF_CLOCKS = 91, /* End of PCC clocks */ - CLOCK_NAME_COUNT = 92, /* The total number of entries */ + CMP0_CLK = 45, /* CMP0 clock source */ + CRC0_CLK = 46, /* CRC0 clock source */ + DMAMUX0_CLK = 47, /* DMAMUX0 clock source */ + EWM0_CLK = 48, /* EWM0 clock source */ + PORTA_CLK = 49, /* PORTA clock source */ + PORTB_CLK = 50, /* PORTB clock source */ + PORTC_CLK = 51, /* PORTC clock source */ + PORTD_CLK = 52, /* PORTD clock source */ + PORTE_CLK = 53, /* PORTE clock source */ + RTC0_CLK = 54, /* RTC0 clock source */ + SAI0_CLK = 55, /* SAI0 clock source */ + SAI1_CLK = 56, /* SAI1 clock source */ + PCC_END_OF_BUS_CLOCKS = 57, /* End of BUS clocks */ + FLEXCAN0_CLK = 58, /* FlexCAN0 clock source */ + FLEXCAN1_CLK = 59, /* FlexCAN1 clock source */ + FLEXCAN2_CLK = 60, /* FlexCAN2 clock source */ + PDB0_CLK = 61, /* PDB0 clock source */ + PDB1_CLK = 62, /* PDB1 clock source */ + PCC_END_OF_SYS_CLOCKS = 63, /* End of SYS clocks */ + FTFC0_CLK = 64, /* FTFC0 clock source */ + PCC_END_OF_SLOW_CLOCKS = 65, /* End of SLOW clocks */ + ENET0_CLK = 66, /* ENET0 clock source */ + FTM0_CLK = 67, /* FTM0 clock source */ + FTM1_CLK = 68, /* FTM1 clock source */ + FTM2_CLK = 69, /* FTM2 clock source */ + FTM3_CLK = 70, /* FTM3 clock source */ + FTM4_CLK = 71, /* FTM4 clock source */ + FTM5_CLK = 72, /* FTM5 clock source */ + FTM6_CLK = 73, /* FTM6 clock source */ + FTM7_CLK = 74, /* FTM7 clock source */ + PCC_END_OF_ASYNCH_DIV1_CLOCKS = 75, /* End of ASYNCH DIV1 clocks */ + ADC0_CLK = 76, /* ADC0 clock source */ + ADC1_CLK = 77, /* ADC1 clock source */ + FLEXIO0_CLK = 78, /* FLEXIO0 clock source */ + LPI2C0_CLK = 79, /* LPI2C0 clock source */ + LPI2C1_CLK = 80, /* LPI2C1 clock source */ + LPIT0_CLK = 81, /* LPIT0 clock source */ + LPSPI0_CLK = 82, /* LPSPI0 clock source */ + LPSPI1_CLK = 83, /* LPSPI1 clock source */ + LPSPI2_CLK = 84, /* LPSPI2 clock source */ + LPTMR0_CLK = 85, /* LPTMR0 clock source */ + LPUART0_CLK = 86, /* LPUART0 clock source */ + LPUART1_CLK = 87, /* LPUART1 clock source */ + LPUART2_CLK = 88, /* LPUART2 clock source */ + QSPI0_CLK = 89, /* QSPI0 clock source */ + PCC_END_OF_ASYNCH_DIV2_CLOCKS = 90, /* End of ASYNCH DIV2 clocks */ + PCC_END_OF_CLOCKS = 91, /* End of PCC clocks */ + CLOCK_NAME_COUNT = 92, /* The total number of entries */ }; -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - #endif /* __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_CLOCKNAMES_H */ diff --git a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c index 9fd24eadc4..43ed3da109 100644 --- a/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c +++ b/arch/arm/src/s32k1xx/s32k1xx_periphclocks.c @@ -1,4 +1,4 @@ -/**************************************************************************** +/************************************************************************************ * arch/arm/src/s32k1xx/s32k1xx_periphclocks.c * * Copyright (C) 2019 Gregory Nutt. All rights reserved. @@ -50,11 +50,11 @@ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF * THE POSSIBILITY OF SUCH DAMAGE. * - ****************************************************************************/ + ************************************************************************************/ -/**************************************************************************** +/************************************************************************************ * Included Files - ****************************************************************************/ + ************************************************************************************/ #include @@ -68,11 +68,11 @@ #include "s32k1xx_clockconfig.h" #include "s32k1xx_periphclocks.h" -/**************************************************************************** +/************************************************************************************ * Private Functions - ****************************************************************************/ + ************************************************************************************/ -/**************************************************************************** +/************************************************************************************ * Name: s32k1xx_get_pclkctrl * * Description: @@ -86,7 +86,7 @@ * Address of peripheral control register. NULL is returned if the clock * name does not map to a PCC control register. * - ****************************************************************************/ + ************************************************************************************/ static uint32_t *s32k1xx_get_pclkctrl(enum clock_names_e clkname) { @@ -104,7 +104,7 @@ static uint32_t *s32k1xx_get_pclkctrl(enum clock_names_e clkname) return NULL; } -/**************************************************************************** +/************************************************************************************ * Name: s32k1xx_pclk_disable * * Description: @@ -117,7 +117,7 @@ static uint32_t *s32k1xx_get_pclkctrl(enum clock_names_e clkname) * Returned Value: * None * - ****************************************************************************/ + ************************************************************************************/ static void s32k1xx_pclk_disable(enum clock_names_e clkname) { @@ -127,7 +127,7 @@ static void s32k1xx_pclk_disable(enum clock_names_e clkname) *ctrlp &= ~PCC_CGC; } -/**************************************************************************** +/************************************************************************************ * Name: s32k1xx_set_pclkctrl * * Description: @@ -139,7 +139,7 @@ static void s32k1xx_pclk_disable(enum clock_names_e clkname) * Returned Value: * None * - ****************************************************************************/ + ************************************************************************************/ static inline void s32k1xx_set_pclkctrl(const struct peripheral_clock_config_s *pclk) @@ -149,26 +149,31 @@ s32k1xx_set_pclkctrl(const struct peripheral_clock_config_s *pclk) DEBUGASSERT(ctrlp != NULL); - /* Configure the peripheral clock source, the fractional clock divider - * and the clock gate. - */ + /* Configure the peripheral clock source, the fractional clock divider and + * the clock gate. + */ - regval = PCC_PCS(pclk->clksrc) | PCC_PCD(pclk->divider); + regval = PCC_PCS(pclk->clksrc); - if (pclk->frac == MULTIPLY_BY_TWO) - { - regval |= PCC_FRAC; - } + if (pclk->divider > 1) + { + regval |= PCC_PCD(pclk->divider); + } - if (pclk->clkgate) - { - regval |= PCC_CGC; - } + if (pclk->frac == MULTIPLY_BY_TWO) + { + regval |= PCC_FRAC; + } - *ctrlp = regval; + if (pclk->clkgate) + { + regval |= PCC_CGC; + } + + *ctrlp = regval; } -/**************************************************************************** +/************************************************************************************ * Name: s32k1xx_get_pclkfreq_divided * * Description: @@ -181,19 +186,19 @@ s32k1xx_set_pclkctrl(const struct peripheral_clock_config_s *pclk) * Returned Value: * None * - ****************************************************************************/ + ************************************************************************************/ static uint32_t s32k1xx_get_pclkfreq_divided(enum clock_names_e clkname, enum scg_async_clock_type_e divider) { - uint32_t *ctrlp; - uint32_t frequency = 0; - uint32_t frac; - uint32_t div; + uint32_t *ctrlp; + uint32_t frequency = 0; + uint32_t frac; + uint32_t div; - ctrlp = s32k1xx_get_pclkctrl(clkname); - frac = ((*ctrlp & PCC_FRAC) == 0) ? 0 : 1; - div = (*ctrlp & PCC_PCD_MASK) >> PCC_PCD_SHIFT; + ctrlp = s32k1xx_get_pclkctrl(clkname); + frac = ((*ctrlp & PCC_FRAC) == 0) ? 0 : 1; + div = (*ctrlp & PCC_PCD_MASK) >> PCC_PCD_SHIFT; /* Check division factor */ @@ -241,12 +246,11 @@ static uint32_t s32k1xx_get_pclkfreq_divided(enum clock_names_e clkname, return frequency; } - -/**************************************************************************** +/************************************************************************************ * Public Functions - ****************************************************************************/ + ************************************************************************************/ -/**************************************************************************** +/************************************************************************************ * Name: s32k1xx_periphclocks * * Description: @@ -259,7 +263,7 @@ static uint32_t s32k1xx_get_pclkfreq_divided(enum clock_names_e clkname, * Returned Value: * None * - ****************************************************************************/ + ************************************************************************************/ void s32k1xx_periphclocks(unsigned int count, const struct peripheral_clock_config_s *pclks) @@ -280,7 +284,7 @@ void s32k1xx_periphclocks(unsigned int count, } } -/**************************************************************************** +/************************************************************************************ * Name: s32k1xx_get_pclkfreq * * Description: @@ -297,7 +301,7 @@ void s32k1xx_periphclocks(unsigned int count, * any failure. -ENODEV is returned if the clock is not enabled or is not * being clocked. * - ****************************************************************************/ + ************************************************************************************/ int s32k1xx_get_pclkfreq(enum clock_names_e clkname, uint32_t *frequency) {