From 0a8aa537a2e0093b7b471d3d9886f345b39b6326 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Wed, 5 Dec 2018 17:42:50 -0600 Subject: [PATCH] arch/arm/src/tiva/cc13xx/cc13xx_gpio.h: Add CC13xx GPIO encoding file. --- arch/arm/src/tiva/cc13xx/cc13xx_gpio.h | 249 ++++++++++++++++++ .../arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h | 129 ++++----- .../cc13x2_cc26x2/cc13x2_cc26x2_ioc.h | 129 ++++----- arch/arm/src/tiva/lm/lm3s_gpio.h | 4 +- arch/arm/src/tiva/lm/lmf4_gpio.h | 4 +- arch/arm/src/tiva/tm4c/tm4c_gpio.h | 4 +- 6 files changed, 388 insertions(+), 131 deletions(-) create mode 100644 arch/arm/src/tiva/cc13xx/cc13xx_gpio.h diff --git a/arch/arm/src/tiva/cc13xx/cc13xx_gpio.h b/arch/arm/src/tiva/cc13xx/cc13xx_gpio.h new file mode 100644 index 0000000000..0ad837cf54 --- /dev/null +++ b/arch/arm/src/tiva/cc13xx/cc13xx_gpio.h @@ -0,0 +1,249 @@ +/**************************************************************************** + * arch/arm/src/tiva/cc13x0/cc13x0_gpio.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * With modifications from Calvin Maguranis + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H +#define __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Bit-encoded input to tiva_configgpio() ***********************************/ + +/* Encoding: + * + * PPPP PPIO WCCR SSHS PPAA GIII EEVD DDDD + * + * PPPPPP - 6 bits. Port ID (see definitions in hardware/c13x0/c13x0_ioc.h + * and hardware.cc13x2_cc26x2/cc13x2_cc26x2_ioc) + * I - 1 bit Input Enable + * O - 1 bit GPIO output + * W - 1 bit Wakeup enable (CC13x2/CC26x only) + * CC - 2 bits Wakeup Configuration + * R - 1 bit RTC event enable (CC13x2/CC26x only) + * SS - 2 bits Drive strength + * H - 1 bit Input hysteresis + * S - 1 bit Reduced output slew enable + * PP - 2 bits Pull-up mode + * AA - 2 bits Current mode + * G - 1 bit Enable interrupt Generation + * III - 3 bits I/O mode + * EE - 2 bits Edge detect mode + * 0 - 1 bit Edge asserts AON_PROG0 (CC13x2/CC26x only) NOTE 1 + * 1 - 1 bit Edge asserts AON_PROG1 (CC13x2/CC26x only) NOTE 1 + * 2 - 1 bit Edge asserts AON_PROG2 (CC13x2/CC26x only) NOTE 1 + * V - 1 bit GPIO output initial value + * DDDDD - 5 bits DIO 0-31 + *t + * NOTE 1: Not currently implemented because no bits are available in + * the uint32_t. We need more bits! + */ + +/* Port ID + * + * PPPP PP.. .... .... .... .... .... .... + * + * See PORTID definitions in the IOC register definitions file. + */ + +#define GPIO_PORTID_SHIFT (26) /* Bits 26-31: Port ID */ +#define GPIO_PORTID_MASK (0x3f << GPIO_PORTID_SHIFT) +# define GPIO_PORTID(n) ((uint32_t)(n) << GPIO_PORTID_SHIFT) + +/* Input Enable: + * + * .... ..I. .... .... .... .... .... .... + */ + +#define GPIO_IE (1 << 25) /* Bit 25: Input Enable */ +[ +/* GPIO output: + * + * .... ...O .... .... .... .... .... .... + */ + +#define GPIO_OUTPUT (1 << 24) /* Bit 24: Input Enable */ + +/* Wakeup enable (CC13x2/CC26x only): + * + * .... .... W... .... .... .... .... .... + */ + +#define GPIO_WUEN (1 << 23) /* Bit 23: Input edge asserts MCU_WU event */ + +/* Wakeup Configuration: + * + * .... .... .CC. .... .... .... .... .... + */ + +#define GPIO_WUCFG_SHIFT (21) /* Bits 21-22: Wakeup Configuration */ +#define GPIO_WUCFG_MASK (3 << GPIO_WUCFG_SHIFT) +# define GPIO_WUCFG_NONE (0 << GPIO_WUCFG_SHIFT) /* 0, 1: Wakeup disabled */ +# define GPIO_WUCFG_ENABLE (2 << GPIO_WUCFG_SHIFT) /* 2, 3: Wakeup enabled */ +# define GPIO_WUCFG_WAKEUPL (2 << GPIO_WUCFG_SHIFT) /* Wakeup on transition low */ +# define GPIO_WUCFG_WEKUPH (3 << GPIO_WUCFG_SHIFT) /* Wakeup on transition high */ + +/* RTC event enable (CC13x2/CC26x only): + * + * .... .... ...R .... .... .... .... .... + */ + +#define GPIO_RTCEN (1 << 20) /* Bit 20: Input edge asserts RTC event */ + +/* Drive strength: + * + * .... .... .... SS.. .... .... .... .... + */ + +#define GPIO_IOSTR_SHIFT (18) /* Bits 18-19: I/O drive strength */ +#define GPIO_IOSTR_MASK (3 << GPIO_IOSTR_SHIFT) +# define GPIO_IOSTR_AUTO (0 << GPIO_IOSTR_SHIFT) /* Automatic drive strength */ +# define GPIO_IOSTR_MIN (1 << GPIO_IOSTR_SHIFT) /* Minimum drive strength */ +# define GPIO_IOSTR_MED (2 << GPIO_IOSTR_SHIFT) /* Medium drive strength */ +# define GPIO_IOSTR_MAX (3 << GPIO_IOSTR_SHIFT) /* Maximum drive strength */ + +/* Input hysteresis: + * + * .... .... .... ..H. .... .... .... .... + */ + +#define GPIO_HYSTEN (1 << 17) /* Bit 17: Input hysteresis enable */ + +/* Reduced output slew enable: + * + * .... .... .... ...S .... .... .... .... + */ + +#define GPIO_SLEW_RED (1 << 16) /* Bit 16: Reduces output slew rate */ + +/* Pull-up mode: + * + * .... .... .... .... PP.. .... .... .... + */ + +#define GPIO_PULL_SHIFT (14) /* Bits 14-15: Pull Control */ +#define GPIO_PULL_MASK (3 << GPIO_PULL_SHIFT) +# define GPIO_PULL_DISABLE (3 << GPIO_PULL_SHIFT) /* No pull */ +# define GPIO_PULL_DOWN (1 << GPIO_PULL_SHIFT) /* Pull down */ +# define GPIO_PULL_UP (2 << GPIO_PULL_SHIFT) /* Pull up */ + +/* Current mode: + * + * .... .... .... .... ..AA .... .... .... + */ + +#define GPIO_IOCURR_SHIFT (12) /* Bits 12-13: I/O current mode */ +#define GPIO_IOCURR_MASK (3 << GPIO_IOCURR_SHIFT) +# define GPIO_IOCURR_2MA (0 << GPIO_IOCURR_SHIFT) /* Extended-Current (EC) mode */ +# define GPIO_IOCURR_4MA (1 << GPIO_IOCURR_SHIFT) /* High-Current (HC) mode */ +# define GPIO_IOCURR_8MA (2 << GPIO_IOCURR_SHIFT) /* Low-Current (LC) mode */ + +/* Enable edge interrupt generation: + * + * .... .... .... .... .... G... .... .... + */ + +#define GPIO_EDGE_IRQEN (1 << 11) /* Bit 11: Enable edge interrupt generation */ + +/* I/O mode: + * + * .... .... .... .... .... .III .... .... + */ + +#define GPIO_IOMODE_SHIFT (8) /* Bits 8-10: I/O Mode */ +#define GPIO_IOMODE_MASK (7 << IOC_IOCFG1_IOMODE_SHIFT) +# define GPIO_IOMODE_NORMAL (0 << IOC_IOCFG1_IOMODE_SHIFT) /* Normal I/O */ +# define GPIO_IOMODE_INV (1 << IOC_IOCFG1_IOMODE_SHIFT) /* Inverted I/O */ +# define GPIO_IOMODE_OPENDR (4 << IOC_IOCFG1_IOMODE_SHIFT) /* Open drain */ +# define GPIO_IOMODE_OPENDRINV (5 << IOC_IOCFG1_IOMODE_SHIFT) /* Open drain, inverted I/O */ +# define GPIO_IOMODE_OPENSRC (6 << IOC_IOCFG1_IOMODE_SHIFT) /* Open source */ +# define GPIO_IOMODE_OPENSRCINV (7 << IOC_IOCFG1_IOMODE_SHIFT) /* Open source, inverted I/O */ + +/* Edge detect mode + * + * .... .... .... .... .... .... EE.. .... + */ + +#define GPIO_EDGE_SHIFT (6) /* Bits 6-7: Enable edge events generation */ +#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT) +# define GPIO_EDGE_NONE (0 << GPIO_EDGE_SHIFT) /* No edge detection */ +# define GPIO_EDGE_NEG (1 << GPIO_EDGE_SHIFT) /* Negative edge detection */ +# define GPIO_EDGE_POS (2 << GPIO_EDGE_SHIFT) /* Positive edge detection */ +# define GPIO_EDGE_BOTH (3 << GPIO_EDGE_SHIFT) /* Both edge detection */ + +#if 0 /* Need more bits! */ +/* Edge asserts AON_PROG0/1/2 (CC13x2/CC26x only): + * + * .... .... .... .... .... .... .... .... + */ + +#define GPIO_AON_PROG0 (1 << xx) /* Bit xx: Input edge asserts AON_PROG0 */ +#define GPIO_AON_PROG1 (1 << xx) /* Bit xx: Input edge asserts AON_PROG1 */ +#define GPIO_AON_PROG2 (1 << xx) /* Bit xx: Input edge assert AON_PROG2 */ + +#endif + +/* GPIO output initial value: + * + * .... .... .... .... .... .... ..V. .... + */ + +#define GPIO_VALUE_SHIFT 8 /* Bit 5: If output, inital value of output */ +#define GPIO_VALUE_MASK (1 << GPIO_VALUE_SHIFT) +# define GPIO_VALUE_ZERO (0 << GPIO_VALUE_SHIFT) /* Initial value is zero */ +# define GPIO_VALUE_ONE (1 << GPIO_VALUE_SHIFT) /* Initial value is one */ + +/* DIO: + * + * .... .... .... .... .... .... ...D DDDD + */ + +#define GPIO_DIO_SHIFT (0) /* Bits 0-4: DIO */ +#define GPIO_DIO_MASK (0x1f << GPIO_PORTID_SHIFT) +# define GPIO_DIO(n) ((uint32_t)(n) << GPIO_PORTID_SHIFT) + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H */ diff --git a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h index 8a650cb586..202ab4a7bc 100644 --- a/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h +++ b/arch/arm/src/tiva/hardware/cc13x0/cc13x0_ioc.h @@ -53,73 +53,74 @@ /* IOC register offsets ************************************************************/ #define TIVA_IOC_IOCFG_OFFSET(n) ((n) << 2) -#define TIVA_IOC_IOCFG0_OFFSET 0x0000 /* Configuration of DIO0 */ -#define TIVA_IOC_IOCFG1_OFFSET 0x0004 /* Configuration of DIO1 */ -#define TIVA_IOC_IOCFG2_OFFSET 0x0008 /* Configuration of DIO2 */ -#define TIVA_IOC_IOCFG3_OFFSET 0x000c /* Configuration of DIO3 */ -#define TIVA_IOC_IOCFG4_OFFSET 0x0010 /* Configuration of DIO4 */ -#define TIVA_IOC_IOCFG5_OFFSET 0x0014 /* Configuration of DIO5 */ -#define TIVA_IOC_IOCFG6_OFFSET 0x0018 /* Configuration of DIO6 */ -#define TIVA_IOC_IOCFG7_OFFSET 0x001c /* Configuration of DIO7 */ -#define TIVA_IOC_IOCFG8_OFFSET 0x0020 /* Configuration of DIO8 */ -#define TIVA_IOC_IOCFG9_OFFSET 0x0024 /* Configuration of DIO9 */ -#define TIVA_IOC_IOCFG10_OFFSET 0x0028 /* Configuration of DIO10 */ -#define TIVA_IOC_IOCFG11_OFFSET 0x002c /* Configuration of DIO11 */ -#define TIVA_IOC_IOCFG12_OFFSET 0x0030 /* Configuration of DIO12 */ -#define TIVA_IOC_IOCFG13_OFFSET 0x0034 /* Configuration of DIO13 */ -#define TIVA_IOC_IOCFG14_OFFSET 0x0038 /* Configuration of DIO14 */ -#define TIVA_IOC_IOCFG15_OFFSET 0x003c /* Configuration of DIO15 */ -#define TIVA_IOC_IOCFG16_OFFSET 0x0040 /* Configuration of DIO16 */ -#define TIVA_IOC_IOCFG17_OFFSET 0x0044 /* Configuration of DIO17 */ -#define TIVA_IOC_IOCFG18_OFFSET 0x0048 /* Configuration of DIO18 */ -#define TIVA_IOC_IOCFG19_OFFSET 0x004c /* Configuration of DIO19 */ -#define TIVA_IOC_IOCFG20_OFFSET 0x0050 /* Configuration of DIO20 */ -#define TIVA_IOC_IOCFG21_OFFSET 0x0054 /* Configuration of DIO21 */ -#define TIVA_IOC_IOCFG22_OFFSET 0x0058 /* Configuration of DIO22 */ -#define TIVA_IOC_IOCFG23_OFFSET 0x005c /* Configuration of DIO23 */ -#define TIVA_IOC_IOCFG24_OFFSET 0x0060 /* Configuration of DIO24 */ -#define TIVA_IOC_IOCFG25_OFFSET 0x0064 /* Configuration of DIO25 */ -#define TIVA_IOC_IOCFG26_OFFSET 0x0068 /* Configuration of DIO26 */ -#define TIVA_IOC_IOCFG27_OFFSET 0x006c /* Configuration of DIO27 */ -#define TIVA_IOC_IOCFG28_OFFSET 0x0070 /* Configuration of DIO28 */ -#define TIVA_IOC_IOCFG29_OFFSET 0x0074 /* Configuration of DIO29 */ -#define TIVA_IOC_IOCFG30_OFFSET 0x0078 /* Configuration of DIO30 */ -#define TIVA_IOC_IOCFG31_OFFSET 0x007c /* Configuration of DIO31 */ +# define TIVA_IOC_IOCFG0_OFFSET 0x0000 /* Configuration of DIO0 */ +# define TIVA_IOC_IOCFG1_OFFSET 0x0004 /* Configuration of DIO1 */ +# define TIVA_IOC_IOCFG2_OFFSET 0x0008 /* Configuration of DIO2 */ +# define TIVA_IOC_IOCFG3_OFFSET 0x000c /* Configuration of DIO3 */ +# define TIVA_IOC_IOCFG4_OFFSET 0x0010 /* Configuration of DIO4 */ +# define TIVA_IOC_IOCFG5_OFFSET 0x0014 /* Configuration of DIO5 */ +# define TIVA_IOC_IOCFG6_OFFSET 0x0018 /* Configuration of DIO6 */ +# define TIVA_IOC_IOCFG7_OFFSET 0x001c /* Configuration of DIO7 */ +# define TIVA_IOC_IOCFG8_OFFSET 0x0020 /* Configuration of DIO8 */ +# define TIVA_IOC_IOCFG9_OFFSET 0x0024 /* Configuration of DIO9 */ +# define TIVA_IOC_IOCFG10_OFFSET 0x0028 /* Configuration of DIO10 */ +# define TIVA_IOC_IOCFG11_OFFSET 0x002c /* Configuration of DIO11 */ +# define TIVA_IOC_IOCFG12_OFFSET 0x0030 /* Configuration of DIO12 */ +# define TIVA_IOC_IOCFG13_OFFSET 0x0034 /* Configuration of DIO13 */ +# define TIVA_IOC_IOCFG14_OFFSET 0x0038 /* Configuration of DIO14 */ +# define TIVA_IOC_IOCFG15_OFFSET 0x003c /* Configuration of DIO15 */ +# define TIVA_IOC_IOCFG16_OFFSET 0x0040 /* Configuration of DIO16 */ +# define TIVA_IOC_IOCFG17_OFFSET 0x0044 /* Configuration of DIO17 */ +# define TIVA_IOC_IOCFG18_OFFSET 0x0048 /* Configuration of DIO18 */ +# define TIVA_IOC_IOCFG19_OFFSET 0x004c /* Configuration of DIO19 */ +# define TIVA_IOC_IOCFG20_OFFSET 0x0050 /* Configuration of DIO20 */ +# define TIVA_IOC_IOCFG21_OFFSET 0x0054 /* Configuration of DIO21 */ +# define TIVA_IOC_IOCFG22_OFFSET 0x0058 /* Configuration of DIO22 */ +# define TIVA_IOC_IOCFG23_OFFSET 0x005c /* Configuration of DIO23 */ +# define TIVA_IOC_IOCFG24_OFFSET 0x0060 /* Configuration of DIO24 */ +# define TIVA_IOC_IOCFG25_OFFSET 0x0064 /* Configuration of DIO25 */ +# define TIVA_IOC_IOCFG26_OFFSET 0x0068 /* Configuration of DIO26 */ +# define TIVA_IOC_IOCFG27_OFFSET 0x006c /* Configuration of DIO27 */ +# define TIVA_IOC_IOCFG28_OFFSET 0x0070 /* Configuration of DIO28 */ +# define TIVA_IOC_IOCFG29_OFFSET 0x0074 /* Configuration of DIO29 */ +# define TIVA_IOC_IOCFG30_OFFSET 0x0078 /* Configuration of DIO30 */ +# define TIVA_IOC_IOCFG31_OFFSET 0x007c /* Configuration of DIO31 */ /* IOC register addresses **********************************************************/ -#define TIVA_IOC_IOCFG0 (TIVA_IOC_BASE + TIVA_IOC_IOCFG0_OFFSET) -#define TIVA_IOC_IOCFG1 (TIVA_IOC_BASE + TIVA_IOC_IOCFG1_OFFSET) -#define TIVA_IOC_IOCFG2 (TIVA_IOC_BASE + TIVA_IOC_IOCFG2_OFFSET) -#define TIVA_IOC_IOCFG3 (TIVA_IOC_BASE + TIVA_IOC_IOCFG3_OFFSET) -#define TIVA_IOC_IOCFG4 (TIVA_IOC_BASE + TIVA_IOC_IOCFG4_OFFSET) -#define TIVA_IOC_IOCFG5 (TIVA_IOC_BASE + TIVA_IOC_IOCFG5_OFFSET) -#define TIVA_IOC_IOCFG6 (TIVA_IOC_BASE + TIVA_IOC_IOCFG6_OFFSET) -#define TIVA_IOC_IOCFG7 (TIVA_IOC_BASE + TIVA_IOC_IOCFG7_OFFSET) -#define TIVA_IOC_IOCFG8 (TIVA_IOC_BASE + TIVA_IOC_IOCFG8_OFFSET) -#define TIVA_IOC_IOCFG9 (TIVA_IOC_BASE + TIVA_IOC_IOCFG9_OFFSET) -#define TIVA_IOC_IOCFG10 (TIVA_IOC_BASE + TIVA_IOC_IOCFG10_OFFSET) -#define TIVA_IOC_IOCFG11 (TIVA_IOC_BASE + TIVA_IOC_IOCFG11_OFFSET) -#define TIVA_IOC_IOCFG12 (TIVA_IOC_BASE + TIVA_IOC_IOCFG12_OFFSET) -#define TIVA_IOC_IOCFG13 (TIVA_IOC_BASE + TIVA_IOC_IOCFG13_OFFSET) -#define TIVA_IOC_IOCFG14 (TIVA_IOC_BASE + TIVA_IOC_IOCFG14_OFFSET) -#define TIVA_IOC_IOCFG15 (TIVA_IOC_BASE + TIVA_IOC_IOCFG15_OFFSET) -#define TIVA_IOC_IOCFG16 (TIVA_IOC_BASE + TIVA_IOC_IOCFG16_OFFSET) -#define TIVA_IOC_IOCFG17 (TIVA_IOC_BASE + TIVA_IOC_IOCFG17_OFFSET) -#define TIVA_IOC_IOCFG18 (TIVA_IOC_BASE + TIVA_IOC_IOCFG18_OFFSET) -#define TIVA_IOC_IOCFG19 (TIVA_IOC_BASE + TIVA_IOC_IOCFG19_OFFSET) -#define TIVA_IOC_IOCFG20 (TIVA_IOC_BASE + TIVA_IOC_IOCFG20_OFFSET) -#define TIVA_IOC_IOCFG21 (TIVA_IOC_BASE + TIVA_IOC_IOCFG21_OFFSET) -#define TIVA_IOC_IOCFG22 (TIVA_IOC_BASE + TIVA_IOC_IOCFG22_OFFSET) -#define TIVA_IOC_IOCFG23 (TIVA_IOC_BASE + TIVA_IOC_IOCFG23_OFFSET) -#define TIVA_IOC_IOCFG24 (TIVA_IOC_BASE + TIVA_IOC_IOCFG24_OFFSET) -#define TIVA_IOC_IOCFG25 (TIVA_IOC_BASE + TIVA_IOC_IOCFG25_OFFSET) -#define TIVA_IOC_IOCFG26 (TIVA_IOC_BASE + TIVA_IOC_IOCFG26_OFFSET) -#define TIVA_IOC_IOCFG27 (TIVA_IOC_BASE + TIVA_IOC_IOCFG27_OFFSET) -#define TIVA_IOC_IOCFG28 (TIVA_IOC_BASE + TIVA_IOC_IOCFG28_OFFSET) -#define TIVA_IOC_IOCFG29 (TIVA_IOC_BASE + TIVA_IOC_IOCFG29_OFFSET) -#define TIVA_IOC_IOCFG30 (TIVA_IOC_BASE + TIVA_IOC_IOCFG30_OFFSET) -#define TIVA_IOC_IOCFG31 (TIVA_IOC_BASE + TIVA_IOC_IOCFG31_OFFSET) +#define TIVA_IOC_IOCFG_(n) (TIVA_IOC_BASE + TIVA_IOC_IOCFG_OFFSET(n)) +# define TIVA_IOC_IOCFG0 (TIVA_IOC_BASE + TIVA_IOC_IOCFG0_OFFSET) +# define TIVA_IOC_IOCFG1 (TIVA_IOC_BASE + TIVA_IOC_IOCFG1_OFFSET) +# define TIVA_IOC_IOCFG2 (TIVA_IOC_BASE + TIVA_IOC_IOCFG2_OFFSET) +# define TIVA_IOC_IOCFG3 (TIVA_IOC_BASE + TIVA_IOC_IOCFG3_OFFSET) +# define TIVA_IOC_IOCFG4 (TIVA_IOC_BASE + TIVA_IOC_IOCFG4_OFFSET) +# define TIVA_IOC_IOCFG5 (TIVA_IOC_BASE + TIVA_IOC_IOCFG5_OFFSET) +# define TIVA_IOC_IOCFG6 (TIVA_IOC_BASE + TIVA_IOC_IOCFG6_OFFSET) +# define TIVA_IOC_IOCFG7 (TIVA_IOC_BASE + TIVA_IOC_IOCFG7_OFFSET) +# define TIVA_IOC_IOCFG8 (TIVA_IOC_BASE + TIVA_IOC_IOCFG8_OFFSET) +# define TIVA_IOC_IOCFG9 (TIVA_IOC_BASE + TIVA_IOC_IOCFG9_OFFSET) +# define TIVA_IOC_IOCFG10 (TIVA_IOC_BASE + TIVA_IOC_IOCFG10_OFFSET) +# define TIVA_IOC_IOCFG11 (TIVA_IOC_BASE + TIVA_IOC_IOCFG11_OFFSET) +# define TIVA_IOC_IOCFG12 (TIVA_IOC_BASE + TIVA_IOC_IOCFG12_OFFSET) +# define TIVA_IOC_IOCFG13 (TIVA_IOC_BASE + TIVA_IOC_IOCFG13_OFFSET) +# define TIVA_IOC_IOCFG14 (TIVA_IOC_BASE + TIVA_IOC_IOCFG14_OFFSET) +# define TIVA_IOC_IOCFG15 (TIVA_IOC_BASE + TIVA_IOC_IOCFG15_OFFSET) +# define TIVA_IOC_IOCFG16 (TIVA_IOC_BASE + TIVA_IOC_IOCFG16_OFFSET) +# define TIVA_IOC_IOCFG17 (TIVA_IOC_BASE + TIVA_IOC_IOCFG17_OFFSET) +# define TIVA_IOC_IOCFG18 (TIVA_IOC_BASE + TIVA_IOC_IOCFG18_OFFSET) +# define TIVA_IOC_IOCFG19 (TIVA_IOC_BASE + TIVA_IOC_IOCFG19_OFFSET) +# define TIVA_IOC_IOCFG20 (TIVA_IOC_BASE + TIVA_IOC_IOCFG20_OFFSET) +# define TIVA_IOC_IOCFG21 (TIVA_IOC_BASE + TIVA_IOC_IOCFG21_OFFSET) +# define TIVA_IOC_IOCFG22 (TIVA_IOC_BASE + TIVA_IOC_IOCFG22_OFFSET) +# define TIVA_IOC_IOCFG23 (TIVA_IOC_BASE + TIVA_IOC_IOCFG23_OFFSET) +# define TIVA_IOC_IOCFG24 (TIVA_IOC_BASE + TIVA_IOC_IOCFG24_OFFSET) +# define TIVA_IOC_IOCFG25 (TIVA_IOC_BASE + TIVA_IOC_IOCFG25_OFFSET) +# define TIVA_IOC_IOCFG26 (TIVA_IOC_BASE + TIVA_IOC_IOCFG26_OFFSET) +# define TIVA_IOC_IOCFG27 (TIVA_IOC_BASE + TIVA_IOC_IOCFG27_OFFSET) +# define TIVA_IOC_IOCFG28 (TIVA_IOC_BASE + TIVA_IOC_IOCFG28_OFFSET) +# define TIVA_IOC_IOCFG29 (TIVA_IOC_BASE + TIVA_IOC_IOCFG29_OFFSET) +# define TIVA_IOC_IOCFG30 (TIVA_IOC_BASE + TIVA_IOC_IOCFG30_OFFSET) +# define TIVA_IOC_IOCFG31 (TIVA_IOC_BASE + TIVA_IOC_IOCFG31_OFFSET) /* IOC register bit settings *******************************************************/ diff --git a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h index afb773af80..745ee5ebe5 100644 --- a/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h +++ b/arch/arm/src/tiva/hardware/cc13x2_cc26x2/cc13x2_cc26x2_ioc.h @@ -53,73 +53,74 @@ /* IOC register offsets ************************************************************/ #define TIVA_IOC_IOCFG_OFFSET(n) ((n) << 2) -#define TIVA_IOC_IOCFG0_OFFSET 0x0000 /* Configuration of DIO0 */ -#define TIVA_IOC_IOCFG1_OFFSET 0x0004 /* Configuration of DIO1 */ -#define TIVA_IOC_IOCFG2_OFFSET 0x0008 /* Configuration of DIO2 */ -#define TIVA_IOC_IOCFG3_OFFSET 0x000c /* Configuration of DIO3 */ -#define TIVA_IOC_IOCFG4_OFFSET 0x0010 /* Configuration of DIO4 */ -#define TIVA_IOC_IOCFG5_OFFSET 0x0014 /* Configuration of DIO5 */ -#define TIVA_IOC_IOCFG6_OFFSET 0x0018 /* Configuration of DIO6 */ -#define TIVA_IOC_IOCFG7_OFFSET 0x001c /* Configuration of DIO7 */ -#define TIVA_IOC_IOCFG8_OFFSET 0x0020 /* Configuration of DIO8 */ -#define TIVA_IOC_IOCFG9_OFFSET 0x0024 /* Configuration of DIO9 */ -#define TIVA_IOC_IOCFG10_OFFSET 0x0028 /* Configuration of DIO10 */ -#define TIVA_IOC_IOCFG11_OFFSET 0x002c /* Configuration of DIO11 */ -#define TIVA_IOC_IOCFG12_OFFSET 0x0030 /* Configuration of DIO12 */ -#define TIVA_IOC_IOCFG13_OFFSET 0x0034 /* Configuration of DIO13 */ -#define TIVA_IOC_IOCFG14_OFFSET 0x0038 /* Configuration of DIO14 */ -#define TIVA_IOC_IOCFG15_OFFSET 0x003c /* Configuration of DIO15 */ -#define TIVA_IOC_IOCFG16_OFFSET 0x0040 /* Configuration of DIO16 */ -#define TIVA_IOC_IOCFG17_OFFSET 0x0044 /* Configuration of DIO17 */ -#define TIVA_IOC_IOCFG18_OFFSET 0x0048 /* Configuration of DIO18 */ -#define TIVA_IOC_IOCFG19_OFFSET 0x004c /* Configuration of DIO19 */ -#define TIVA_IOC_IOCFG20_OFFSET 0x0050 /* Configuration of DIO20 */ -#define TIVA_IOC_IOCFG21_OFFSET 0x0054 /* Configuration of DIO21 */ -#define TIVA_IOC_IOCFG22_OFFSET 0x0058 /* Configuration of DIO22 */ -#define TIVA_IOC_IOCFG23_OFFSET 0x005c /* Configuration of DIO23 */ -#define TIVA_IOC_IOCFG24_OFFSET 0x0060 /* Configuration of DIO24 */ -#define TIVA_IOC_IOCFG25_OFFSET 0x0064 /* Configuration of DIO25 */ -#define TIVA_IOC_IOCFG26_OFFSET 0x0068 /* Configuration of DIO26 */ -#define TIVA_IOC_IOCFG27_OFFSET 0x006c /* Configuration of DIO27 */ -#define TIVA_IOC_IOCFG28_OFFSET 0x0070 /* Configuration of DIO28 */ -#define TIVA_IOC_IOCFG29_OFFSET 0x0074 /* Configuration of DIO29 */ -#define TIVA_IOC_IOCFG30_OFFSET 0x0078 /* Configuration of DIO30 */ -#define TIVA_IOC_IOCFG31_OFFSET 0x007c /* Configuration of DIO31 */ +# define TIVA_IOC_IOCFG0_OFFSET 0x0000 /* Configuration of DIO0 */ +# define TIVA_IOC_IOCFG1_OFFSET 0x0004 /* Configuration of DIO1 */ +# define TIVA_IOC_IOCFG2_OFFSET 0x0008 /* Configuration of DIO2 */ +# define TIVA_IOC_IOCFG3_OFFSET 0x000c /* Configuration of DIO3 */ +# define TIVA_IOC_IOCFG4_OFFSET 0x0010 /* Configuration of DIO4 */ +# define TIVA_IOC_IOCFG5_OFFSET 0x0014 /* Configuration of DIO5 */ +# define TIVA_IOC_IOCFG6_OFFSET 0x0018 /* Configuration of DIO6 */ +# define TIVA_IOC_IOCFG7_OFFSET 0x001c /* Configuration of DIO7 */ +# define TIVA_IOC_IOCFG8_OFFSET 0x0020 /* Configuration of DIO8 */ +# define TIVA_IOC_IOCFG9_OFFSET 0x0024 /* Configuration of DIO9 */ +# define TIVA_IOC_IOCFG10_OFFSET 0x0028 /* Configuration of DIO10 */ +# define TIVA_IOC_IOCFG11_OFFSET 0x002c /* Configuration of DIO11 */ +# define TIVA_IOC_IOCFG12_OFFSET 0x0030 /* Configuration of DIO12 */ +# define TIVA_IOC_IOCFG13_OFFSET 0x0034 /* Configuration of DIO13 */ +# define TIVA_IOC_IOCFG14_OFFSET 0x0038 /* Configuration of DIO14 */ +# define TIVA_IOC_IOCFG15_OFFSET 0x003c /* Configuration of DIO15 */ +# define TIVA_IOC_IOCFG16_OFFSET 0x0040 /* Configuration of DIO16 */ +# define TIVA_IOC_IOCFG17_OFFSET 0x0044 /* Configuration of DIO17 */ +# define TIVA_IOC_IOCFG18_OFFSET 0x0048 /* Configuration of DIO18 */ +# define TIVA_IOC_IOCFG19_OFFSET 0x004c /* Configuration of DIO19 */ +# define TIVA_IOC_IOCFG20_OFFSET 0x0050 /* Configuration of DIO20 */ +# define TIVA_IOC_IOCFG21_OFFSET 0x0054 /* Configuration of DIO21 */ +# define TIVA_IOC_IOCFG22_OFFSET 0x0058 /* Configuration of DIO22 */ +# define TIVA_IOC_IOCFG23_OFFSET 0x005c /* Configuration of DIO23 */ +# define TIVA_IOC_IOCFG24_OFFSET 0x0060 /* Configuration of DIO24 */ +# define TIVA_IOC_IOCFG25_OFFSET 0x0064 /* Configuration of DIO25 */ +# define TIVA_IOC_IOCFG26_OFFSET 0x0068 /* Configuration of DIO26 */ +# define TIVA_IOC_IOCFG27_OFFSET 0x006c /* Configuration of DIO27 */ +# define TIVA_IOC_IOCFG28_OFFSET 0x0070 /* Configuration of DIO28 */ +# define TIVA_IOC_IOCFG29_OFFSET 0x0074 /* Configuration of DIO29 */ +# define TIVA_IOC_IOCFG30_OFFSET 0x0078 /* Configuration of DIO30 */ +# define TIVA_IOC_IOCFG31_OFFSET 0x007c /* Configuration of DIO31 */ /* IOC register addresses **********************************************************/ -#define TIVA_IOC_IOCFG0 (TIVA_IOC_BASE + TIVA_IOC_IOCFG0_OFFSET) -#define TIVA_IOC_IOCFG1 (TIVA_IOC_BASE + TIVA_IOC_IOCFG1_OFFSET) -#define TIVA_IOC_IOCFG2 (TIVA_IOC_BASE + TIVA_IOC_IOCFG2_OFFSET) -#define TIVA_IOC_IOCFG3 (TIVA_IOC_BASE + TIVA_IOC_IOCFG3_OFFSET) -#define TIVA_IOC_IOCFG4 (TIVA_IOC_BASE + TIVA_IOC_IOCFG4_OFFSET) -#define TIVA_IOC_IOCFG5 (TIVA_IOC_BASE + TIVA_IOC_IOCFG5_OFFSET) -#define TIVA_IOC_IOCFG6 (TIVA_IOC_BASE + TIVA_IOC_IOCFG6_OFFSET) -#define TIVA_IOC_IOCFG7 (TIVA_IOC_BASE + TIVA_IOC_IOCFG7_OFFSET) -#define TIVA_IOC_IOCFG8 (TIVA_IOC_BASE + TIVA_IOC_IOCFG8_OFFSET) -#define TIVA_IOC_IOCFG9 (TIVA_IOC_BASE + TIVA_IOC_IOCFG9_OFFSET) -#define TIVA_IOC_IOCFG10 (TIVA_IOC_BASE + TIVA_IOC_IOCFG10_OFFSET) -#define TIVA_IOC_IOCFG11 (TIVA_IOC_BASE + TIVA_IOC_IOCFG11_OFFSET) -#define TIVA_IOC_IOCFG12 (TIVA_IOC_BASE + TIVA_IOC_IOCFG12_OFFSET) -#define TIVA_IOC_IOCFG13 (TIVA_IOC_BASE + TIVA_IOC_IOCFG13_OFFSET) -#define TIVA_IOC_IOCFG14 (TIVA_IOC_BASE + TIVA_IOC_IOCFG14_OFFSET) -#define TIVA_IOC_IOCFG15 (TIVA_IOC_BASE + TIVA_IOC_IOCFG15_OFFSET) -#define TIVA_IOC_IOCFG16 (TIVA_IOC_BASE + TIVA_IOC_IOCFG16_OFFSET) -#define TIVA_IOC_IOCFG17 (TIVA_IOC_BASE + TIVA_IOC_IOCFG17_OFFSET) -#define TIVA_IOC_IOCFG18 (TIVA_IOC_BASE + TIVA_IOC_IOCFG18_OFFSET) -#define TIVA_IOC_IOCFG19 (TIVA_IOC_BASE + TIVA_IOC_IOCFG19_OFFSET) -#define TIVA_IOC_IOCFG20 (TIVA_IOC_BASE + TIVA_IOC_IOCFG20_OFFSET) -#define TIVA_IOC_IOCFG21 (TIVA_IOC_BASE + TIVA_IOC_IOCFG21_OFFSET) -#define TIVA_IOC_IOCFG22 (TIVA_IOC_BASE + TIVA_IOC_IOCFG22_OFFSET) -#define TIVA_IOC_IOCFG23 (TIVA_IOC_BASE + TIVA_IOC_IOCFG23_OFFSET) -#define TIVA_IOC_IOCFG24 (TIVA_IOC_BASE + TIVA_IOC_IOCFG24_OFFSET) -#define TIVA_IOC_IOCFG25 (TIVA_IOC_BASE + TIVA_IOC_IOCFG25_OFFSET) -#define TIVA_IOC_IOCFG26 (TIVA_IOC_BASE + TIVA_IOC_IOCFG26_OFFSET) -#define TIVA_IOC_IOCFG27 (TIVA_IOC_BASE + TIVA_IOC_IOCFG27_OFFSET) -#define TIVA_IOC_IOCFG28 (TIVA_IOC_BASE + TIVA_IOC_IOCFG28_OFFSET) -#define TIVA_IOC_IOCFG29 (TIVA_IOC_BASE + TIVA_IOC_IOCFG29_OFFSET) -#define TIVA_IOC_IOCFG30 (TIVA_IOC_BASE + TIVA_IOC_IOCFG30_OFFSET) -#define TIVA_IOC_IOCFG31 (TIVA_IOC_BASE + TIVA_IOC_IOCFG31_OFFSET) +#define TIVA_IOC_IOCFG_(n) (TIVA_IOC_BASE + TIVA_IOC_IOCFG_OFFSET(n)) +# define TIVA_IOC_IOCFG0 (TIVA_IOC_BASE + TIVA_IOC_IOCFG0_OFFSET) +# define TIVA_IOC_IOCFG1 (TIVA_IOC_BASE + TIVA_IOC_IOCFG1_OFFSET) +# define TIVA_IOC_IOCFG2 (TIVA_IOC_BASE + TIVA_IOC_IOCFG2_OFFSET) +# define TIVA_IOC_IOCFG3 (TIVA_IOC_BASE + TIVA_IOC_IOCFG3_OFFSET) +# define TIVA_IOC_IOCFG4 (TIVA_IOC_BASE + TIVA_IOC_IOCFG4_OFFSET) +# define TIVA_IOC_IOCFG5 (TIVA_IOC_BASE + TIVA_IOC_IOCFG5_OFFSET) +# define TIVA_IOC_IOCFG6 (TIVA_IOC_BASE + TIVA_IOC_IOCFG6_OFFSET) +# define TIVA_IOC_IOCFG7 (TIVA_IOC_BASE + TIVA_IOC_IOCFG7_OFFSET) +# define TIVA_IOC_IOCFG8 (TIVA_IOC_BASE + TIVA_IOC_IOCFG8_OFFSET) +# define TIVA_IOC_IOCFG9 (TIVA_IOC_BASE + TIVA_IOC_IOCFG9_OFFSET) +# define TIVA_IOC_IOCFG10 (TIVA_IOC_BASE + TIVA_IOC_IOCFG10_OFFSET) +# define TIVA_IOC_IOCFG11 (TIVA_IOC_BASE + TIVA_IOC_IOCFG11_OFFSET) +# define TIVA_IOC_IOCFG12 (TIVA_IOC_BASE + TIVA_IOC_IOCFG12_OFFSET) +# define TIVA_IOC_IOCFG13 (TIVA_IOC_BASE + TIVA_IOC_IOCFG13_OFFSET) +# define TIVA_IOC_IOCFG14 (TIVA_IOC_BASE + TIVA_IOC_IOCFG14_OFFSET) +# define TIVA_IOC_IOCFG15 (TIVA_IOC_BASE + TIVA_IOC_IOCFG15_OFFSET) +# define TIVA_IOC_IOCFG16 (TIVA_IOC_BASE + TIVA_IOC_IOCFG16_OFFSET) +# define TIVA_IOC_IOCFG17 (TIVA_IOC_BASE + TIVA_IOC_IOCFG17_OFFSET) +# define TIVA_IOC_IOCFG18 (TIVA_IOC_BASE + TIVA_IOC_IOCFG18_OFFSET) +# define TIVA_IOC_IOCFG19 (TIVA_IOC_BASE + TIVA_IOC_IOCFG19_OFFSET) +# define TIVA_IOC_IOCFG20 (TIVA_IOC_BASE + TIVA_IOC_IOCFG20_OFFSET) +# define TIVA_IOC_IOCFG21 (TIVA_IOC_BASE + TIVA_IOC_IOCFG21_OFFSET) +# define TIVA_IOC_IOCFG22 (TIVA_IOC_BASE + TIVA_IOC_IOCFG22_OFFSET) +# define TIVA_IOC_IOCFG23 (TIVA_IOC_BASE + TIVA_IOC_IOCFG23_OFFSET) +# define TIVA_IOC_IOCFG24 (TIVA_IOC_BASE + TIVA_IOC_IOCFG24_OFFSET) +# define TIVA_IOC_IOCFG25 (TIVA_IOC_BASE + TIVA_IOC_IOCFG25_OFFSET) +# define TIVA_IOC_IOCFG26 (TIVA_IOC_BASE + TIVA_IOC_IOCFG26_OFFSET) +# define TIVA_IOC_IOCFG27 (TIVA_IOC_BASE + TIVA_IOC_IOCFG27_OFFSET) +# define TIVA_IOC_IOCFG28 (TIVA_IOC_BASE + TIVA_IOC_IOCFG28_OFFSET) +# define TIVA_IOC_IOCFG29 (TIVA_IOC_BASE + TIVA_IOC_IOCFG29_OFFSET) +# define TIVA_IOC_IOCFG30 (TIVA_IOC_BASE + TIVA_IOC_IOCFG30_OFFSET) +# define TIVA_IOC_IOCFG31 (TIVA_IOC_BASE + TIVA_IOC_IOCFG31_OFFSET) /* IOC register bit settings *******************************************************/ diff --git a/arch/arm/src/tiva/lm/lm3s_gpio.h b/arch/arm/src/tiva/lm/lm3s_gpio.h index 37b6be5523..bdd5b2f35c 100644 --- a/arch/arm/src/tiva/lm/lm3s_gpio.h +++ b/arch/arm/src/tiva/lm/lm3s_gpio.h @@ -122,7 +122,7 @@ # undef CONFIG_TIVA_GPIOQ_IRQS #endif -/* Bit-encoded input to tiva_configgpio() *******************************************/ +/* Bit-encoded input to tiva_configgpio() ***********************************/ /* Encoding: * @@ -238,4 +238,6 @@ * Public Function Prototypes ****************************************************************************/ +uintptr_t tiva_gpiobaseaddress(unsigned int port); + #endif /* __ARCH_ARM_SRC_TIVA_LM_LM3S_H */ diff --git a/arch/arm/src/tiva/lm/lmf4_gpio.h b/arch/arm/src/tiva/lm/lmf4_gpio.h index c09e329652..9b031ef84f 100644 --- a/arch/arm/src/tiva/lm/lmf4_gpio.h +++ b/arch/arm/src/tiva/lm/lmf4_gpio.h @@ -122,7 +122,7 @@ # undef CONFIG_TIVA_GPIOQ_IRQS #endif -/* Bit-encoded input to tiva_configgpio() *******************************************/ +/* Bit-encoded input to tiva_configgpio() ***********************************/ /* Encoding: * @@ -266,4 +266,6 @@ * Public Function Prototypes ****************************************************************************/ +uintptr_t tiva_gpiobaseaddress(unsigned int port); + #endif /* __ARCH_ARM_SRC_TIVA_LM_LM4F_H */ diff --git a/arch/arm/src/tiva/tm4c/tm4c_gpio.h b/arch/arm/src/tiva/tm4c/tm4c_gpio.h index 131f1554fd..35ef2c184f 100644 --- a/arch/arm/src/tiva/tm4c/tm4c_gpio.h +++ b/arch/arm/src/tiva/tm4c/tm4c_gpio.h @@ -152,7 +152,7 @@ # undef CONFIG_TIVA_GPIOQ_IRQS #endif -/* Bit-encoded input to tiva_configgpio() *******************************************/ +/* Bit-encoded input to tiva_configgpio() ***********************************/ /* Encoding: * @@ -296,4 +296,6 @@ * Public Function Prototypes ****************************************************************************/ +uintptr_t tiva_gpiobaseaddress(unsigned int port); + #endif /* __ARCH_ARM_SRC_TIVA_TIVA_GPIO_H */