arch/arm: correct the frame pointer register declare

In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code.
In AArch64, the frame pointer is stored in register X29.

Signed-off-by: chao.an <anchao@xiaomi.com>
This commit is contained in:
chao.an 2021-08-18 12:13:35 +08:00 committed by Xiang Xiao
parent 38bfadbeb9
commit 0a8d951837
6 changed files with 18 additions and 6 deletions

View File

@ -84,7 +84,11 @@
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#ifdef CONFIG_ARM_THUMB
#define REG_FP REG_R7
#else
#define REG_FP REG_R11
#endif /* CONFIG_ARM_THUMB */
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14

View File

@ -119,7 +119,7 @@
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#define REG_FP REG_R7
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14

View File

@ -183,7 +183,11 @@
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#ifdef CONFIG_ARM_THUMB
#define REG_FP REG_R7
#else
#define REG_FP REG_R11
#endif /* CONFIG_ARM_THUMB */
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14

View File

@ -75,7 +75,7 @@
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#define REG_FP REG_R7
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14

View File

@ -183,7 +183,11 @@
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#ifdef CONFIG_ARM_THUMB
#define REG_FP REG_R7
#else
#define REG_FP REG_R11
#endif /* CONFIG_ARM_THUMB */
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14

View File

@ -75,7 +75,7 @@
#define REG_V7 REG_R10
#define REG_SB REG_R9
#define REG_SL REG_R10
#define REG_FP REG_R11
#define REG_FP REG_R7
#define REG_IP REG_R12
#define REG_SP REG_R13
#define REG_LR REG_R14