From 0a8d9518379f6c296316d8382f0d650a1975703a Mon Sep 17 00:00:00 2001 From: "chao.an" Date: Wed, 18 Aug 2021 12:13:35 +0800 Subject: [PATCH] arch/arm: correct the frame pointer register declare In AArch32, the frame pointer is stored in register R11 for ARM code or register R7 for Thumb code. In AArch64, the frame pointer is stored in register X29. Signed-off-by: chao.an --- arch/arm/include/arm/irq.h | 6 +++++- arch/arm/include/armv6-m/irq.h | 2 +- arch/arm/include/armv7-a/irq.h | 6 +++++- arch/arm/include/armv7-m/irq.h | 2 +- arch/arm/include/armv7-r/irq.h | 6 +++++- arch/arm/include/armv8-m/irq.h | 2 +- 6 files changed, 18 insertions(+), 6 deletions(-) diff --git a/arch/arm/include/arm/irq.h b/arch/arm/include/arm/irq.h index 6c7f3aecc0..376288220e 100644 --- a/arch/arm/include/arm/irq.h +++ b/arch/arm/include/arm/irq.h @@ -84,7 +84,11 @@ #define REG_V7 REG_R10 #define REG_SB REG_R9 #define REG_SL REG_R10 -#define REG_FP REG_R11 +#ifdef CONFIG_ARM_THUMB + #define REG_FP REG_R7 +#else + #define REG_FP REG_R11 +#endif /* CONFIG_ARM_THUMB */ #define REG_IP REG_R12 #define REG_SP REG_R13 #define REG_LR REG_R14 diff --git a/arch/arm/include/armv6-m/irq.h b/arch/arm/include/armv6-m/irq.h index 9d23cc1527..104828b26c 100644 --- a/arch/arm/include/armv6-m/irq.h +++ b/arch/arm/include/armv6-m/irq.h @@ -119,7 +119,7 @@ #define REG_V7 REG_R10 #define REG_SB REG_R9 #define REG_SL REG_R10 -#define REG_FP REG_R11 +#define REG_FP REG_R7 #define REG_IP REG_R12 #define REG_SP REG_R13 #define REG_LR REG_R14 diff --git a/arch/arm/include/armv7-a/irq.h b/arch/arm/include/armv7-a/irq.h index c954408be2..7bbc7870cd 100644 --- a/arch/arm/include/armv7-a/irq.h +++ b/arch/arm/include/armv7-a/irq.h @@ -183,7 +183,11 @@ #define REG_V7 REG_R10 #define REG_SB REG_R9 #define REG_SL REG_R10 -#define REG_FP REG_R11 +#ifdef CONFIG_ARM_THUMB + #define REG_FP REG_R7 +#else + #define REG_FP REG_R11 +#endif /* CONFIG_ARM_THUMB */ #define REG_IP REG_R12 #define REG_SP REG_R13 #define REG_LR REG_R14 diff --git a/arch/arm/include/armv7-m/irq.h b/arch/arm/include/armv7-m/irq.h index 3ba7c7308a..96fd94c1f0 100644 --- a/arch/arm/include/armv7-m/irq.h +++ b/arch/arm/include/armv7-m/irq.h @@ -75,7 +75,7 @@ #define REG_V7 REG_R10 #define REG_SB REG_R9 #define REG_SL REG_R10 -#define REG_FP REG_R11 +#define REG_FP REG_R7 #define REG_IP REG_R12 #define REG_SP REG_R13 #define REG_LR REG_R14 diff --git a/arch/arm/include/armv7-r/irq.h b/arch/arm/include/armv7-r/irq.h index bf502a4a14..5acced1f55 100644 --- a/arch/arm/include/armv7-r/irq.h +++ b/arch/arm/include/armv7-r/irq.h @@ -183,7 +183,11 @@ #define REG_V7 REG_R10 #define REG_SB REG_R9 #define REG_SL REG_R10 -#define REG_FP REG_R11 +#ifdef CONFIG_ARM_THUMB + #define REG_FP REG_R7 +#else + #define REG_FP REG_R11 +#endif /* CONFIG_ARM_THUMB */ #define REG_IP REG_R12 #define REG_SP REG_R13 #define REG_LR REG_R14 diff --git a/arch/arm/include/armv8-m/irq.h b/arch/arm/include/armv8-m/irq.h index 8898f30ef3..a89de9078c 100644 --- a/arch/arm/include/armv8-m/irq.h +++ b/arch/arm/include/armv8-m/irq.h @@ -75,7 +75,7 @@ #define REG_V7 REG_R10 #define REG_SB REG_R9 #define REG_SL REG_R10 -#define REG_FP REG_R11 +#define REG_FP REG_R7 #define REG_IP REG_R12 #define REG_SP REG_R13 #define REG_LR REG_R14