TMS570: More GIO definitions
This commit is contained in:
Gregory Nutt
parent
2563663a45
commit
0a936e7fa7
@ -259,45 +259,156 @@
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/* Register Bit-Field Definitions *******************************************************************/
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/* GIO Global Control Register */
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#define GIO_GCR0_
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/* GIO Interrupt Detect Register */
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#define GIO_INTDET_
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/* GIO Interrupt Polarity Register */
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#define GIO_POL_
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/* GIO Interrupt Enable Set Register */
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#define GIO_ENASET_
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/* GIO Interrupt Enable Clear Register */
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#define GIO_ENACLR_
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/* GIO Interrupt Priority Set Register */
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#define GIO_LVLSET_
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/* GIO Interrupt Priority Clear Register */
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#define GIO_LVLCLR_
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/* GIO Interrupt Flag Register */
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#define GIO_FLG_
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/* GIO Offset 1 Register */
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#define GIO_OFF1_
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/* GIO Offset 2 Register */
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#define GIO_OFF2_
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/* GIO Emulation 1 Register */
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#define GIO_EMU1_
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/* GIO Emulation 2 Register */
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#define GIO_EMU2_
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/* GIO Data Direction Register */
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#define GIO_DIR_
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/* GIO Data Input Register */
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#define GIO_DIN_
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/* GIO Data Output Register */
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#define GIO_DOUT_
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/* GIO Data Set Register */
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#define GIO_DSET_
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/* GIO Data Clear Register */
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#define GIO_DCLR_
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/* GIO Open Drain Register */
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#define GIO_PDR_
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/* GIO Pull Disable Register */
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#define GIO_PULDIS_
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/* GIO Pull Select Register */
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#define GIO_PSL_
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#define GIO_GCR0_RESET (1 << 0) /* Bit 0: GIO reset */
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/* GIO Interrupt Detect Register */
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#define GIO_INTDET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt detection select for pins GIOA[7:0] */
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#define GIO_INTDET_GIOA_MASK (0xff << GIO_INTDET_GIOA_SHIFT)
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# define GIO_INTDET_GIOA_PIN(n) (1 << (GIO_INTDET_GIOA_SHIFT + (n)))
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#define GIO_INTDET_GIOB_SHIFT (8) /* Bits 8-15: Interrupt detection select for pins GIOB[7:0] */
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#define GIO_INTDET_GIOB_MASK (0xff << GIO_INTDET_GIOB_SHIFT)
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# define GIO_INTDET_GIOB_PIN(n) (1 << (GIO_INTDET_GIOB_SHIFT + (n)))
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#define GIO_INTDET_GIOC_SHIFT (16) /* Bits 16-23: Interrupt detection select for pins GIOC[7:0] */
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#define GIO_INTDET_GIOC_MASK (0xff << GIO_INTDET_GIOC_SHIFT)
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# define GIO_INTDET_GIOC_PIN(n) (1 << (GIO_INTDET_GIOC_SHIFT + (n)))
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#define GIO_INTDET_GIOD_SHIFT (24) /* Bits 24-31: Interrupt detection select for pins GIOD[7:0] */
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#define GIO_INTDET_GIOD_MASK (0xff << GIO_INTDET_GIOD_SHIFT)
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# define GIO_INTDET_GIOD_PIN(n) (1 << (GIO_INTDET_GIOD_SHIFT + (n)))
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/* GIO Interrupt Polarity Register */
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#define GIO_POL_GIOA_SHIFT (0) /* Bits 0-7: Interrupt polarity select for pins GIOA[7:0] */
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#define GIO_POL_GIOA_MASK (0xff << GIO_POL_GIOA_SHIFT)
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# define GIO_POL_GIOA_PIN(n) (1 << (GIO_POL_GIOA_SHIFT + (n)))
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#define GIO_POL_GIOB_SHIFT (8) /* Bits 8-15: Interrupt polarity select for pins GIOB[7:0] */
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#define GIO_POL_GIOB_MASK (0xff << GIO_POL_GIOB_SHIFT)
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# define GIO_POL_GIOB_PIN(n) (1 << (GIO_POL_GIOB_SHIFT + (n)))
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#define GIO_POL_GIOC_SHIFT (16) /* Bits 16-23: Interrupt polarity select for pins GIOC[7:0] */
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#define GIO_POL_GIOC_MASK (0xff << GIO_POL_GIOC_SHIFT)
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# define GIO_POL_GIOC_PIN(n) (1 << (GIO_POL_GIOC_SHIFT + (n)))
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#define GIO_POL_GIOD_SHIFT (24) /* Bits 24-31: Interrupt polarity select for pins GIOD[7:0] */
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#define GIO_POL_GIOD_MASK (0xff << GIO_POL_GIOD_SHIFT)
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# define GIO_POL_GIOD_PIN(n) (1 << (GIO_POL_GIOD_SHIFT + (n)))
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/* GIO Interrupt Enable Set Register */
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#define GIO_ENASET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt enable for pins GIOA[7:0] */
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#define GIO_ENASET_GIOA_MASK (0xff << GIO_ENASET_GIOA_SHIFT)
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# define GIO_ENASET_GIOA_PIN(n) (1 << (GIO_ENASET_GIOA_SHIFT + (n)))
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#define GIO_ENASET_GIOB_SHIFT (8) /* Bits 8-15: Interrupt enable for pins GIOB[7:0] */
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#define GIO_ENASET_GIOB_MASK (0xff << GIO_ENASET_GIOB_SHIFT)
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# define GIO_ENASET_GIOB_PIN(n) (1 << (GIO_ENASET_GIOB_SHIFT + (n)))
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#define GIO_ENASET_GIOC_SHIFT (16) /* Bits 16-23: Interrupt enable for pins GIOC[7:0] */
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#define GIO_ENASET_GIOC_MASK (0xff << GIO_ENASET_GIOC_SHIFT)
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# define GIO_ENASET_GIOC_PIN(n) (1 << (GIO_ENASET_GIOC_SHIFT + (n)))
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#define GIO_ENASET_GIOD_SHIFT (24) /* Bits 24-31: Interrupt enable for pins GIOD[7:0] */
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#define GIO_ENASET_GIOD_MASK (0xff << GIO_ENASET_GIOD_SHIFT)
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# define GIO_ENASET_GIOD_PIN(n) (1 << (GIO_ENASET_GIOD_SHIFT + (n)))
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/* GIO Interrupt Enable Clear Register */
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#define GIO_ENACLR_GIOA_SHIFT (0) /* Bits 0-7: Interrupt disable for pins GIOA[7:0] */
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#define GIO_ENACLR_GIOA_MASK (0xff << GIO_ENACLR_GIOA_SHIFT)
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# define GIO_ENACLR_GIOA_PIN(n) (1 << (GIO_ENACLR_GIOA_SHIFT + (n)))
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#define GIO_ENACLR_GIOB_SHIFT (8) /* Bits 8-15: Interrupt disable for pins GIOB[7:0] */
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#define GIO_ENACLR_GIOB_MASK (0xff << GIO_ENACLR_GIOB_SHIFT)
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# define GIO_ENACLR_GIOB_PIN(n) (1 << (GIO_ENACLR_GIOB_SHIFT + (n)))
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#define GIO_ENACLR_GIOC_SHIFT (16) /* Bits 16-23: Interrupt disable for pins GIOC[7:0] */
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#define GIO_ENACLR_GIOC_MASK (0xff << GIO_ENACLR_GIOC_SHIFT)
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# define GIO_ENACLR_GIOC_PIN(n) (1 << (GIO_ENACLR_GIOC_SHIFT + (n)))
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#define GIO_ENACLR_GIOD_SHIFT (24) /* Bits 24-31: Interrupt disable for pins GIOD[7:0] */
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#define GIO_ENACLR_GIOD_MASK (0xff << GIO_ENACLR_GIOD_SHIFT)
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# define GIO_ENACLR_GIOD_PIN(n) (1 << (GIO_ENACLR_GIOD_SHIFT + (n)))
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/* GIO Interrupt Priority Set Register */
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#define GIO_LVLSET_GIOA_SHIFT (0) /* Bits 0-7: Interrupt high level select for pins GIOA[7:0] */
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#define GIO_LVLSET_GIOA_MASK (0xff << GIO_LVLSET_GIOA_SHIFT)
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# define GIO_LVLSET_GIOA_PIN(n) (1 << (GIO_LVLSET_GIOA_SHIFT + (n)))
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#define GIO_LVLSET_GIOB_SHIFT (8) /* Bits 8-15: Interrupt high level select for pins GIOB[7:0] */
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#define GIO_LVLSET_GIOB_MASK (0xff << GIO_LVLSET_GIOB_SHIFT)
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# define GIO_LVLSET_GIOB_PIN(n) (1 << (GIO_LVLSET_GIOB_SHIFT + (n)))
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#define GIO_LVLSET_GIOC_SHIFT (16) /* Bits 16-23: Interrupt high level select for pins GIOC[7:0] */
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#define GIO_LVLSET_GIOC_MASK (0xff << GIO_LVLSET_GIOC_SHIFT)
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# define GIO_LVLSET_GIOC_PIN(n) (1 << (GIO_LVLSET_GIOC_SHIFT + (n)))
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#define GIO_LVLSET_GIOD_SHIFT (24) /* Bits 24-31: Interrupt high level select for pins GIOD[7:0] */
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#define GIO_LVLSET_GIOD_MASK (0xff << GIO_LVLSET_GIOD_SHIFT)
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# define GIO_LVLSET_GIOD_PIN(n) (1 << (GIO_LVLSET_GIOD_SHIFT + (n)))
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/* GIO Interrupt Priority Clear Register */
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#define GIO_LVLCLR_GIOA_SHIFT (0) /* Bits 0-7: Interrupt low level select for pins GIOA[7:0] */
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#define GIO_LVLCLR_GIOA_MASK (0xff << GIO_LVLCLR_GIOA_SHIFT)
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# define GIO_LVLCLR_GIOA_PIN(n) (1 << (GIO_LVLCLR_GIOA_SHIFT + (n)))
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#define GIO_LVLCLR_GIOB_SHIFT (8) /* Bits 8-15: Interrupt low level select for pins GIOB[7:0] */
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#define GIO_LVLCLR_GIOB_MASK (0xff << GIO_LVLCLR_GIOB_SHIFT)
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# define GIO_LVLCLR_GIOB_PIN(n) (1 << (GIO_LVLCLR_GIOB_SHIFT + (n)))
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#define GIO_LVLCLR_GIOC_SHIFT (16) /* Bits 16-23: Interrupt low level select for pins GIOC[7:0] */
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#define GIO_LVLCLR_GIOC_MASK (0xff << GIO_LVLCLR_GIOC_SHIFT)
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# define GIO_LVLCLR_GIOC_PIN(n) (1 << (GIO_LVLCLR_GIOC_SHIFT + (n)))
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#define GIO_LVLCLR_GIOD_SHIFT (24) /* Bits 24-31: Interrupt low level select for pins GIOD[7:0] */
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#define GIO_LVLCLR_GIOD_MASK (0xff << GIO_LVLCLR_GIOD_SHIFT)
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# define GIO_LVLCLR_GIOD_PIN(n) (1 << (GIO_LVLCLR_GIOD_SHIFT + (n)))
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/* GIO Interrupt Flag Register */
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#define GIO_FLG_GIOA_SHIFT (0) /* Bits 0-7: Interrupt flag for pins GIOA[7:0] */
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#define GIO_FLG_GIOA_MASK (0xff << GIO_FLG_GIOA_SHIFT)
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# define GIO_FLG_GIOA_PIN(n) (1 << (GIO_FLG_GIOA_SHIFT + (n)))
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#define GIO_FLG_GIOB_SHIFT (8) /* Bits 8-15: Interrupt flag for pins GIOB[7:0] */
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#define GIO_FLG_GIOB_MASK (0xff << GIO_FLG_GIOB_SHIFT)
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# define GIO_FLG_GIOB_PIN(n) (1 << (GIO_FLG_GIOB_SHIFT + (n)))
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#define GIO_FLG_GIOC_SHIFT (16) /* Bits 16-23: Interrupt flag for pins GIOC[7:0] */
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#define GIO_FLG_GIOC_MASK (0xff << GIO_FLG_GIOC_SHIFT)
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# define GIO_FLG_GIOC_PIN(n) (1 << (GIO_FLG_GIOC_SHIFT + (n)))
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#define GIO_FLG_GIOD_SHIFT (24) /* Bits 24-31: Interrupt flag for pins GIOD[7:0] */
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#define GIO_FLG_GIOD_MASK (0xff << GIO_FLG_GIOD_SHIFT)
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# define GIO_FLG_GIOD_PIN(n) (1 << (GIO_FLG_GIOD_SHIFT + (n)))
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/* GIO Offset 1/2 Register and GIO Emulation 1/2 Register */
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#define GIO_OFF_MASK (0x3f) /* Bits 0-5: GIO offset */
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# define GIO_OFF_NONE (0x00) /* No interrupt pending */
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# define GIO_OFF_GIOA0 (0x01) /* GIOA0 interrupt pending */
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# define GIO_OFF_GIOA1 (0x02) /* GIOA1 interrupt pending */
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# define GIO_OFF_GIOA2 (0x03) /* GIOA2 interrupt pending */
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# define GIO_OFF_GIOA3 (0x04) /* GIOA3 interrupt pending */
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# define GIO_OFF_GIOA4 (0x05) /* GIOA4 interrupt pending */
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# define GIO_OFF_GIOA5 (0x06) /* GIOA5 interrupt pending */
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# define GIO_OFF_GIOA6 (0x07) /* GIOA6 interrupt pending */
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# define GIO_OFF_GIOA7 (0x08) /* GIOA7 interrupt pending */
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# define GIO_OFF_GIOB0 (0x09) /* GIOB0 interrupt pending */
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# define GIO_OFF_GIOB1 (0x0a) /* GIOB1 interrupt pending */
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# define GIO_OFF_GIOB2 (0x0b) /* GIOB2 interrupt pending */
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# define GIO_OFF_GIOB3 (0x0c) /* GIOB3 interrupt pending */
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# define GIO_OFF_GIOB4 (0x0d) /* GIOB4 interrupt pending */
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# define GIO_OFF_GIOB5 (0x0e) /* GIOB5 interrupt pending */
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# define GIO_OFF_GIOB6 (0x0f) /* GIOB6 interrupt pending */
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# define GIO_OFF_GIOB7 (0x10) /* GIOB7 interrupt pending */
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# define GIO_OFF_GIOC0 (0x11) /* GIOC0 interrupt pending */
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# define GIO_OFF_GIOC1 (0x12) /* GIOC1 interrupt pending */
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# define GIO_OFF_GIOC2 (0x13) /* GIOC2 interrupt pending */
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# define GIO_OFF_GIOC3 (0x14) /* GIOC3 interrupt pending */
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# define GIO_OFF_GIOC4 (0x15) /* GIOC4 interrupt pending */
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# define GIO_OFF_GIOC5 (0x16) /* GIOC5 interrupt pending */
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# define GIO_OFF_GIOC6 (0x17) /* GIOC6 interrupt pending */
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# define GIO_OFF_GIOC7 (0x18) /* GIOC7 interrupt pending */
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# define GIO_OFF_GIOD0 (0x19) /* GIOD0 interrupt pending */
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# define GIO_OFF_GIOD1 (0x1a) /* GIOD1 interrupt pending */
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# define GIO_OFF_GIOD2 (0x1b) /* GIOD2 interrupt pending */
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# define GIO_OFF_GIOD3 (0x1c) /* GIOD3 interrupt pending */
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# define GIO_OFF_GIOD4 (0x1d) /* GIOD4 interrupt pending */
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# define GIO_OFF_GIOD5 (0x1e) /* GIOD5 interrupt pending */
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# define GIO_OFF_GIOD6 (0x1f) /* GIOD6 interrupt pending */
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# define GIO_OFF_GIOD7 (0x20) /* GIOD7 interrupt pending */
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/* GIO Data Direction Register, GIO Data Input Register, GIO Data Output Register,
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* GIO Data Set Register, GIO Data Clear Register, GIO Open Drain Register,
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* GIO Pull Disable Register, and GIO Pull Select Register
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*/
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#define GIO_PIN(n) (1 << (n)) /* Bit n: Corresponds to pin n */
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#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_GIO_H */
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325
arch/arm/src/tms570/tms570_gio.h
Normal file
325
arch/arm/src/tms570/tms570_gio.h
Normal file
@ -0,0 +1,325 @@
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/************************************************************************************
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* arch/arm/src/tms570/tms570_gio.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TMS570_TMS570_GIO_H
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#define __ARCH_ARM_SRC_TMS570_TMS570_GIO_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <assert.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Bit-encoded input to tms570_configgio() ********************************************/
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/* 32-bit Encoding:
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*
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* .... .... .... .... MCCC .IIV PPP. .BBB
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*/
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/* Input/Output mode:
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*
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* .... .... .... .... M... .... .... ....
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*/
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#define GIO_MODE_SHIFT (15) /* Bit 15: GIO mode */
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#define GIO_MODE_MASK (1 << GIO_MODE_SHIFT)
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# define GIO_INPUT (0 << GIO_MODE_SHIFT) /* GIO Input */
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# define GIO_OUTPUT (1 << GIO_MODE_SHIFT) /* GIO Output */
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/* These bits set the configuration of the pin:
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* NOTE: No definitions for parallel capture mode
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*
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* .... .... .... .... .CCC .... .... ....
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*/
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#define GIO_CFG_SHIFT (12) /* Bits 12-14: GIO configuration bits */
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#define GIO_CFG_MASK (7 << GIO_CFG_SHIFT)
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# define GIO_CFG_DEFAULT (0 << GIO_CFG_SHIFT) /* Default, no attribute */
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# define GIO_CFG_PULLUP (1 << GIO_CFG_SHIFT) /* Bit 16: Internal pull-up */
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# define GIO_CFG_PULLDOWN (2 << GIO_CFG_SHIFT) /* Bit 17: Internal pull-down */
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# define GIO_CFG_OPENDRAIN (4 << GIO_CFG_SHIFT) /* Bit 19: Open drain */
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/* Interrupt modes:
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*
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* .... .... .... .... .... .II. .... ....
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*/
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#define GIO_INT_SHIFT (9) /* Bits 9-10: GIO interrupt bits */
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#define GIO_INT_MASK (3 << GIO_INT_SHIFT)
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# define GIO_INT_NONE (0 << GIO_INT_SHIFT)
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# define GIO_INT_RISING (1 << GIO_INT_SHIFT)
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# define GIO_INT_FALLING (2 << GIO_INT_SHIFT)
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# define GIO_INT_BOTHEDGES (3 << GIO_INT_SHIFT)
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/* If the pin is an GIO output, then this identifies the initial output value:
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*
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* .... .... .... .... .... ...V .... ....
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*/
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#define GIO_OUTPUT_SET (1 << 8) /* Bit 8: Initial value of output */
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#define GIO_OUTPUT_CLEAR (0)
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/* This identifies the GIO port:
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*
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* .... .... .... .... .... .... PPP. ....
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*/
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#define GIO_PORT_SHIFT (5) /* Bit 5-7: Port number */
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#define GIO_PORT_MASK (7 << GIO_PORT_SHIFT)
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# define GIO_PORT_GIOA (0 << GIO_PORT_SHIFT)
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# define GIO_PORT_GIOB (1 << GIO_PORT_SHIFT)
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# define GIO_PORT_GIOC (2 << GIO_PORT_SHIFT)
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# define GIO_PORT_GIOD (3 << GIO_PORT_SHIFT)
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# define GIO_PORT_GIOE (4 << GIO_PORT_SHIFT)
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# define GIO_PORT_GIOF (5 << GIO_PORT_SHIFT)
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# define GIO_PORT_GIOG (6 << GIO_PORT_SHIFT)
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# define GIO_PORT_GIOH (7 << GIO_PORT_SHIFT)
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||||
/* This identifies the bit in the port:
|
||||
*
|
||||
* .... .... .... .... .... .... .... .BBB
|
||||
*/
|
||||
|
||||
#define GIO_PIN_SHIFT (0) /* Bits 0-2: GIO number: 0-7 */
|
||||
#define GIO_PIN_MASK (7 << GIO_PIN_SHIFT)
|
||||
# define GIO_PIN0 (0 << GIO_PIN_SHIFT)
|
||||
# define GIO_PIN1 (1 << GIO_PIN_SHIFT)
|
||||
# define GIO_PIN2 (2 << GIO_PIN_SHIFT)
|
||||
# define GIO_PIN3 (3 << GIO_PIN_SHIFT)
|
||||
# define GIO_PIN4 (4 << GIO_PIN_SHIFT)
|
||||
# define GIO_PIN5 (5 << GIO_PIN_SHIFT)
|
||||
# define GIO_PIN6 (6 << GIO_PIN_SHIFT)
|
||||
# define GIO_PIN7 (7 << GIO_PIN_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/* Must be big enough to hold the 32-bit encoding */
|
||||
|
||||
typedef uint16_t gio_pinset_t;
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tms570_gio_base
|
||||
*
|
||||
* Description:
|
||||
* Return the base address of the GIO register set
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uintptr_t tms570_gio_base(gio_pinset_t cfgset)
|
||||
{
|
||||
int port = (cfgset & GIO_PORT_MASK) >> GIO_PORT_SHIFT;
|
||||
return TMS570_GIO_PORTBASE(n);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tms570_gio_port
|
||||
*
|
||||
* Description:
|
||||
* Return the GIO port number
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int tms570_gio_port(gio_pinset_t cfgset)
|
||||
{
|
||||
return (cfgset & GIO_PORT_MASK) >> GIO_PORT_SHIFT;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tms570_gio_pin
|
||||
*
|
||||
* Description:
|
||||
* Return the GIO pin number
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int tms570_gio_pin(gio_pinset_t cfgset)
|
||||
{
|
||||
return (cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: tms570_gio_pinmask
|
||||
*
|
||||
* Description:
|
||||
* Return the GIO pin bit maskt
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline int tms570_gio_pinmask(gio_pinset_t cfgset)
|
||||
{
|
||||
return 1 << ((cfgset & GIO_PIN_MASK) >> GIO_PIN_SHIFT);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_gioirqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to support a second level of interrupt decoding for GIO pins.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_TMS570_GIO_IRQ
|
||||
void tms570_gioirqinitialize(void);
|
||||
#else
|
||||
# define tms570_gioirqinitialize()
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_configgio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int tms570_configgio(gio_pinset_t cfgset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_giowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void tms570_giowrite(gio_pinset_t pinset, bool value);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_gioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
bool tms570_gioread(gio_pinset_t pinset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_gioirq
|
||||
*
|
||||
* Description:
|
||||
* Configure an interrupt for the specified GIO pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_TMS570_GIO_IRQ
|
||||
void tms570_gioirq(gio_pinset_t pinset);
|
||||
#else
|
||||
# define tms570_gioirq(pinset)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_gioirqenable
|
||||
*
|
||||
* Description:
|
||||
* Enable the interrupt for specified GIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_TMS570_GIO_IRQ
|
||||
void tms570_gioirqenable(int irq);
|
||||
#else
|
||||
# define tms570_gioirqenable(irq)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: tms570_gioirqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the interrupt for specified GIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_TMS570_GIO_IRQ
|
||||
void tms570_gioirqdisable(int irq);
|
||||
#else
|
||||
# define tms570_gioirqdisable(irq)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Function: tms570_dumpgio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GIO registers associated with the base address of the provided pinset.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GIO
|
||||
int tms570_dumpgio(uint32_t pinset, const char *msg);
|
||||
#else
|
||||
# define tms570_dumpgio(p,m)
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_TMS570_TMS570_GIO_H */
|
||||
Loading…
Reference in New Issue
Block a user