diff --git a/arch/risc-v/src/esp32c3/esp32c3_resetcause.h b/arch/risc-v/src/esp32c3/esp32c3_resetcause.h
index b67c68a4b6..abc9ae908a 100644
--- a/arch/risc-v/src/esp32c3/esp32c3_resetcause.h
+++ b/arch/risc-v/src/esp32c3/esp32c3_resetcause.h
@@ -24,18 +24,24 @@
 
 enum esp32c3_resetcause_e
 {
-  ESP32C3_RESETCAUSE_SYS_CHIPPOR = 0x01,
-  ESP32C3_RESETCAUSE_SYS_RWDTSR  = 0x10,
-  ESP32C3_RESETCAUSE_SYS_BOR     = 0x0f,
-  ESP32C3_RESETCAUSE_CORE_SOFT   = 0x03,
-  ESP32C3_RESETCAUSE_CORE_DPSP   = 0x05,
-  ESP32C3_RESETCAUSE_CORE_MWDT0  = 0x07,
-  ESP32C3_RESETCAUSE_CORE_MWDT1  = 0x08,
-  ESP32C3_RESETCAUSE_CORE_RWDT   = 0x09,
-  ESP32C3_RESETCAUSE_CPU_MWDT0   = 0x0b,
-  ESP32C3_RESETCAUSE_CPU_SOFT    = 0x0c,
-  ESP32C3_RESETCAUSE_CPU_RWDT    = 0x0d,
-  ESP32C3_RESETCAUSE_CPU_PROCPU  = 0x0e
+  ESP32C3_RESETCAUSE_SYS_CHIPPOR    = 0x01,
+  ESP32C3_RESETCAUSE_SYS_BOR        = 0x0f,
+  ESP32C3_RESETCAUSE_SYS_RWDTSR     = 0x10,
+  ESP32C3_RESETCAUSE_SYS_SWD        = 0x12,
+  ESP32C3_RESETCAUSE_SYS_CLKGLITCH  = 0x13,
+  ESP32C3_RESETCAUSE_CORE_SOFT      = 0x03,
+  ESP32C3_RESETCAUSE_CORE_DPSP      = 0x05,
+  ESP32C3_RESETCAUSE_CORE_MWDT0     = 0x07,
+  ESP32C3_RESETCAUSE_CORE_MWDT1     = 0x08,
+  ESP32C3_RESETCAUSE_CORE_RWDT      = 0x09,
+  ESP32C3_RESETCAUSE_CORE_EFUSE     = 0x14,
+  ESP32C3_RESETCAUSE_CORE_USBUART   = 0x15,
+  ESP32C3_RESETCAUSE_CORE_USBJTAG   = 0x16,
+  ESP32C3_RESETCAUSE_CORE_PWRGLITCH = 0x17,
+  ESP32C3_RESETCAUSE_CPU_MWDT0      = 0x0b,
+  ESP32C3_RESETCAUSE_CPU_SOFT       = 0x0c,
+  ESP32C3_RESETCAUSE_CPU_RWDT       = 0x0d,
+  ESP32C3_RESETCAUSE_CPU_MWDT1      = 0x11
 };
 
 /****************************************************************************