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risc-v/esp32c3: Add the rest of the reset causes.

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Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2022-07-07 17:14:08 +02:00 committed by Xiang Xiao
parent 3daa18b661
commit 0bdf713df0
1 changed files with 18 additions and 12 deletions
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10
arch/risc-v/src/esp32c3/esp32c3_resetcause.h
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@ -25,17 +25,23 @@
enum esp32c3_resetcause_e enum esp32c3_resetcause_e
{ {
ESP32C3_RESETCAUSE_SYS_CHIPPOR = 0x01, ESP32C3_RESETCAUSE_SYS_CHIPPOR = 0x01,
ESP32C3_RESETCAUSE_SYS_RWDTSR = 0x10,
ESP32C3_RESETCAUSE_SYS_BOR = 0x0f, ESP32C3_RESETCAUSE_SYS_BOR = 0x0f,
ESP32C3_RESETCAUSE_SYS_RWDTSR = 0x10,
ESP32C3_RESETCAUSE_SYS_SWD = 0x12,
ESP32C3_RESETCAUSE_SYS_CLKGLITCH = 0x13,
ESP32C3_RESETCAUSE_CORE_SOFT = 0x03, ESP32C3_RESETCAUSE_CORE_SOFT = 0x03,
ESP32C3_RESETCAUSE_CORE_DPSP = 0x05, ESP32C3_RESETCAUSE_CORE_DPSP = 0x05,
ESP32C3_RESETCAUSE_CORE_MWDT0 = 0x07, ESP32C3_RESETCAUSE_CORE_MWDT0 = 0x07,
ESP32C3_RESETCAUSE_CORE_MWDT1 = 0x08, ESP32C3_RESETCAUSE_CORE_MWDT1 = 0x08,
ESP32C3_RESETCAUSE_CORE_RWDT = 0x09, ESP32C3_RESETCAUSE_CORE_RWDT = 0x09,
ESP32C3_RESETCAUSE_CORE_EFUSE = 0x14,
ESP32C3_RESETCAUSE_CORE_USBUART = 0x15,
ESP32C3_RESETCAUSE_CORE_USBJTAG = 0x16,
ESP32C3_RESETCAUSE_CORE_PWRGLITCH = 0x17,
ESP32C3_RESETCAUSE_CPU_MWDT0 = 0x0b, ESP32C3_RESETCAUSE_CPU_MWDT0 = 0x0b,
ESP32C3_RESETCAUSE_CPU_SOFT = 0x0c, ESP32C3_RESETCAUSE_CPU_SOFT = 0x0c,
ESP32C3_RESETCAUSE_CPU_RWDT = 0x0d, ESP32C3_RESETCAUSE_CPU_RWDT = 0x0d,
ESP32C3_RESETCAUSE_CPU_PROCPU = 0x0e ESP32C3_RESETCAUSE_CPU_MWDT1 = 0x11
}; };
/**************************************************************************** /****************************************************************************