arm/armv8-r: Adding a cache interface to armv8-r
Summary: 1. Add up_get_icache_size、up_get_dcache_size 2. Added L2 cahce PL310 implementation Signed-off-by: wangming9 <wangming9@xiaomi.com>
This commit is contained in:
wangming9
Xiang Xiao
parent
ddc6e31740
commit
0bfd4c5e0d
@ -90,3 +90,138 @@ config ARMV8R_FAST_INTERRUPT
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config ARMV8R_NONMASKABLE_FIQ
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bool "Enable Non-maskable FIQ Support at __start"
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default n
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config ARMV8R_HAVE_L2CC
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bool
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default n
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---help---
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Selected by the configuration tool if the architecture supports any
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kind of L2 cache.
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config ARMV8R_HAVE_L2CC_PL310
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bool
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default n
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select ARMV8R_HAVE_L2CC
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---help---
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Set by architecture-specific code if the hardware supports a PL310
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r3p2 L2 cache (only version r3p2 is supported).
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if ARMV8R_HAVE_L2CC
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menu "L2 Cache Configuration"
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config ARMV8R_L2CC_PL310
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bool "ARMv8-R L2CC P310 Support"
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default n
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depends on ARMV8R_HAVE_L2CC_PL310
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select ARCH_L2CACHE
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---help---
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Enable the 2 Cache Controller (L2CC) is based on the L2CC-PL310 ARM
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multi-way cache macrocell, version r3p2. The addition of an on-chip
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secondary cache, also referred to as a Level 2 or L2 cache, is a
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method of improving the system performance when significant memory
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traffic is generated by the processor.
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if ARCH_L2CACHE
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if ARMV8R_L2CC_PL310
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config PL310_LOCKDOWN_BY_MASTER
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bool "PL310 Lockdown by Master"
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default n
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config PL310_LOCKDOWN_BY_LINE
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bool "PL310 Lockdown by Line"
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default n
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config PL310_ADDRESS_FILTERING
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bool "PL310 Address Filtering by Line"
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default n
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config PL310_TRCR
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bool "PL310 TRCR set by usr"
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default n
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if PL310_TRCR
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config PL310_TRCR_TSETLAT
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int "PL310 TRCR setup latency"
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default 1
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config PL310_TRCR_TRDLAT
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int "PL310 TRCR read access latency"
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default 1
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config PL310_TRCR_TWRLAT
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int "PL310 TRCR write access latency"
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default 1
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endif # PL310_TRCR
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config PL310_DRCR
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bool "PL310 DRCR set by usr"
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default n
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if PL310_DRCR
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config PL310_DRCR_DSETLAT
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int "PL310 DRCR setup latency"
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default 1
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config PL310_DRCR_DRDLAT
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int "PL310 DRCR read access latency"
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default 1
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config PL310_DRCR_DWRLAT
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int "PL310 DRCR write access latency"
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default 1
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endif # PL310_DRCR
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endif # ARMV8R_L2CC_PL310
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choice
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prompt "L2 Cache Associativity"
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default ARMV8R_ASSOCIATIVITY_8WAY
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depends on ARCH_L2CACHE
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---help---
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This choice specifies the associativity of L2 cache in terms of the
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number of ways. This value could be obtained by querying cache
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configuration registers. However, by defining a configuration
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setting instead, we can avoid using RAM memory to hold information
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about properties of the memory.
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config ARMV8R_ASSOCIATIVITY_8WAY
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bool "8-Way Associativity"
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config ARMV8R_ASSOCIATIVITY_16WAY
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bool "16-Way Associativity"
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endchoice # L2 Cache Associativity
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choice
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prompt "L2 Cache Way Size"
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default ARMV8R_WAYSIZE_16KB
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depends on ARCH_L2CACHE
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---help---
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This choice specifies size of each way. This value can be obtained
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by querying cache configuration registers. However, by defining a
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configuration setting instead, we can avoid using RAM memory to hold
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information
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config ARMV8R_WAYSIZE_16KB
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bool "16 KiB"
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config ARMV8R_WAYSIZE_32KB
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bool "32 KiB"
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config ARMV8R_WAYSIZE_64KB
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bool "64 KiB"
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config ARMV8R_WAYSIZE_128KB
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bool "128 KiB"
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config ARMV8R_WAYSIZE_256KB
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bool "256 KiB"
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config ARMV8R_WAYSIZE_512KB
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bool "512 KiB"
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endchoice # L2 Cache Way Size
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endif # ARCH_L2CACHE
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endmenu # L2 Cache Configuration
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endif # ARMV8R_HAVE_L2CC
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@ -49,3 +49,6 @@ ifeq ($(CONFIG_ARCH_FPU),y)
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CMN_ASRCS += arm_fpuconfig.S
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endif
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ifeq ($(CONFIG_ARMV8R_L2CC_PL310),y)
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CMN_CSRCS += arm_l2cc_pl310.c
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endif
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@ -29,41 +29,12 @@
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#include "cp15_cacheops.h"
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#include "barriers.h"
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#include "l2cc.h"
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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#if defined(CONFIG_ARCH_ICACHE) || defined(CONFIG_ARCH_DCACHE)
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/****************************************************************************
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* Name: up_get_cache_linesize
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*
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* Description:
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* Get cache linesize
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Cache line size
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*
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****************************************************************************/
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static size_t up_get_cache_linesize(void)
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{
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static uint32_t clsize;
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if (clsize == 0)
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{
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clsize = MAX(cp15_cache_linesize(), l2cc_get_linesize());
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}
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return clsize;
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}
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -86,7 +57,40 @@ static size_t up_get_cache_linesize(void)
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size_t up_get_icache_linesize(void)
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{
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return up_get_cache_linesize();
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static uint32_t clsize;
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if (clsize == 0)
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{
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clsize = MAX(cp15_icache_linesize(), l2cc_linesize());
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}
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return clsize;
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}
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/****************************************************************************
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* Name: up_get_icache_size
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*
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* Description:
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* Get icache size
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Cache size
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*
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****************************************************************************/
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size_t up_get_icache_size(void)
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{
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static uint32_t csize;
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if (csize == 0)
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{
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csize = MAX(cp15_icache_size(), l2cc_size());
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}
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return csize;
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}
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/****************************************************************************
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@ -188,7 +192,40 @@ void up_disable_icache(void)
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size_t up_get_dcache_linesize(void)
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{
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return up_get_cache_linesize();
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static uint32_t clsize;
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if (clsize == 0)
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{
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clsize = MAX(cp15_dcache_linesize(), l2cc_linesize());
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}
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return clsize;
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}
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/****************************************************************************
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* Name: up_get_dcache_size
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*
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* Description:
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* Get dcache size
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* Cache size
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*
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****************************************************************************/
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size_t up_get_dcache_size(void)
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{
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static uint32_t csize;
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if (csize == 0)
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{
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csize = MAX(cp15_dcache_size(), l2cc_size());
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}
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return csize;
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}
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/****************************************************************************
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@ -216,6 +253,7 @@ size_t up_get_dcache_linesize(void)
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void up_invalidate_dcache(uintptr_t start, uintptr_t end)
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{
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cp15_invalidate_dcache(start, end);
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l2cc_invalidate(start, end);
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}
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/****************************************************************************
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@ -240,6 +278,7 @@ void up_invalidate_dcache_all(void)
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#ifdef CONFIG_ARCH_L2CACHE
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irqstate_t flags = enter_critical_section();
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cp15_invalidate_dcache_all();
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l2cc_invalidate_all();
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leave_critical_section(flags);
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#else
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cp15_invalidate_dcache_all();
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893
arch/arm/src/armv8-r/arm_l2cc_pl310.c
Normal file
893
arch/arm/src/armv8-r/arm_l2cc_pl310.c
Normal file
@ -0,0 +1,893 @@
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/****************************************************************************
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* arch/arm/src/armv8-r/arm_l2cc_pl310.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
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* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
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*
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* NOTE: This logic is incompatible with older versions of the PL310!
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <sys/param.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/irq.h>
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#include "arm_internal.h"
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#include "barriers.h"
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#include "l2cc.h"
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#include "l2cc_pl310.h"
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#ifdef CONFIG_ARMV8R_L2CC_PL310
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Number of ways depends on ARM configuration */
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#if defined(CONFIG_ARMV8R_ASSOCIATIVITY_8WAY)
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# define PL310_NWAYS 8
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# define PL310_WAY_MASK 0x000000ff
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#elif defined(CONFIG_ARMV8R_ASSOCIATIVITY_16WAY)
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# define PL310_NWAYS 16
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# define PL310_WAY_MASK 0x0000ffff
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#else
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# error "Number of ways not selected"
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#endif
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/* The size of one depends on ARM configuration */
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#if defined(CONFIG_ARMV8R_WAYSIZE_16KB)
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# define PL310_WAYSIZE (16 * 1024)
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#elif defined(CONFIG_ARMV8R_WAYSIZE_32KB)
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# define PL310_WAYSIZE (32 * 1024)
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#elif defined(CONFIG_ARMV8R_WAYSIZE_64KB)
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# define PL310_WAYSIZE (64 * 1024)
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#elif defined(CONFIG_ARMV8R_WAYSIZE_128KB)
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# define PL310_WAYSIZE (128 * 1024)
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#elif defined(CONFIG_ARMV8R_WAYSIZE_256KB)
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# define PL310_WAYSIZE (256 * 1024)
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#elif defined(CONFIG_ARMV8R_WAYSIZE_512KB)
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# define PL310_WAYSIZE (512 * 1024)
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#else
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# error "Way size not selected"
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#endif
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/* The size of the cache is then the product of the number of ways times
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* the size of each way.
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*/
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#define PL310_CACHE_SIZE (PL310_NWAYS * PL310_WAYSIZE)
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/* Use for aligning addresses to a cache line boundary */
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#define PL310_CACHE_LINE_MASK (PL310_CACHE_LINE_SIZE - 1)
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/* Configurable options
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*
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* REVISIT: Currently there are not configuration options. All values
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* are just set to the default.
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*/
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/* Bit 0: Full line zero enable
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*
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* Default: 0=Full line of write zero behavior disabled
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*/
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#define L2CC_ACR_FLZE_CONFIG (0) /* 0=Full line of write zero behavior disabled */
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/* Bit 10: High Priority for SO and Dev Reads Enable
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*
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* Default: 0=Strongly Ordered and Device reads have lower priority than
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* cacheable accesses
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*/
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#define L2CC_ACR_HPSO_CONFIG (0) /* 0=Have lower priority than cache */
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/* Bit 11: Store Buffer Device Limitation Enable
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*
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* Default: 0=Store buffer device limitation disabled
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*/
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#define L2CC_ACR_SBDLE_CONFIG (0) /* 0=Store buffer device limitation disabled */
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/* Bit 12: Exclusive Cache Configuration
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*
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* Default: 0=Disabled
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*/
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#define L2CC_ACR_EXCC_CONFIG (0) /* 0=Disabled */
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/* Bit 13: Shared Attribute Invalidate Enable
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*
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* Default: 0=Shared invalidate behavior disabled
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*/
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#define L2CC_ACR_SAIE_CONFIG (0) /* 0=Shared invalidate behavior disabled */
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/* Bit 20: Event Monitor Bus Enable
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*
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* Default: 0=Disabled
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*/
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#define L2CC_ACR_EMBEN_CONFIG (0) /* 0=Disabled */
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/* Bit 21: Parity Enable
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*
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* Default: 0=Disabled
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*/
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#define L2CC_ACR_PEN_CONFIG (0) /* 0=Disabled */
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/* Bit 22: Shared Attribute Override Enable
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*
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* Default: 0=Treats shared accesses as specified in the TRM
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*/
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#define L2CC_ACR_SAOEN_CONFIG (0) /* 0=As specified in the TRM */
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/* Bits 23-24: Force Write Allocate
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*
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* Default: 0=Use AWCACHE attributes for WA
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*/
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#define L2CC_ACR_FWA_CONFIG L2CC_ACR_FWA_AWCACHE /* Use AWCACHE attributes for WA */
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/* Bit 25: Cache Replacement Policy
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*
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* Default: 1=Round robin replacement policy
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*/
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#define L2CC_ACR_CRPOL_CONFIG L2CC_ACR_CRPOL /* 1=Round robin replacement policy */
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/* Bit 26: Non-Secure Lockdown Enable
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*
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* Default: 0=Lockdown registers cannot be modified using non-secure accesses
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*/
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#define L2CC_ACR_NSLEN_CONFIG (0) /* 0=Secure access only */
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/* Bit 27: Non-Secure Interrupt Access Control
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*
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* Default: 0=Interrupt Clear and Mask can only be modified or read with
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* secure accesses
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*/
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#define L2CC_ACR_NSIAC_CONFIG (0) /* 0=Secure access only */
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/* Bit 28: Data Prefetch Enable
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*
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* Default: 0=Data prefetching disabled
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*/
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#define L2CC_ACR_DPEN_CONFIG (0) /* 0=Data prefetching disabled */
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/* Bit 29: Instruction Prefetch Enable
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*
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* Default: 0=Instruction prefetching disabled
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*/
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#define L2CC_ACR_IPEN_CONFIG (0) /* 0=Instruction prefetching disabled */
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/* Bit 30: Early BRESP enable
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*
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* Default: 0=Early BRESP disabled
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*/
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#define L2CC_ACR_EBRESP_CONFIG (0) /* 0=Early BRESP disabled */
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#define L2CC_ACR_CONFIG \
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(L2CC_ACR_FLZE_CONFIG | L2CC_ACR_HPSO_CONFIG | L2CC_ACR_SBDLE_CONFIG | \
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L2CC_ACR_EXCC_CONFIG | L2CC_ACR_SAIE_CONFIG | L2CC_ACR_EMBEN_CONFIG | \
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L2CC_ACR_PEN_CONFIG | L2CC_ACR_SAOEN_CONFIG | L2CC_ACR_FWA_CONFIG | \
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L2CC_ACR_CRPOL_CONFIG | L2CC_ACR_NSLEN_CONFIG | L2CC_ACR_NSIAC_CONFIG | \
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L2CC_ACR_DPEN_CONFIG | L2CC_ACR_IPEN_CONFIG | L2CC_ACR_EBRESP_CONFIG)
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#define L2CC_ACR_ALLCONFIGS (0x7f303c01)
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#define L2CC_ACR_CONFIGMASK (L2CC_ACR_SBZ | L2CC_ACR_ALLCONFIGS)
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/* Filter end address */
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#define CONFIG_PL310_FLEND (CONFIG_PL310_FLSTRT + CONFIG_PL310_FLSIZE)
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/* Block size. Used to break up long operations so that interrupts are not
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* disabled for a long time.
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*/
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|
||||
#define PL310_GULP_SIZE 4096
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pl310_flush_all
|
||||
*
|
||||
* Description:
|
||||
* Flush all ways using the Clean Invalidate Way Register (CIWR).
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void pl310_flush_all(void)
|
||||
{
|
||||
/* Flush all ways by writing the set of ways to be cleaned to the Clean
|
||||
* Invalidate Way Register (CIWR).
|
||||
*/
|
||||
|
||||
putreg32(PL310_WAY_MASK, L2CC_CIWR);
|
||||
|
||||
/* Wait for cache operation by way to complete */
|
||||
|
||||
while ((getreg32(L2CC_CIWR) & PL310_WAY_MASK) != 0);
|
||||
|
||||
/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
|
||||
* EB, are empty.
|
||||
*/
|
||||
|
||||
putreg32(0, L2CC_CSR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_l2ccinitialize
|
||||
*
|
||||
* Description:
|
||||
* One time configuration of the L2 cache. The L2 cache will be enabled
|
||||
* upon return.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None. The L2 cache configuration is controlled by configuration
|
||||
* settings.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_l2ccinitialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
int i;
|
||||
|
||||
/* Make sure that this is a PL310 cache, version r3p2.
|
||||
*
|
||||
* REVISIT: The SAMA5D4 is supposed to report its ID as 0x410000C8 which
|
||||
* is r3p2, but the chip that I have actually* reports 0x410000C9 which
|
||||
* is some later revision.
|
||||
*/
|
||||
|
||||
/* DEBUGASSERT((getreg32(L2CC_IDR) & L2CC_IDR_REV_MASK) ==
|
||||
* L2CC_IDR_REV_R3P2);
|
||||
*/
|
||||
|
||||
/* Make sure that actual cache configuration agrees with the configured
|
||||
* cache configuration.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARMV8R_ASSOCIATIVITY_8WAY)
|
||||
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == 0);
|
||||
#elif defined(CONFIG_ARMV8R_ASSOCIATIVITY_16WAY)
|
||||
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_ASS) == L2CC_ACR_ASS);
|
||||
#else
|
||||
# error No associativity selected
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARMV8R_WAYSIZE_16KB)
|
||||
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
|
||||
L2CC_ACR_WAYSIZE_16KB);
|
||||
#elif defined(CONFIG_ARMV8R_WAYSIZE_32KB)
|
||||
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
|
||||
L2CC_ACR_WAYSIZE_32KB);
|
||||
#elif defined(CONFIG_ARMV8R_WAYSIZE_64KB)
|
||||
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
|
||||
L2CC_ACR_WAYSIZE_64KB);
|
||||
#elif defined(CONFIG_ARMV8R_WAYSIZE_128KB)
|
||||
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
|
||||
L2CC_ACR_WAYSIZE_128KB);
|
||||
#elif defined(CONFIG_ARMV8R_WAYSIZE_256KB)
|
||||
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
|
||||
L2CC_ACR_WAYSIZE_256KB);
|
||||
#elif defined(CONFIG_ARMV8R_WAYSIZE_512KB)
|
||||
DEBUGASSERT((getreg32(L2CC_ACR) & L2CC_ACR_WAYSIZE_MASK) ==
|
||||
L2CC_ACR_WAYSIZE_512KB);
|
||||
#else
|
||||
# error No way size selected
|
||||
#endif
|
||||
|
||||
/* L2 configuration can only be changed if the cache is disabled,
|
||||
*
|
||||
* NOTE: This register access will fail if we are not in secure more.
|
||||
*/
|
||||
|
||||
if ((getreg32(L2CC_CR) & L2CC_CR_L2CEN) == 0)
|
||||
{
|
||||
#if defined(CONFIG_PL310_TRCR_TSETLAT) && defined(CONFIG_PL310_TRCR_TRDLAT) && \
|
||||
defined(CONFIG_PL310_TRCR_TWRLAT)
|
||||
/* Configure Tag RAM control */
|
||||
|
||||
regval = ((CONFIG_PL310_TRCR_TSETLAT - 1) << L2CC_TRCR_TSETLAT_SHIFT) |
|
||||
((CONFIG_PL310_TRCR_TRDLAT - 1) << L2CC_TRCR_TRDLAT_SHIFT) |
|
||||
((CONFIG_PL310_TRCR_TWRLAT - 1) << L2CC_TRCR_TWRLAT_SHIFT);
|
||||
putreg32(regval, L2CC_TRCR);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PL310_DRCR_DSETLAT) && defined(CONFIG_PL310_DRCR_DRDLAT) && \
|
||||
defined(CONFIG_PL310_DRCR_DWRLAT)
|
||||
/* Configure Data RAM control */
|
||||
|
||||
regval = ((CONFIG_PL310_DRCR_DSETLAT - 1) << L2CC_DRCR_DSETLAT_SHIFT) |
|
||||
((CONFIG_PL310_DRCR_DRDLAT - 1) << L2CC_DRCR_DRDLAT_SHIFT) |
|
||||
((CONFIG_PL310_DRCR_DWRLAT - 1) << L2CC_DRCR_DWRLAT_SHIFT);
|
||||
putreg32(regval, L2CC_DRCR);
|
||||
#endif
|
||||
|
||||
#ifdef PL310_ADDRESS_FILTERING
|
||||
#if defined(CONFIG_PL310_FLSTRT) && defined(CONFIG_PL310_FLSIZE)
|
||||
/* Configure the address filter */
|
||||
|
||||
regval = (CONFIG_PL310_FLEND + ~L2CC_FLEND_MASK) & L2CC_FLEND_MASK;
|
||||
putreg32(regval, L2CC_FLEND);
|
||||
|
||||
regval = (CONFIG_PL310_FLSTRT & L2CC_FLSTRT_MASK) | L2CC_FLSTRT_ENABLE;
|
||||
putreg32(regval | L2X0_ADDR_FILTER_EN, L2CC_FLSTRT);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Make sure that the memory is not locked down */
|
||||
|
||||
for (i = 0; i < PL310_NLOCKREGS; i++)
|
||||
{
|
||||
putreg32(0, L2CC_DLKR(i));
|
||||
putreg32(0, L2CC_ILKR(i));
|
||||
}
|
||||
|
||||
/* Configure the cache properties */
|
||||
|
||||
regval = getreg32(L2CC_ACR);
|
||||
regval &= ~L2CC_ACR_CONFIGMASK;
|
||||
regval |= L2CC_ACR_CONFIG;
|
||||
putreg32(regval, L2CC_ACR);
|
||||
|
||||
/* Invalidate and enable the cache */
|
||||
|
||||
l2cc_invalidate_all();
|
||||
putreg32(L2CC_CR_L2CEN, L2CC_CR);
|
||||
ARM_DSB();
|
||||
ARM_ISB();
|
||||
}
|
||||
|
||||
sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
|
||||
PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_linesize
|
||||
*
|
||||
* Description:
|
||||
* Get L2CC-P310 L2 cache linesize
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* L2 cache linesize
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t l2cc_linesize(void)
|
||||
{
|
||||
return PL310_CACHE_LINE_SIZE;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_size
|
||||
*
|
||||
* Description:
|
||||
* Get L2CC-P310 L2 cache size
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* L2 cache size
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t l2cc_size(void)
|
||||
{
|
||||
return PL310_CACHE_SIZE;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_enable
|
||||
*
|
||||
* Description:
|
||||
* Re-enable the L2CC-P310 L2 cache by setting the enable bit in the
|
||||
* Control Register (CR)
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_enable(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
/* Invalidate and enable the cache (must be disabled to do this!) */
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
if ((getreg32(L2CC_CR) & L2CC_CR_L2CEN) != 0)
|
||||
{
|
||||
l2cc_disable();
|
||||
}
|
||||
|
||||
l2cc_invalidate_all();
|
||||
putreg32(L2CC_CR_L2CEN, L2CC_CR);
|
||||
ARM_DSB();
|
||||
ARM_ISB();
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_disable
|
||||
*
|
||||
* Description:
|
||||
* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR)
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_disable(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
/* Flush all ways using the Clean Invalidate Way Register (CIWR). */
|
||||
|
||||
flags = enter_critical_section();
|
||||
pl310_flush_all();
|
||||
|
||||
/* Disable the L2CC-P310 L2 cache by clearing the Control Register (CR) */
|
||||
|
||||
putreg32(0, L2CC_CR);
|
||||
ARM_DSB();
|
||||
ARM_ISB();
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_sync
|
||||
*
|
||||
* Description:
|
||||
* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
|
||||
* EB, are empty.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_sync(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
|
||||
* EB, are empty.
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
putreg32(0, L2CC_CSR);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_invalidate_all
|
||||
*
|
||||
* Description:
|
||||
* Invalidate all ways using the Invalidate Way Register (IWR).
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_invalidate_all(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
/* Invalidate all ways */
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Invalidate all ways by writing the bit mask of ways to be invalidated
|
||||
* the Invalidate Way Register (IWR).
|
||||
*/
|
||||
|
||||
putreg32(PL310_WAY_MASK, L2CC_IWR);
|
||||
|
||||
/* Wait for cache operation by way to complete */
|
||||
|
||||
while ((getreg32(L2CC_IWR) & PL310_WAY_MASK) != 0);
|
||||
|
||||
/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
|
||||
* EB, are empty.
|
||||
*/
|
||||
|
||||
putreg32(0, L2CC_CSR);
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_invalidate
|
||||
*
|
||||
* Description:
|
||||
* Invalidate a range of addresses by writing to the Invalidate Physical
|
||||
* Address Line Register (IPALR) repeatedly.
|
||||
*
|
||||
* Input Parameters:
|
||||
* startaddr - The first address to be invalidated
|
||||
* endaddr - The last address to be invalidated
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_invalidate(uintptr_t startaddr, uintptr_t endaddr)
|
||||
{
|
||||
uintptr_t invalsize;
|
||||
uintptr_t gulpend;
|
||||
irqstate_t flags;
|
||||
|
||||
/* Check if the start address is aligned with a cacheline */
|
||||
|
||||
flags = enter_critical_section();
|
||||
if ((startaddr & PL310_CACHE_LINE_MASK) != 0)
|
||||
{
|
||||
/* No.. align down and flush the cache line by writing the address to
|
||||
* the Clean Invalidate Physical Address Line Register (CIPALR).
|
||||
*/
|
||||
|
||||
startaddr &= ~PL310_CACHE_LINE_MASK;
|
||||
putreg32(startaddr, L2CC_CIPALR);
|
||||
|
||||
/* Then start invalidating at the next cache line */
|
||||
|
||||
startaddr += PL310_CACHE_LINE_SIZE;
|
||||
}
|
||||
|
||||
/* Check if the end address is aligned with a cache line */
|
||||
|
||||
if ((endaddr & PL310_CACHE_LINE_MASK) != 0)
|
||||
{
|
||||
/* No.. align down and flush cache line by writing the address to
|
||||
* the Clean Invalidate Physical Address Line Register (CIPALR).
|
||||
*/
|
||||
|
||||
endaddr &= ~PL310_CACHE_LINE_MASK;
|
||||
putreg32(endaddr, L2CC_CIPALR);
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
|
||||
/* Loop, invalidated the address range by cache line. Interrupts are re-
|
||||
* enabled momentarily every PL310_GULP_SIZE bytes.
|
||||
*/
|
||||
|
||||
while (startaddr < endaddr)
|
||||
{
|
||||
/* Get the size of the next gulp of cache lines to invalidate. We do
|
||||
* this in small chunks so that we do not have to keep interrupts
|
||||
* disabled throughout the whole flush.
|
||||
*/
|
||||
|
||||
invalsize = endaddr - startaddr;
|
||||
gulpend = startaddr + MIN(invalsize, PL310_GULP_SIZE);
|
||||
|
||||
/* Disable interrupts and invalidate the gulp */
|
||||
|
||||
flags = enter_critical_section();
|
||||
while (startaddr < gulpend)
|
||||
{
|
||||
/* Invalidate the cache line by writing the address to the
|
||||
* Invalidate Physical Address Line Register (IPALR).
|
||||
*/
|
||||
|
||||
putreg32(startaddr, L2CC_IPALR);
|
||||
|
||||
/* Start of the next cache line */
|
||||
|
||||
startaddr += PL310_CACHE_LINE_SIZE;
|
||||
}
|
||||
|
||||
/* Enable interrupts momentarily */
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
|
||||
* EB, are empty.
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
putreg32(0, L2CC_CSR);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_clean_all
|
||||
*
|
||||
* Description:
|
||||
* Clean all ways by using the Clean Ways Register (CWR).
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_clean_all(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
/* Clean all ways by writing the set of ways to be cleaned to the Clean
|
||||
* Ways Register (CWR).
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
putreg32(PL310_WAY_MASK, L2CC_CWR);
|
||||
|
||||
/* Wait for cache operation by way to complete */
|
||||
|
||||
while ((getreg32(L2CC_CWR) & PL310_WAY_MASK) != 0);
|
||||
|
||||
/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
|
||||
* EB, are empty.
|
||||
*/
|
||||
|
||||
putreg32(0, L2CC_CSR);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_clean
|
||||
*
|
||||
* Description:
|
||||
* Clean the cache line over a range of addresses uing the Clean Physical
|
||||
* Address Line Register (CPALR) repeatedly.
|
||||
*
|
||||
* Input Parameters:
|
||||
* startaddr - The first address to be cleaned
|
||||
* endaddr - The last address to be cleaned
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_clean(uintptr_t startaddr, uintptr_t endaddr)
|
||||
{
|
||||
uintptr_t cleansize;
|
||||
uintptr_t gulpend;
|
||||
irqstate_t flags;
|
||||
|
||||
/* If the range of addresses to clean is as large or larger the L2 cache,
|
||||
* then just clean the whole thing.
|
||||
*/
|
||||
|
||||
cleansize = endaddr - startaddr;
|
||||
if (cleansize >= PL310_CACHE_SIZE)
|
||||
{
|
||||
l2cc_clean_all();
|
||||
return;
|
||||
}
|
||||
|
||||
/* Align the starting address to a cache line boundary */
|
||||
|
||||
startaddr &= ~PL310_CACHE_LINE_MASK;
|
||||
|
||||
/* Clean the L2 cache by cache line, enabling interrupts momentarily
|
||||
* every PL310_GULP_SIZE bytes.
|
||||
*/
|
||||
|
||||
while (startaddr < endaddr)
|
||||
{
|
||||
/* Get the size of the next gulp of cache lines to flush. We do
|
||||
* this in small chunks so that we do not have to keep interrupts
|
||||
* disabled throughout the whole flush.
|
||||
*/
|
||||
|
||||
cleansize = endaddr - startaddr;
|
||||
gulpend = startaddr + MIN(cleansize, PL310_GULP_SIZE);
|
||||
|
||||
/* Disable interrupts and clean the gulp */
|
||||
|
||||
flags = enter_critical_section();
|
||||
while (startaddr < gulpend)
|
||||
{
|
||||
/* Clean the cache line by writing the address to the Clean
|
||||
* Physical Address Line Register (CPALR).
|
||||
*/
|
||||
|
||||
putreg32(startaddr, L2CC_CPALR);
|
||||
|
||||
/* Start of the next cache line */
|
||||
|
||||
startaddr += PL310_CACHE_LINE_SIZE;
|
||||
}
|
||||
|
||||
/* Enable interrupts momentarily */
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
|
||||
* EB, are empty.
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
putreg32(0, L2CC_CSR);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_flush_all
|
||||
*
|
||||
* Description:
|
||||
* Flush all ways using the Clean Invalidate Way Register (CIWR).
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_flush_all(void)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
/* Flush all ways using the Clean Invalidate Way Register (CIWR). */
|
||||
|
||||
flags = enter_critical_section();
|
||||
pl310_flush_all();
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_flush
|
||||
*
|
||||
* Description:
|
||||
* Flush a range of address by using the Clean Invalidate Physical Address
|
||||
* Line Register (CIPALR) repeatedly.
|
||||
*
|
||||
* Input Parameters:
|
||||
* startaddr - The first address to be flushed
|
||||
* endaddr - The last address to be flushed
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_flush(uint32_t startaddr, uint32_t endaddr)
|
||||
{
|
||||
uintptr_t flushsize;
|
||||
uintptr_t gulpend;
|
||||
irqstate_t flags;
|
||||
|
||||
/* If the range of addresses to flush is as large or larger the L2 cache,
|
||||
* then just flush the whole thing.
|
||||
*/
|
||||
|
||||
flushsize = endaddr - startaddr;
|
||||
if (flushsize >= PL310_CACHE_SIZE)
|
||||
{
|
||||
l2cc_flush_all();
|
||||
return;
|
||||
}
|
||||
|
||||
/* Align the starting address to a cache line boundary */
|
||||
|
||||
startaddr &= ~PL310_CACHE_LINE_MASK;
|
||||
|
||||
/* Flush the L2 cache by cache line, enabling interrupts momentarily
|
||||
* every PL310_GULP_SIZE bytes.
|
||||
*/
|
||||
|
||||
while (startaddr < endaddr)
|
||||
{
|
||||
/* Get the size of the next gulp of cache lines to flush. We do
|
||||
* this in small chunks so that we do not have to keep interrupts
|
||||
* disabled throughout the whole flush.
|
||||
*/
|
||||
|
||||
flushsize = endaddr - startaddr;
|
||||
gulpend = startaddr + MIN(flushsize, PL310_GULP_SIZE);
|
||||
|
||||
/* Disable interrupts and flush the gulp */
|
||||
|
||||
flags = enter_critical_section();
|
||||
while (startaddr < gulpend)
|
||||
{
|
||||
/* Flush the cache line by writing the address to the Clean
|
||||
* Invalidate Physical Address Line Register (CIPALR).
|
||||
*/
|
||||
|
||||
putreg32(startaddr, L2CC_CIPALR);
|
||||
|
||||
/* Start of the next cache line */
|
||||
|
||||
startaddr += PL310_CACHE_LINE_SIZE;
|
||||
}
|
||||
|
||||
/* Enable interrupts momentarily */
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
/* Drain the STB. Operation complete when all buffers, LRB, LFB, STB, and
|
||||
* EB, are empty.
|
||||
*/
|
||||
|
||||
flags = enter_critical_section();
|
||||
putreg32(0, L2CC_CSR);
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARMV8R_L2CC_PL310 */
|
||||
@ -259,18 +259,60 @@ void cp15_flush_dcache_all(void)
|
||||
cp15_dcache_op(CP15_CACHE_CLEANINVALIDATE);
|
||||
}
|
||||
|
||||
uint32_t cp15_cache_size(void)
|
||||
uint32_t cp15_icache_size(void)
|
||||
{
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
uint32_t line;
|
||||
static uint32_t csize;
|
||||
|
||||
line = cp15_cache_get_info(&sets, &ways);
|
||||
if (csize == 0)
|
||||
{
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
uint32_t line;
|
||||
|
||||
return sets * ways * line;
|
||||
line = cp15_cache_get_info(&sets, &ways, true);
|
||||
csize = sets * ways * line;
|
||||
}
|
||||
|
||||
return csize;
|
||||
}
|
||||
|
||||
uint32_t cp15_cache_linesize(void)
|
||||
uint32_t cp15_dcache_size(void)
|
||||
{
|
||||
return cp15_cache_get_info(NULL, NULL);
|
||||
static uint32_t csize;
|
||||
|
||||
if (csize == 0)
|
||||
{
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
uint32_t line;
|
||||
|
||||
line = cp15_cache_get_info(&sets, &ways, false);
|
||||
csize = sets * ways * line;
|
||||
}
|
||||
|
||||
return csize;
|
||||
}
|
||||
|
||||
uint32_t cp15_icache_linesize(void)
|
||||
{
|
||||
static uint32_t clsize;
|
||||
|
||||
if (clsize == 0)
|
||||
{
|
||||
clsize = cp15_cache_get_info(NULL, NULL, true);
|
||||
}
|
||||
|
||||
return clsize;
|
||||
}
|
||||
|
||||
uint32_t cp15_dcache_linesize(void)
|
||||
{
|
||||
static uint32_t clsize;
|
||||
|
||||
if (clsize == 0)
|
||||
{
|
||||
clsize = cp15_cache_get_info(NULL, NULL, false);
|
||||
}
|
||||
|
||||
return clsize;
|
||||
}
|
||||
|
||||
@ -1098,10 +1098,10 @@ void cp15_flush_dcache(uintptr_t start, uintptr_t end);
|
||||
void cp15_flush_dcache_all(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_cache_size
|
||||
* Name: cp15_icache_size
|
||||
*
|
||||
* Description:
|
||||
* Get cp15 cache size in byte
|
||||
* Get cp15 icache size in byte
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
@ -1111,23 +1111,55 @@ void cp15_flush_dcache_all(void);
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t cp15_cache_size(void);
|
||||
uint32_t cp15_icache_size(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_cache_linesize
|
||||
* Name: cp15_cache_size
|
||||
*
|
||||
* Description:
|
||||
* Get cp15 cache linesize in byte
|
||||
* Get cp15 dcache size in byte
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* Cache linesize in byte
|
||||
* Cache size in byte
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t cp15_cache_linesize(void);
|
||||
uint32_t cp15_dcache_size(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_icache_linesize
|
||||
*
|
||||
* Description:
|
||||
* Get cp15 icache linesize in byte
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* ICache linesize in byte
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t cp15_icache_linesize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: cp15_dcache_linesize
|
||||
*
|
||||
* Description:
|
||||
* Get cp15 dcache linesize in byte
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* DCache linesize in byte
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t cp15_dcache_linesize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
|
||||
277
arch/arm/src/armv8-r/l2cc.h
Normal file
277
arch/arm/src/armv8-r/l2cc.h
Normal file
@ -0,0 +1,277 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv8-r/l2cc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_ARMV8_R_L2CC_H
|
||||
#define __ARCH_ARM_SRC_ARMV8_R_L2CC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_L2CACHE
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_l2ccinitialize
|
||||
*
|
||||
* Description:
|
||||
* One time configuration of the L2 cache. The L2 cache will be enabled
|
||||
* upon return.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None. The L2 cache configuration is controlled by configuration
|
||||
* settings.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if 0 /* Prototyped in arm_internal.h */
|
||||
void arm_l2ccinitialize(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_linesize
|
||||
*
|
||||
* Description:
|
||||
* Get L2 cache linesize
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* L2 cache linesize
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t l2cc_linesize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_size
|
||||
*
|
||||
* Description:
|
||||
* Get L2CC-P310 L2 cache size
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* L2 cache size
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t l2cc_size(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_enable
|
||||
*
|
||||
* Description:
|
||||
* Re-enable the L2CC-P310 L2 cache by setting the enable bit in the
|
||||
* Control Register (CR)
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_enable(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_disable
|
||||
*
|
||||
* Description:
|
||||
* Disable the L2 cache
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_disable(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_sync
|
||||
*
|
||||
* Description:
|
||||
* Drain the L2 cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_sync(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_invalidate_all
|
||||
*
|
||||
* Description:
|
||||
* Invalidate the entire L2 cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_invalidate_all(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_invalidate
|
||||
*
|
||||
* Description:
|
||||
* Invalidate a range of addresses in the L2 cache
|
||||
*
|
||||
* Input Parameters:
|
||||
* startaddr - The first address to be invalidated
|
||||
* endaddr - The last address to be invalidated
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_invalidate(uintptr_t startaddr, uintptr_t endaddr);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_clean_all
|
||||
*
|
||||
* Description:
|
||||
* Clean the entire L2 cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_clean_all(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_clean
|
||||
*
|
||||
* Description:
|
||||
* Clean a range of address within the L2 cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* startaddr - The first address to be cleaned
|
||||
* endaddr - The last address to be cleaned
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_clean(uintptr_t startaddr, uintptr_t endaddr);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_flush_all
|
||||
*
|
||||
* Description:
|
||||
* Flush the entire L2 cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_flush_all(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: l2cc_flush
|
||||
*
|
||||
* Description:
|
||||
* Flush a range of address within the L2 cache.
|
||||
*
|
||||
* Input Parameters:
|
||||
* startaddr - The first address to be flushed
|
||||
* endaddr - The last address to be flushed
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void l2cc_flush(uint32_t startaddr, uint32_t endaddr);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#else /* CONFIG_ARCH_L2CACHE */
|
||||
/* Provide simple definitions to concentrate the inline conditional
|
||||
* compilation in one place.
|
||||
*/
|
||||
|
||||
# define l2cc_size() 0
|
||||
# define l2cc_linesize() 0
|
||||
# define l2cc_enable()
|
||||
# define l2cc_disable()
|
||||
# define l2cc_sync()
|
||||
# define l2cc_invalidate_all()
|
||||
# define l2cc_invalidate(s,e)
|
||||
# define l2cc_clean_all()
|
||||
# define l2cc_clean(s,e)
|
||||
# define l2cc_flush_all()
|
||||
# define l2cc_flush(s,e)
|
||||
|
||||
#endif /* CONFIG_ARCH_L2CACHE */
|
||||
#endif /* __ARCH_ARM_SRC_ARMV8_R_L2CC_H */
|
||||
483
arch/arm/src/armv8-r/l2cc_pl310.h
Normal file
483
arch/arm/src/armv8-r/l2cc_pl310.h
Normal file
@ -0,0 +1,483 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv8-r/l2cc_pl310.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* Reference: "CoreLink™ Level 2 Cache Controller L2C-310", Revision r3p2,
|
||||
* Technical Reference Manual, ARM DDI 0246F (ID011711), ARM
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_ARMV8_R_L2CC_PL310_H
|
||||
#define __ARCH_ARM_SRC_ARMV8_R_L2CC_PL310_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* The base address of the L2CC implementation must be provided in the chip.h
|
||||
* header file as L2CC_VBASE.
|
||||
*/
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* General Definitions ******************************************************/
|
||||
|
||||
#define PL310_CACHE_LINE_SIZE 32
|
||||
|
||||
#ifdef CONFIG_PL310_LOCKDOWN_BY_MASTER
|
||||
# define PL310_NLOCKREGS 8
|
||||
#else
|
||||
# define PL310_NLOCKREGS 1
|
||||
#endif
|
||||
|
||||
/* L2CC Register Offsets ****************************************************/
|
||||
|
||||
#define L2CC_IDR_OFFSET 0x0000 /* Cache ID Register */
|
||||
#define L2CC_TYPR_OFFSET 0x0004 /* Cache Type Register */
|
||||
#define L2CC_CR_OFFSET 0x0100 /* Control Register */
|
||||
#define L2CC_ACR_OFFSET 0x0104 /* Auxiliary Control Register */
|
||||
#define L2CC_TRCR_OFFSET 0x0108 /* Tag RAM Control Register */
|
||||
#define L2CC_DRCR_OFFSET 0x010c /* Data RAM Control Register */
|
||||
/* 0x0110-0x01fc Reserved */
|
||||
#define L2CC_ECR_OFFSET 0x0200 /* Event Counter Control Register */
|
||||
#define L2CC_ECFGR1_OFFSET 0x0204 /* Event Counter 1 Configuration Register */
|
||||
#define L2CC_ECFGR0_OFFSET 0x0208 /* Event Counter 0 Configuration Register */
|
||||
#define L2CC_EVR1_OFFSET 0x020c /* Event Counter 1 Value Register */
|
||||
#define L2CC_EVR0_OFFSET 0x0210 /* Event Counter 0 Value Register */
|
||||
#define L2CC_IMR_OFFSET 0x0214 /* Interrupt Mask Register */
|
||||
#define L2CC_MISR_OFFSET 0x0218 /* Masked Interrupt Status Register */
|
||||
#define L2CC_RISR_OFFSET 0x021c /* Raw Interrupt Status Register */
|
||||
#define L2CC_ICR_OFFSET 0x0220 /* Interrupt Clear Register */
|
||||
/* 0x0224-0x072c Reserved */
|
||||
#define L2CC_CSR_OFFSET 0x0730 /* Cache Synchronization Register */
|
||||
/* 0x0734-0x076c Reserved */
|
||||
#define L2CC_IPALR_OFFSET 0x0770 /* Invalidate Physical Address Line Register */
|
||||
/* 0x0774-0x0778 Reserved */
|
||||
#define L2CC_IWR_OFFSET 0x077c /* Invalidate Way Register */
|
||||
/* 0x0780-0x07af Reserved */
|
||||
#define L2CC_CPALR_OFFSET 0x07b0 /* Clean Physical Address Line Register */
|
||||
/* 0x07b4 Reserved */
|
||||
#define L2CC_CIR_OFFSET 0x07b8 /* Clean Index Register */
|
||||
#define L2CC_CWR_OFFSET 0x07bc /* Clean Way Register */
|
||||
/* 0x07c0-0x07ec Reserved */
|
||||
#define L2CC_CIPALR_OFFSET 0x07f0 /* Clean Invalidate Physical Address Line Register */
|
||||
/* 0x07f4 Reserved */
|
||||
#define L2CC_CIIR_OFFSET 0x07f8 /* Clean Invalidate Index Register */
|
||||
#define L2CC_CIWR_OFFSET 0x07fc /* Clean Invalidate Way Register */
|
||||
/* 0x0800-0x08fc Reserved */
|
||||
|
||||
/* Data and Instruction Lockdown registers where n=0-7.
|
||||
* The registers for n > 0 are implemented if the option
|
||||
* pl310_LOCKDOWN_BY_MASTER is enabled.
|
||||
* Otherwise, they are unused
|
||||
*/
|
||||
|
||||
#define L2CC_DLKR_OFFSET(n) (0x0900 + ((n) << 3)) /* Data Lockdown Register */
|
||||
#define L2CC_ILKR_OFFSET(n) (0x0904 + ((n) << 3)) /* Instruction Lockdown Register */
|
||||
/* 0x0940-0x0f4c Reserved */
|
||||
#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
|
||||
# define L2CC_LKLN_OFFSET 0x0950 /* Lock Line Enable Register */
|
||||
# define L2CC_UNLKW_OFFSET 0x0954 /* Unlock Way Register */
|
||||
#endif
|
||||
/* 0x0958-0x0bfc Reserved */
|
||||
#define L2CC_FLSTRT_OFFSET 0x0c00 /* Address filter start */
|
||||
#define L2CC_FLEND_OFFSET 0x0c04 /* Address filter end */
|
||||
/* 0x0c08-0x0f3c Reserved */
|
||||
#define L2CC_DCR_OFFSET 0x0f40 /* Debug Control Register */
|
||||
/* 0x0f44-0x0f5c Reserved */
|
||||
#define L2CC_PCR_OFFSET 0x0f60 /* Prefetch Control Register */
|
||||
/* 0x0f64-0x0f7c Reserved */
|
||||
#define L2CC_POWCR_OFFSET 0x0f80 /* Power Control Register */
|
||||
|
||||
/* L2CC Register Addresses **************************************************/
|
||||
|
||||
#define L2CC_IDR (L2CC_VBASE+L2CC_IDR_OFFSET)
|
||||
#define L2CC_TYPR (L2CC_VBASE+L2CC_TYPR_OFFSET)
|
||||
#define L2CC_CR (L2CC_VBASE+L2CC_CR_OFFSET)
|
||||
#define L2CC_ACR (L2CC_VBASE+L2CC_ACR_OFFSET)
|
||||
#define L2CC_TRCR (L2CC_VBASE+L2CC_TRCR_OFFSET)
|
||||
#define L2CC_DRCR (L2CC_VBASE+L2CC_DRCR_OFFSET)
|
||||
#define L2CC_ECR (L2CC_VBASE+L2CC_ECR_OFFSET)
|
||||
#define L2CC_ECFGR1 (L2CC_VBASE+L2CC_ECFGR1_OFFSET)
|
||||
#define L2CC_ECFGR0 (L2CC_VBASE+L2CC_ECFGR0_OFFSET)
|
||||
#define L2CC_EVR1 (L2CC_VBASE+L2CC_EVR1_OFFSET)
|
||||
#define L2CC_EVR0 (L2CC_VBASE+L2CC_EVR0_OFFSET)
|
||||
#define L2CC_IMR (L2CC_VBASE+L2CC_IMR_OFFSET)
|
||||
#define L2CC_MISR (L2CC_VBASE+L2CC_MISR_OFFSET)
|
||||
#define L2CC_RISR (L2CC_VBASE+L2CC_RISR_OFFSET)
|
||||
#define L2CC_ICR (L2CC_VBASE+L2CC_ICR_OFFSET)
|
||||
#define L2CC_CSR (L2CC_VBASE+L2CC_CSR_OFFSET)
|
||||
#define L2CC_IPALR (L2CC_VBASE+L2CC_IPALR_OFFSET)
|
||||
#define L2CC_IWR (L2CC_VBASE+L2CC_IWR_OFFSET)
|
||||
#define L2CC_CPALR (L2CC_VBASE+L2CC_CPALR_OFFSET)
|
||||
#define L2CC_CIR (L2CC_VBASE+L2CC_CIR_OFFSET)
|
||||
#define L2CC_CWR (L2CC_VBASE+L2CC_CWR_OFFSET)
|
||||
#define L2CC_CIPALR (L2CC_VBASE+L2CC_CIPALR_OFFSET)
|
||||
#define L2CC_CIIR (L2CC_VBASE+L2CC_CIIR_OFFSET)
|
||||
#define L2CC_CIWR (L2CC_VBASE+L2CC_CIWR_OFFSET)
|
||||
#define L2CC_DLKR(n) (L2CC_VBASE+L2CC_DLKR_OFFSET(n))
|
||||
#define L2CC_ILKR(n) (L2CC_VBASE+L2CC_ILKR_OFFSET(n))
|
||||
|
||||
#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
|
||||
# define L2CC_LKLN (L2CC_VBASE+L2CC_LKLN_OFFSET)
|
||||
# define L2CC_UNLKW (L2CC_VBASE+L2CC_UNLKW_OFFSET)
|
||||
#endif
|
||||
|
||||
#define L2CC_FLSTRT (L2CC_VBASE+L2CC_FLSTRT_OFFSET)
|
||||
#define L2CC_FLEND (L2CC_VBASE+L2CC_FLEND_OFFSET)
|
||||
#define L2CC_DCR (L2CC_VBASE+L2CC_DCR_OFFSET)
|
||||
#define L2CC_PCR (L2CC_VBASE+L2CC_PCR_OFFSET)
|
||||
#define L2CC_POWCR (L2CC_VBASE+L2CC_POWCR_OFFSET)
|
||||
|
||||
/* L2CC Register Bit Definitions ********************************************/
|
||||
|
||||
/* Cache ID Register (32-bit ID) */
|
||||
|
||||
#define L2CC_IDR_REV_MASK 0x0000003f
|
||||
#define L2CC_IDR_REV_R0P0 0x00000000
|
||||
#define L2CC_IDR_REV_R1P0 0x00000002
|
||||
#define L2CC_IDR_REV_R2P0 0x00000004
|
||||
#define L2CC_IDR_REV_R3P0 0x00000005
|
||||
#define L2CC_IDR_REV_R3P1 0x00000006
|
||||
#define L2CC_IDR_REV_R3P2 0x00000008
|
||||
|
||||
/* Cache Type Register */
|
||||
|
||||
#define L2CC_TYPR_IL2ASS (1 << 6) /* Bit 6: Instruction L2 Cache Associativity */
|
||||
#define L2CC_TYPR_IL2WSIZE_SHIFT (8) /* Bits 8-10: Instruction L2 Cache Way Size */
|
||||
#define L2CC_TYPR_IL2WSIZE_MASK (7 << L2CC_TYPR_IL2WSIZE_SHIFT)
|
||||
#define L2CC_TYPR_IL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_IL2WSIZE_SHIFT)
|
||||
#define L2CC_TYPR_DL2ASS (1 << 18) /* Bit 18: Data L2 Cache Associativity */
|
||||
#define L2CC_TYPR_DL2WSIZE_SHIFT (20) /* Bits 20-22: Data L2 Cache Way Size */
|
||||
#define L2CC_TYPR_DL2WSIZE_MASK (7 << L2CC_TYPR_DL2WSIZE_SHIFT)
|
||||
#define L2CC_TYPR_DL2WSIZE(n) ((uint32_t)(n) << L2CC_TYPR_DL2WSIZE_SHIFT)
|
||||
|
||||
/* Control Register */
|
||||
|
||||
#define L2CC_CR_L2CEN (1 << 0) /* Bit 0: L2 Cache Enable */
|
||||
|
||||
/* Auxiliary Control Register */
|
||||
|
||||
#define L2CC_ACR_FLZE (1 << 0) /* Bit 0: Full line zero enable */
|
||||
#define L2CC_ACR_HPSO (1 << 10) /* Bit 10: High Priority for SO and Dev Reads Enable */
|
||||
#define L2CC_ACR_SBDLE (1 << 11) /* Bit 11: Store Buffer Device Limitation Enable */
|
||||
#define L2CC_ACR_EXCC (1 << 12) /* Bit 12: Exclusive Cache Configuration */
|
||||
#define L2CC_ACR_SAIE (1 << 13) /* Bit 13: Shared Attribute Invalidate Enable */
|
||||
#define L2CC_ACR_ASS (1 << 16) /* Bit 16: Associativity */
|
||||
#define L2CC_ACR_WAYSIZE_SHIFT (17) /* Bits 17-19: Way Size */
|
||||
#define L2CC_ACR_WAYSIZE_MASK (7 << L2CC_ACR_WAYSIZE_SHIFT)
|
||||
#define L2CC_ACR_WAYSIZE_16KB (1 << L2CC_ACR_WAYSIZE_SHIFT)
|
||||
#define L2CC_ACR_WAYSIZE_32KB (2 << L2CC_ACR_WAYSIZE_SHIFT)
|
||||
#define L2CC_ACR_WAYSIZE_64KB (3 << L2CC_ACR_WAYSIZE_SHIFT)
|
||||
#define L2CC_ACR_WAYSIZE_128KB (4 << L2CC_ACR_WAYSIZE_SHIFT)
|
||||
#define L2CC_ACR_WAYSIZE_256KB (5 << L2CC_ACR_WAYSIZE_SHIFT)
|
||||
#define L2CC_ACR_WAYSIZE_512KB (6 << L2CC_ACR_WAYSIZE_SHIFT)
|
||||
#define L2CC_ACR_EMBEN (1 << 20) /* Bit 20: Event Monitor Bus Enable */
|
||||
#define L2CC_ACR_PEN (1 << 21) /* Bit 21: Parity Enable */
|
||||
#define L2CC_ACR_SAOEN (1 << 22) /* Bit 22: Shared Attribute Override Enable */
|
||||
#define L2CC_ACR_FWA_SHIFT (23) /* Bits 23-24: Force Write Allocate */
|
||||
#define L2CC_ACR_FWA_MASK (3 << L2CC_ACR_FWA_SHIFT)
|
||||
#define L2CC_ACR_FWA_AWCACHE (0 << L2CC_ACR_FWA_SHIFT) /* Use AWCACHE attributes for WA */
|
||||
#define L2CC_ACR_FWA_NOALLOC (1 << L2CC_ACR_FWA_SHIFT) /* No allocate */
|
||||
#define L2CC_ACR_FWA_OVERRIDE (2 << L2CC_ACR_FWA_SHIFT) /* Override AWCACHE attributes */
|
||||
#define L2CC_ACR_FWA_MAPPED (3 << L2CC_ACR_FWA_SHIFT) /* Internally mapped to 00 */
|
||||
|
||||
#define L2CC_ACR_CRPOL (1 << 25) /* Bit 25: Cache Replacement Policy */
|
||||
#define L2CC_ACR_NSLEN (1 << 26) /* Bit 26: Non-Secure Lockdown Enable */
|
||||
#define L2CC_ACR_NSIAC (1 << 27) /* Bit 27: Non-Secure Interrupt Access Control */
|
||||
#define L2CC_ACR_DPEN (1 << 28) /* Bit 28: Data Prefetch Enable */
|
||||
#define L2CC_ACR_IPEN (1 << 29) /* Bit 29: Instruction Prefetch Enable */
|
||||
#define L2CC_ACR_EBRESP (1 << 30) /* Bit 30: Early BRESP enable */
|
||||
|
||||
#define L2CC_ACR_SBZ (0x8000c1fe)
|
||||
|
||||
/* Tag RAM Control Register */
|
||||
|
||||
#define L2CC_TRCR_TSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */
|
||||
#define L2CC_TRCR_TSETLAT_MASK (7 << L2CC_TRCR_TSETLAT_SHIFT)
|
||||
#define L2CC_TRCR_TSETLAT(n) ((uint32_t)(n) << L2CC_TRCR_TSETLAT_SHIFT)
|
||||
#define L2CC_TRCR_TRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */
|
||||
#define L2CC_TRCR_TRDLAT_MASK (7 << L2CC_TRCR_TRDLAT_SHIFT)
|
||||
#define L2CC_TRCR_TRDLAT(n) ((uint32_t)(n) << L2CC_TRCR_TRDLAT_SHIFT)
|
||||
#define L2CC_TRCR_TWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */
|
||||
#define L2CC_TRCR_TWRLAT_MASK (7 << L2CC_TRCR_TWRLAT_SHIFT)
|
||||
#define L2CC_TRCR_TWRLAT(n) ((uint32_t)(n) << L2CC_TRCR_TWRLAT_SHIFT)
|
||||
|
||||
/* Data RAM Control Register */
|
||||
|
||||
#define L2CC_DRCR_DSETLAT_SHIFT (0) /* Bits 0-2: Setup Latency */
|
||||
#define L2CC_DRCR_DSETLAT_MASK (7 << L2CC_DRCR_DSETLAT_SHIFT)
|
||||
#define L2CC_DRCR_DSETLAT(n) ((uint32_t)(n) << L2CC_DRCR_DSETLAT_SHIFT)
|
||||
#define L2CC_DRCR_DRDLAT_SHIFT (4) /* Bits 4-6: Read Access Latency */
|
||||
#define L2CC_DRCR_DRDLAT_MASK (7 << L2CC_DRCR_DRDLAT_SHIFT)
|
||||
#define L2CC_DRCR_DRDLAT(n) ((uint32_t)(n) << L2CC_DRCR_DRDLAT_SHIFT)
|
||||
#define L2CC_DRCR_DWRLAT_SHIFT (8) /* Bits 8-10: Write Access Latency */
|
||||
#define L2CC_DRCR_DWRLAT_MASK (7 << L2CC_DRCR_DWRLAT_SHIFT)
|
||||
#define L2CC_DRCR_DWRLAT(n) ((uint32_t)(n) << L2CC_DRCR_DWRLAT_SHIFT)
|
||||
|
||||
/* Event Counter Control Register */
|
||||
|
||||
#define L2CC_ECR_EVCEN (1 << 0) /* Bit 0: Event Counter Enable */
|
||||
#define L2CC_ECR_EVC0RST (1 << 1) /* Bit 1: Event Counter 0 Reset */
|
||||
#define L2CC_ECR_EVC1RST (1 << 2) /* Bit 2: Event Counter 1 Reset */
|
||||
|
||||
/* Event Counter 1 Configuration Register */
|
||||
|
||||
#define L2CC_ECFGR1_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */
|
||||
#define L2CC_ECFGR1_EIGEN_MASK (3 << L2CC_ECFGR1_EIGEN_SHIFT)
|
||||
#define L2CC_ECFGR1_EIGEN_INTDIS (0 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables (default) */
|
||||
#define L2CC_ECFGR1_EIGEN_INTENINCR (1 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Increment condition */
|
||||
#define L2CC_ECFGR1_EIGEN_INTENOVER (2 << L2CC_ECFGR1_EIGEN_SHIFT) /* Enables with Overflow condition */
|
||||
#define L2CC_ECFGR1_EIGEN_INTGENDIS (3 << L2CC_ECFGR1_EIGEN_SHIFT) /* Disables Interrupt generation */
|
||||
#define L2CC_ECFGR1_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */
|
||||
#define L2CC_ECFGR1_ESRC_MASK (15 << L2CC_ECFGR1_ESRC_SHIFT)
|
||||
#define L2CC_ECFGR1_ESRC_CNTDIS (0 << L2CC_ECFGR1_ESRC_SHIFT) /* Counter Disabled */
|
||||
#define L2CC_ECFGR1_ESRC_CO (1 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is CO */
|
||||
#define L2CC_ECFGR1_ESRC_DRHIT (2 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRHIT */
|
||||
#define L2CC_ECFGR1_ESRC_DRREQ (3 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DRREQ */
|
||||
#define L2CC_ECFGR1_ESRC_DWHIT (4 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWHIT */
|
||||
#define L2CC_ECFGR1_ESRC_DWREQ (5 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWREQ */
|
||||
#define L2CC_ECFGR1_ESRC_DWTREQ (6 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is DWTREQ */
|
||||
#define L2CC_ECFGR1_ESRC_IRHIT (7 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRHIT */
|
||||
#define L2CC_ECFGR1_ESRC_IRREQ (8 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IRREQ */
|
||||
#define L2CC_ECFGR1_ESRC_WA (9 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is WA */
|
||||
#define L2CC_ECFGR1_ESRC_IPFALLOC (10 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is IPFALLOC */
|
||||
#define L2CC_ECFGR1_ESRC_EPFHIT (11 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFHIT */
|
||||
#define L2CC_ECFGR1_ESRC_EPFALLOC (12 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFALLOC */
|
||||
#define L2CC_ECFGR1_ESRC_SRRCVD (13 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRRCVD */
|
||||
#define L2CC_ECFGR1_ESRC_SRCONF (14 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is SRCONF */
|
||||
#define L2CC_ECFGR1_ESRC_EPFRCVD (15 << L2CC_ECFGR1_ESRC_SHIFT) /* Source is EPFRCVD */
|
||||
|
||||
/* Event Counter 0 Configuration Register */
|
||||
|
||||
#define L2CC_ECFGR0_EIGEN_SHIFT (0) /* Bits 0-1: Event Counter Interrupt Generation */
|
||||
#define L2CC_ECFGR0_EIGEN_MASK (3 << L2CC_ECFGR0_EIGEN_SHIFT)
|
||||
#define L2CC_ECFGR0_EIGEN_INTDIS (0 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables (default) */
|
||||
#define L2CC_ECFGR0_EIGEN_INTENINCR (1 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Increment condition */
|
||||
#define L2CC_ECFGR0_EIGEN_INTENOVER (2 << L2CC_ECFGR0_EIGEN_SHIFT) /* Enables with Overflow condition */
|
||||
#define L2CC_ECFGR0_EIGEN_INTGENDIS (3 << L2CC_ECFGR0_EIGEN_SHIFT) /* Disables Interrupt generation */
|
||||
#define L2CC_ECFGR0_ESRC_SHIFT (2) /* Bits 2-5: Event Counter Source */
|
||||
#define L2CC_ECFGR0_ESRC_MASK (15 << L2CC_ECFGR0_ESRC_SHIFT)
|
||||
#define L2CC_ECFGR0_ESRC_CNTDIS (0 << L2CC_ECFGR0_ESRC_SHIFT) /* Counter Disabled */
|
||||
#define L2CC_ECFGR0_ESRC_CO (1 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is CO */
|
||||
#define L2CC_ECFGR0_ESRC_DRHIT (2 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRHIT */
|
||||
#define L2CC_ECFGR0_ESRC_DRREQ (3 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DRREQ */
|
||||
#define L2CC_ECFGR0_ESRC_DWHIT (4 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWHIT */
|
||||
#define L2CC_ECFGR0_ESRC_DWREQ (5 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWREQ */
|
||||
#define L2CC_ECFGR0_ESRC_DWTREQ (6 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is DWTREQ */
|
||||
#define L2CC_ECFGR0_ESRC_IRHIT (7 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRHIT */
|
||||
#define L2CC_ECFGR0_ESRC_IRREQ (8 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IRREQ */
|
||||
#define L2CC_ECFGR0_ESRC_WA (9 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is WA */
|
||||
#define L2CC_ECFGR0_ESRC_IPFALLOC (10 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is IPFALLOC */
|
||||
#define L2CC_ECFGR0_ESRC_EPFHIT (11 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFHIT */
|
||||
#define L2CC_ECFGR0_ESRC_EPFALLOC (12 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFALLOC */
|
||||
#define L2CC_ECFGR0_ESRC_SRRCVD (13 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRRCVD */
|
||||
#define L2CC_ECFGR0_ESRC_SRCONF (14 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is SRCONF */
|
||||
#define L2CC_ECFGR0_ESRC_EPFRCVD (15 << L2CC_ECFGR0_ESRC_SHIFT) /* Source is EPFRCVD */
|
||||
|
||||
/* Event Counter 1 Value Register (32-bit value) */
|
||||
|
||||
/* Event Counter 0 Value Register (32-bit value) */
|
||||
|
||||
/* Interrupt Mask Register, Masked Interrupt Status Register,
|
||||
* Raw Interrupt Status Register, and Interrupt Clear Register.
|
||||
*/
|
||||
|
||||
#define L2CC_INT_ECNTR (1 << 0) /* Bit 0: Event Counter 1/0 Overflow Increment */
|
||||
#define L2CC_INT_PARRT (1 << 1) /* Bit 1: Parity Error on L2 Tag RAM, Read */
|
||||
#define L2CC_INT_PARRD (1 << 2) /* Bit 2: Parity Error on L2 Data RAM, Read */
|
||||
#define L2CC_INT_ERRWT (1 << 3) /* Bit 3: Error on L2 Tag RAM, Write */
|
||||
#define L2CC_INT_ERRWD (1 << 4) /* Bit 4: Error on L2 Data RAM, Write */
|
||||
#define L2CC_INT_ERRRT (1 << 5) /* Bit 5: Error on L2 Tag RAM, Read */
|
||||
#define L2CC_INT_ERRRD (1 << 6) /* Bit 6: Error on L2 Data RAM, Read */
|
||||
#define L2CC_INT_SLVERR (1 << 7) /* Bit 7: SLVERR from L3 Memory */
|
||||
#define L2CC_INT_DECERR (1 << 8) /* Bit 8: DECERR from L3 Memory */
|
||||
|
||||
/* Cache Synchronization Register */
|
||||
|
||||
#define L2CC_CSR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
|
||||
|
||||
/* Invalidate Physical Address Line Register */
|
||||
|
||||
#define L2CC_IPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
|
||||
#define L2CC_IPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */
|
||||
#define L2CC_IPALR_IDX_MASK (0x1ff << L2CC_IPALR_IDX_SHIFT)
|
||||
#define L2CC_IPALR_IDX(n) ((uint32_t)(n) << L2CC_IPALR_IDX_SHIFT)
|
||||
#define L2CC_IPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */
|
||||
#define L2CC_IPALR_TAG_MASK (0x3ffff << L2CC_IPALR_TAG_SHIFT)
|
||||
#define L2CC_IPALR_TAG(n) ((uint32_t)(n) << L2CC_IPALR_TAG_SHIFT)
|
||||
|
||||
/* Invalidate Way Register */
|
||||
|
||||
#define L2CC_IWR_WAY(n) (1 << (n)) /* Bist 0-7: Invalidate Way Number n, n=0..7 */
|
||||
#define L2CC_IWR_WAY0 (1 << 0) /* Bit 0: Invalidate Way Number 0 */
|
||||
#define L2CC_IWR_WAY1 (1 << 1) /* Bit 1: Invalidate Way Number 1 */
|
||||
#define L2CC_IWR_WAY2 (1 << 2) /* Bit 2: Invalidate Way Number 2 */
|
||||
#define L2CC_IWR_WAY3 (1 << 3) /* Bit 3: Invalidate Way Number 3 */
|
||||
#define L2CC_IWR_WAY4 (1 << 4) /* Bit 4: Invalidate Way Number 4 */
|
||||
#define L2CC_IWR_WAY5 (1 << 5) /* Bit 5: Invalidate Way Number 5 */
|
||||
#define L2CC_IWR_WAY6 (1 << 6) /* Bit 6: Invalidate Way Number 6 */
|
||||
#define L2CC_IWR_WAY7 (1 << 7) /* Bit 7: Invalidate Way Number 7 */
|
||||
|
||||
/* Clean Physical Address Line Register */
|
||||
|
||||
#define L2CC_CPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
|
||||
#define L2CC_CPALR_IDX_SHIFT (5) /* Bits 5-13: Index number */
|
||||
#define L2CC_CPALR_IDX_MASK (0x1ff << L2CC_CPALR_IDX_SHIFT)
|
||||
#define L2CC_CPALR_IDX(n) ((uint32_t)(n) << L2CC_CPALR_IDX_SHIFT)
|
||||
#define L2CC_CPALR_TAG_SHIFT (14) /* Bits 14-31: Tag number */
|
||||
#define L2CC_CPALR_TAG_MASK (0x3ffff << L2CC_CPALR_TAG_SHIFT)
|
||||
#define L2CC_CPALR_TAG(n) ((uint32_t)(n) << L2CC_CPALR_TAG_SHIFT)
|
||||
|
||||
/* Clean Index Register */
|
||||
|
||||
#define L2CC_CIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
|
||||
#define L2CC_CIR_IDX_SHIFT (5) /* Bits 5-13: Index number */
|
||||
#define L2CC_CIR_IDX_MASK (0x1ff << L2CC_CIR_IDX_SHIFT)
|
||||
#define L2CC_CIR_IDX(n) ((uint32_t)(n) << L2CC_CIR_IDX_SHIFT)
|
||||
#define L2CC_CIR_WAY_SHIFT (28) /* Bits 28-30: Way number */
|
||||
#define L2CC_CIR_WAY_MASK (7 << L2CC_CIR_WAY_SHIFT)
|
||||
#define L2CC_CIR_WAY(n) ((uint32_t)(n) << L2CC_CIR_WAY_SHIFT)
|
||||
|
||||
/* Clean Way Register */
|
||||
|
||||
#define L2CC_CWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Way Number n, n=0..7 */
|
||||
#define L2CC_CWR_WAY0 (1 << 0) /* Bit 0: Clean Way Number 0 */
|
||||
#define L2CC_CWR_WAY1 (1 << 1) /* Bit 1: Clean Way Number 1 */
|
||||
#define L2CC_CWR_WAY2 (1 << 2) /* Bit 2: Clean Way Number 2 */
|
||||
#define L2CC_CWR_WAY3 (1 << 3) /* Bit 3: Clean Way Number 3 */
|
||||
#define L2CC_CWR_WAY4 (1 << 4) /* Bit 4: Clean Way Number 4 */
|
||||
#define L2CC_CWR_WAY5 (1 << 5) /* Bit 5: Clean Way Number 5 */
|
||||
#define L2CC_CWR_WAY6 (1 << 6) /* Bit 6: Clean Way Number 6 */
|
||||
#define L2CC_CWR_WAY7 (1 << 7) /* Bit 7: Clean Way Number 7 */
|
||||
|
||||
/* Clean Invalidate Physical Address Line Register */
|
||||
|
||||
#define L2CC_CIPALR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
|
||||
#define L2CC_CIPALR_IDX_SHIFT (5) /* Bits 5-13: Index Number */
|
||||
#define L2CC_CIPALR_IDX_MASK (0x1ff << L2CC_CIPALR_IDX_SHIFT)
|
||||
#define L2CC_CIPALR_IDX(n) ((uint32_t)(n) << L2CC_CIPALR_IDX_SHIFT)
|
||||
#define L2CC_CIPALR_TAG_SHIFT (14) /* Bits 14-31: Tag Number */
|
||||
#define L2CC_CIPALR_TAG_MASK (0x3ffff << L2CC_CIPALR_TAG_SHIFT)
|
||||
#define L2CC_CIPALR_TAG(n) ((uint32_t)(n) << L2CC_CIPALR_TAG_SHIFT)
|
||||
|
||||
/* Clean Invalidate Index Register */
|
||||
|
||||
#define L2CC_CIIR_C (1 << 0) /* Bit 0: Cache Synchronization Status */
|
||||
#define L2CC_CIIR_IDX_SHIFT (5) /* Bits 5-13: Index Number */
|
||||
#define L2CC_CIIR_IDX_MASK (0x1ff << L2CC_CIIR_IDX_SHIFT)
|
||||
#define L2CC_CIIR_IDX(n) ((uint32_t)(n) << L2CC_CIIR_IDX_SHIFT)
|
||||
#define L2CC_CIIR_WAY_SHIFT (28) /* Bits 28-30: Way Number */
|
||||
#define L2CC_CIIR_WAY_MASK (7 << L2CC_CIIR_WAY_SHIFT)
|
||||
#define L2CC_CIIR_WAY(n) ((uint32_t)(n) << L2CC_CIIR_WAY_SHIFT)
|
||||
|
||||
/* Clean Invalidate Way Register */
|
||||
|
||||
#define L2CC_CIWR_WAY(n) (1 << (n)) /* Bits 0-7: Clean Invalidate Way Number n, n=1..7 */
|
||||
#define L2CC_CIWR_WAY0 (1 << 0) /* Bit 0: Clean Invalidate Way Number 0 */
|
||||
#define L2CC_CIWR_WAY1 (1 << 1) /* Bit 1: Clean Invalidate Way Number 1 */
|
||||
#define L2CC_CIWR_WAY2 (1 << 2) /* Bit 2: Clean Invalidate Way Number 2 */
|
||||
#define L2CC_CIWR_WAY3 (1 << 3) /* Bit 3: Clean Invalidate Way Number 3 */
|
||||
#define L2CC_CIWR_WAY4 (1 << 4) /* Bit 4: Clean Invalidate Way Number 4 */
|
||||
#define L2CC_CIWR_WAY5 (1 << 5) /* Bit 5: Clean Invalidate Way Number 5 */
|
||||
#define L2CC_CIWR_WAY6 (1 << 6) /* Bit 6: Clean Invalidate Way Number 6 */
|
||||
#define L2CC_CIWR_WAY7 (1 << 7) /* Bit 7: Clean Invalidate Way Number 7 */
|
||||
|
||||
/* Data Lockdown Register */
|
||||
|
||||
#define L2CC_DLKR_DLK(n) (1 << (n)) /* Bits 0-7: Data Lockdown in Way Number n, n=0..7 */
|
||||
#define L2CC_DLKR_DLK0 (1 << 0) /* Bit 0: Data Lockdown in Way Number 0 */
|
||||
#define L2CC_DLKR_DLK1 (1 << 1) /* Bit 1: Data Lockdown in Way Number 1 */
|
||||
#define L2CC_DLKR_DLK2 (1 << 2) /* Bit 2: Data Lockdown in Way Number 2 */
|
||||
#define L2CC_DLKR_DLK3 (1 << 3) /* Bit 3: Data Lockdown in Way Number 3 */
|
||||
#define L2CC_DLKR_DLK4 (1 << 4) /* Bit 4: Data Lockdown in Way Number 4 */
|
||||
#define L2CC_DLKR_DLK5 (1 << 5) /* Bit 5: Data Lockdown in Way Number 5 */
|
||||
#define L2CC_DLKR_DLK6 (1 << 6) /* Bit 6: Data Lockdown in Way Number 6 */
|
||||
#define L2CC_DLKR_DLK7 (1 << 7) /* Bit 7: Data Lockdown in Way Number 7 */
|
||||
|
||||
/* Instruction Lockdown Register */
|
||||
|
||||
#define L2CC_ILKR_ILK(n) (1 << (n)) /* Bits 0-7: Instruction Lockdown in Way Number n, n=0..7 */
|
||||
#define L2CC_ILKR_ILK0 (1 << 0) /* Bit 0: Instruction Lockdown in Way Number 0 */
|
||||
#define L2CC_ILKR_ILK1 (1 << 1) /* Bit 1: Instruction Lockdown in Way Number 1 */
|
||||
#define L2CC_ILKR_ILK2 (1 << 2) /* Bit 2: Instruction Lockdown in Way Number 2 */
|
||||
#define L2CC_ILKR_ILK3 (1 << 3) /* Bit 3: Instruction Lockdown in Way Number 3 */
|
||||
#define L2CC_ILKR_ILK4 (1 << 4) /* Bit 4: Instruction Lockdown in Way Number 4 */
|
||||
#define L2CC_ILKR_ILK5 (1 << 5) /* Bit 5: Instruction Lockdown in Way Number 5 */
|
||||
#define L2CC_ILKR_ILK6 (1 << 6) /* Bit 6: Instruction Lockdown in Way Number 6 */
|
||||
#define L2CC_ILKR_ILK7 (1 << 7) /* Bit 7: Instruction Lockdown in Way Number 7 */
|
||||
|
||||
/* Lock Line Enable Register */
|
||||
|
||||
#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
|
||||
# define L2CC_LKLN_ENABLE (1 << 0) /* Bit 0: Lockdown by line enable */
|
||||
#endif
|
||||
|
||||
/* Unlock Way Register */
|
||||
|
||||
#ifdef CONFIG_PL310_LOCKDOWN_BY_LINE
|
||||
# define L2CC_UNLKW_WAY_SHIFT (0) /* Bits 0-15: Unlock line for corresponding way */
|
||||
# define L2CC_UNLKW_WAY_MASK (0xffff << L2CC_UNLKW_WAY_SHIFT)
|
||||
# define L2CC_UNLKW_WAY_SET(n) ((uint32_t)(n) << L2CC_UNLKW_WAY_SHIFT)
|
||||
# define L2CC_UNLKW_WAY_BIT(n) ((1 << (n)) << L2CC_UNLKW_WAY_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Address filter start */
|
||||
|
||||
#ifdef PL310_ADDRESS_FILTERING
|
||||
# define L2CC_FLSTRT_ENABLE (1 << 0) /* Bit 0: Address filter enable */
|
||||
# define L2CC_FLSTRT_MASK (0xfff00000) /* Bits 20-31: Bits 20-31 of address mask */
|
||||
#endif
|
||||
|
||||
/* Address filter end */
|
||||
|
||||
#ifdef PL310_ADDRESS_FILTERING
|
||||
# define L2CC_FLEND_MASK (0xfff00000) /* Bits 20-31: Bits 20-31 of address mask */
|
||||
#endif
|
||||
|
||||
/* Debug Control Register */
|
||||
|
||||
#define L2CC_DCR_DCL (1 << 0) /* Bit 0: Disable Cache Linefill */
|
||||
#define L2CC_DCR_DWB (1 << 1) /* Bit 1: Disable Write-back, Force Write-through */
|
||||
#define L2CC_DCR_SPNIDEN (1 << 2) /* Bit 2: SPNIDEN Value */
|
||||
|
||||
/* Prefetch Control Register */
|
||||
|
||||
#define L2CC_PCR_SHIFT (0) /* Bits 0-4: Prefetch Offset */
|
||||
#define L2CC_PCR_MASK (31 << L2CC_PCR_SHIFT)
|
||||
#define L2CC_PCR_PREFETCH(n) ((uint32_t)(n) << L2CC_PCR_SHIFT)
|
||||
#define L2CC_PCR_NSIDEN (1 << 21) /* Bit 21: Not Same ID on Exclusive Sequence Enable */
|
||||
#define L2CC_PCR_IDLEN (1 << 23) /* Bit 23: INCR Double Linefill Enable */
|
||||
#define L2CC_PCR_PDEN (1 << 24) /* Bit 24: Prefetch Drop Enable */
|
||||
#define L2CC_PCR_DLFWRDIS (1 << 27) /* Bit 27: Double Linefill on WRAP Read Disable */
|
||||
#define L2CC_PCR_DATPEN (1 << 28) /* Bit 28: Data Prefetch Enable */
|
||||
#define L2CC_PCR_INSPEN (1 << 29) /* Bit 29: Instruction Prefetch Enable */
|
||||
#define L2CC_PCR_DLEN (1 << 30) /* Bit 30: Double Linefill Enable */
|
||||
|
||||
/* Power Control Register */
|
||||
|
||||
#define L2CC_POWCR_STBYEN (1 << 0) /* Bit 0: Standby Mode Enable */
|
||||
#define L2CC_POWCR_DCKGATEN (1 << 1) /* Bit 1: Dynamic Clock Gating Enable */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_ARMV8_R_L2CC_PL310_H */
|
||||
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Reference in New Issue
Block a user