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arch/arm/src/stm32f7: Port Bob Feritich's change (2c699d7812) to SDMMC2 and to all other STM32F7 architectures. Also add a conifiguration option to automatically enable I/O compensation.

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This commit is contained in:
Gregory Nutt 2018-07-15 16:17:41 -06:00
parent 2c699d7812
commit 0c093f800d
8 changed files with 86 additions and 49 deletions
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12
arch/arm/src/stm32f7/Kconfig
View File

@ -1642,6 +1642,18 @@ config STM32F7_WWDG
endmenu
config STM32F7_SYSCFG_IOCOMPENSATION
bool "SYSCFG I/O Compensation"
default n
---help---
By default the I/O compensation cell is not used. However when the I/O
output buffer speed is configured in 50 MHz or 100 MHz mode, it is
recommended to use the compensation cell for slew rate control on I/O
tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply.
The I/O compensation cell can be used only when the supply voltage ranges
from 2.4 to 3.6 V.
menu "U[S]ART Configuration"
depends on STM32F7_USART

12
arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h
*
* Copyright (C) 2014-2015, 2017 Gregory Nutt. All rights reserved.
* Copyright (C) 2014-2015, 2017-2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
* Bob Feretich <bob.feretich@rafresearch.com>
@ -58,7 +58,7 @@
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PA11 on some board, then the following definitions should
* CAN1_RX connects via PA11 on some board, then the following definitions should
* appear inthe board.h header file for that board:
*
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
@ -578,9 +578,9 @@
/* SD/MMC
*
* Note that the below configures GPIO_SPEED_50MHz I/O, that means for using
* the SDMMC, the board's boot code must enable I/O Compensation in the
* SYSCFG_CMPCR register.
* Note that the below configures GPIO_SPEED_50MHz I/O, that means for using
* the SDMMC, the board's boot code must enable I/O Compensation via the
* configuration option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y.
*/
#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
@ -594,7 +594,7 @@
#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
#define GPIO_SDMMC2_CK (GPIO_ALT|GPIO_AF11|GPIO_PORTD|GPIO_PIN6)
#define GPIO_SDMMC2_CK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6)
#define GPIO_SDMMC2_CMD (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7)
#define GPIO_SDMMC2_D0_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SDMMC2_D0_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)

11
arch/arm/src/stm32f7/chip/stm32f74xx75xx_pinmap.h
View File

@ -57,7 +57,7 @@
* Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
* Drivers, however, will use the pin selection without the numeric suffix.
* Additional definitions are required in the board.h file. For example, if
* CAN1_RX connects vis PA11 on some board, then the following definitions should
* CAN1_RX connects via PA11 on some board, then the following definitions should
* appear inthe board.h header file for that board:
*
* #define GPIO_CAN1_RX GPIO_CAN1_RX_1
@ -816,9 +816,14 @@
#define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11)
#define GPIO_SAI2_SD_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN10)
/* SD/MMC */
/* SD/MMC
*
* Note that the below configures GPIO_SPEED_50MHz I/O, that means for using
* the SDMMC, the board's boot code must enable I/O Compensation via the
* configuration option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y.
*/
#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)

13
arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h
View File

@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h
*
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
* Copyright (C) 2016, 2018 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@ -927,9 +927,14 @@
#define GPIO_SAI2_SD_B_3 (GPIO_ALT|GPIO_AF10|GPIO_PORTF|GPIO_PIN11)
#define GPIO_SAI2_SD_B_4 (GPIO_ALT|GPIO_AF10|GPIO_PORTG|GPIO_PIN10)
/* SD/MMC */
/* SD/MMC
*
* Note that the below configures GPIO_SPEED_50MHz I/O, that means for using
* the SDMMC, the board's boot code must enable I/O Compensation via the
* configuration option CONFIG_STM32F7_SYSCFG_IOCOMPENSATION=y.
*/
#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
@ -940,7 +945,7 @@
#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
#define GPIO_SDMMC2_CK (GPIO_ALT|GPIO_AF11|GPIO_PORTD|GPIO_PIN6)
#define GPIO_SDMMC2_CK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PORTD|GPIO_PIN6)
#define GPIO_SDMMC2_CMD (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7)
#define GPIO_SDMMC2_D0_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
#define GPIO_SDMMC2_D1_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)

22
arch/arm/src/stm32f7/stm32_gpio.c
View File

@ -49,9 +49,6 @@
#include <nuttx/irq.h>
#include <arch/stm32f7/chip.h>
#include "up_arch.h"
#include "chip/stm32_syscfg.h"
#include "stm32_gpio.h"
/* Content of this file requires verification before it is used with other
@ -108,25 +105,6 @@ const uint32_t g_gpiobase[STM32F7_NGPIO] =
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exclusion is necessary.
*
****************************************************************************/
void stm32_gpioinit(void)
{
}
/****************************************************************************
* Name: stm32_configgpio
*

56
arch/arm/src/stm32f7/stm32_gpio.h
View File

@ -49,7 +49,9 @@
#include <nuttx/irq.h>
#include "up_arch.h"
#include "chip.h"
#include "chip/stm32_syscfg.h"
#include "chip/stm32_gpio.h"
/************************************************************************************
@ -253,6 +255,47 @@ extern "C"
EXTERN const uint32_t g_gpiobase[STM32F7_NGPIO];
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: syscfg_iocompensation
*
* Description:
* Enable I/O compensation.
*
* By default the I/O compensation cell is not used. However when the I/O
* output buffer speed is configured in 50 MHz or 100 MHz mode, it is
* recommended to use the compensation cell for slew rate control on I/O
* tf(IO)out)/tr(IO)out commutation to reduce the I/O noise on power supply.
*
* The I/O compensation cell can be used only when the supply voltage ranges
* from 2.4 to 3.6 V.
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
static inline void syscfg_iocompensation(void)
{
/* Enable I/O Compensation. Writing '1' to the CMPCR power-down bit
* enables the I/O compensation cell.
*/
putreg32(SYSCFG_CMPCR_CMPPD, STM32_SYSCFG_CMPCR);
/* Wait for compensation cell to become ready */
while ((getreg32(STM32_SYSCFG_CMPCR) & SYSCFG_CMPCR_READY) == 0)
{
}
}
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
@ -352,19 +395,6 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg);
# define stm32_dumpgpio(p,m)
#endif
/************************************************************************************
* Function: stm32_gpioinit
*
* Description:
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32_start().
*
************************************************************************************/
void stm32_gpioinit(void);
#undef EXTERN
#if defined(__cplusplus)
}

2
arch/arm/src/stm32f7/stm32_otghost.c
View File

@ -5367,7 +5367,7 @@ FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller)
/* Alternate function pin configuration. Here we assume that:
*
* 1. GPIOA, SYSCFG, and OTG FS peripheral clocking have already been\
* 1. GPIOA, SYSCFG, and OTG FS peripheral clocking have already been
* enabled as part of the boot sequence.
* 2. Board-specific logic has already enabled other board specific GPIOs
* for things like soft pull-up, VBUS sensing, power controls, and over-

7
arch/arm/src/stm32f7/stm32_rcc.c
View File

@ -51,6 +51,7 @@
#include "up_arch.h"
#include "chip/stm32_flash.h"
#include "stm32_gpio.h"
#include "stm32_rcc.h"
#include "stm32_pwr.h"
@ -137,6 +138,12 @@ void stm32_clockconfig(void)
#endif
#ifdef CONFIG_STM32F7_SYSCFG_IOCOMPENSATION
/* Enable I/O Compensation */
syscfg_iocompensation();
#endif
/* Enable peripheral clocking */
rcc_enableperipherals();