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arm/armv8-r: Fix cache interface

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Signed-off-by: wangming9 <wangming9@xiaomi.com>
This commit is contained in:
wangming9 2024-02-06 20:31:49 +08:00 committed by Xiang Xiao
parent 0bfd4c5e0d
commit 0c12fb9237
3 changed files with 24 additions and 8 deletions
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4
arch/arm/src/armv8-r/arm_cache.c
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@ -308,7 +308,7 @@ void up_invalidate_dcache_all(void)
void up_clean_dcache(uintptr_t start, uintptr_t end) void up_clean_dcache(uintptr_t start, uintptr_t end)
{ {
if ((end - start) < cp15_cache_size()) if ((end - start) < cp15_dcache_size())
{ {
cp15_clean_dcache(start, end); cp15_clean_dcache(start, end);
} }
@ -372,7 +372,7 @@ void up_clean_dcache_all(void)
void up_flush_dcache(uintptr_t start, uintptr_t end) void up_flush_dcache(uintptr_t start, uintptr_t end)
{ {
if ((end - start) < cp15_cache_size()) if ((end - start) < cp15_dcache_size())
{ {
cp15_flush_dcache(start, end); cp15_flush_dcache(start, end);
} }

26
arch/arm/src/armv8-r/cp15_cacheops.c
View File

@ -28,6 +28,12 @@
#include "cp15_cacheops.h" #include "cp15_cacheops.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define NVIC_CSSELR_IND (1 << 0)
/**************************************************************************** /****************************************************************************
* Private Functions * Private Functions
****************************************************************************/ ****************************************************************************/
@ -44,9 +50,17 @@ static inline uint32_t ilog2(uint32_t u)
return i; return i;
} }
static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways) static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways,
bool icache)
{ {
uint32_t ccsidr = CP15_GET(CCSIDR); uint32_t ccsidr;
uint32_t csselr;
csselr = CP15_GET(CSSELR);
CP15_SET(CSSELR, (csselr & ~NVIC_CSSELR_IND) | (icache & NVIC_CSSELR_IND));
ccsidr = CP15_GET(CCSIDR);
if (sets) if (sets)
{ {
@ -58,6 +72,8 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
*ways = ((ccsidr >> 3) & 0x3ff) + 1; *ways = ((ccsidr >> 3) & 0x3ff) + 1;
} }
CP15_SET(CSSELR, csselr); /* restore csselr */
return (1 << ((ccsidr & 0x7) + 2)) * 4; return (1 << ((ccsidr & 0x7) + 2)) * 4;
} }
@ -93,7 +109,7 @@ static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
{ {
uint32_t line; uint32_t line;
line = cp15_cache_get_info(NULL, NULL); line = cp15_dcache_linesize();
ARM_DSB(); ARM_DSB();
@ -158,7 +174,7 @@ void cp15_dcache_op_level(uint32_t level, int op)
/* Get cache info */ /* Get cache info */
line = cp15_cache_get_info(&sets, &ways); line = cp15_cache_get_info(&sets, &ways, false);
way_shift = 32 - ilog2(ways); way_shift = 32 - ilog2(ways);
set_shift = ilog2(line); set_shift = ilog2(line);
@ -209,7 +225,7 @@ void cp15_invalidate_icache(uintptr_t start, uintptr_t end)
{ {
uint32_t line; uint32_t line;
line = cp15_cache_get_info(NULL, NULL); line = cp15_icache_linesize();
start &= ~(line - 1); start &= ~(line - 1);
ARM_DSB(); ARM_DSB();

2
arch/arm/src/armv8-r/cp15_cacheops.h
View File

@ -1114,7 +1114,7 @@ void cp15_flush_dcache_all(void);
uint32_t cp15_icache_size(void); uint32_t cp15_icache_size(void);
/**************************************************************************** /****************************************************************************
* Name: cp15_cache_size * Name: cp15_dcache_size
* *
* Description: * Description:
* Get cp15 dcache size in byte * Get cp15 dcache size in byte