Teensy clock fixes.

The High Gain bit in MCG_C1 was preventing teensy from booting
except after a programming session. The second change doesn't appear
to change any functionality, but complies with restrictions in the k20
family reference manual on FEI -> FBE clock transiions.

arch/arm/src/kinetis/kinetis_clockconfig.c

@@ -132,8 +132,11 @@ void kinetis_pllconfig(void)
    *   HGO   = 1 (High Gain Oscillator Select)
    *   RANGE = 2 (Oscillator of 8 MHz to 32 MHz)
    */
-
+#ifdef BOARD_EXTAL_LP
+  putreg8(MCG_C2_EREFS | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
+#else
   putreg8(MCG_C2_EREFS | MCG_C2_HGO | MCG_C2_RANGE_VHIGH, KINETIS_MCG_C2);
+#endif /*BOARD_EXTAL_LP*/
 #endif
 
   /* Released latched state of oscillator and GPIO */
@@ -156,7 +159,11 @@ void kinetis_pllconfig(void)
    *   CLKS     = 2 (Clock Source Select, External reference clock)
    */
 
+#ifdef BOARD_FRDIV
+  putreg8(BOARD_FRDIV | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1);
+#else
   putreg8(MCG_C1_FRDIV_DIV256 | MCG_C1_CLKS_EXTREF, KINETIS_MCG_C1);
+#endif
 
   /* If we aren't using an oscillator input we don't need to wait for the
    * oscillator to initialize

configs/teensy-3.x/include/board.h

@@ -56,6 +56,14 @@
 /* The teensy-3.1 has a 16MHz crystal on board */
 
 #undef  BOARD_EXTCLOCK                      /* Crystal */
+#define BOARD_EXTAL_LP                      /* Low Power, as opposed to Hi Gain */
+
+/* BOARD_FR_DIV is MCG_C1_FRDIV_DIV512 from kinetis_mcg.h. According to the k20
+ * reference manual, when transitioning MCG clock modes to FLL Bypassed External
+ * the C1 divider must be set so that the FLL clock is between 31.25 and 39.0625 khz.
+ * For teensy-3.x that works out to a divider of 512.
+ */
+#define BOARD_FR_DIV (4 << 3)
 #define BOARD_EXTAL_FREQ     16000000       /* 16MHz crystal frequency (REFCLK) */
 #define BOARD_XTAL32_FREQ    32768          /* 32KHz RTC Oscillator (not populated) */