boards/arm/ac6: add scatter linker script for sabre-6quad/lm3s6965-ek
add armclang compiler(AC6) support for board sabre-6quad/lm3s6965-ek Verified config: 1. lm3s6965-ek:qemu-flat (Disable file apps) ./tools/configure.sh lm3s6965-ek:qemu-flat -CONFIG_BOARDCTL_APP_SYMTAB=y -CONFIG_ELF=y -CONFIG_EXAMPLES_ELF=y -CONFIG_EXAMPLES_ELF_DEVPATH="/dev/ram5" -CONFIG_EXAMPLES_HELLO=y -CONFIG_EXAMPLES_MODULE=y -CONFIG_EXAMPLES_MODULE_DEVPATH="/dev/ram6" -CONFIG_EXAMPLES_NETTEST=m -CONFIG_EXAMPLES_WGET=y -CONFIG_HOST_MACOS=y -CONFIG_LIBC_DLFCN=y -CONFIG_NSH_FILE_APPS=y 2. sabre-6quad/smp Signed-off-by: chao an <anchao@xiaomi.com>
This commit is contained in:
chao an
Xiang Xiao
parent
0bafb014a1
commit
0c4ca8dd21
@ -22,7 +22,11 @@ include $(TOPDIR)/.config
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include $(TOPDIR)/tools/Config.mk
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include $(TOPDIR)/arch/arm/src/armv7-a/Toolchain.defs
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LDSCRIPT = dramboot.ld
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ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),y)
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LDSCRIPT = dramboot.sct
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else
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LDSCRIPT = dramboot.ld
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endif
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ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
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ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
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130
boards/arm/imx6/sabre-6quad/scripts/dramboot.sct
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130
boards/arm/imx6/sabre-6quad/scripts/dramboot.sct
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@ -0,0 +1,130 @@
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#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-a9
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/****************************************************************************
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* boards/arm/imx6/sabre-6quad/scripts/dramboot.sct
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* The i.MX6 has 256 KB of OCRAM beginning at virtual address 0x0090:0000
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* This memory configuration, however, loads into the 1GB DDR3 on board
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* the Sabre 6Quad K which lies at 0x1000:0000. Code is positioned at
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* 0x10800000 which the standard load address of Linux when used with uBoot.
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*
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* Vectors in low memory are assumed and 16KB of OCRAM is reserved at the
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* high end of OCRAM for the page table.
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*/
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#define DDR3_START 0x10800000
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#define DDR3_SIZE 0x000FE000
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OSCRAM_SECTIONS DDR3_START DDR3_SIZE
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{
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text +0
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{
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*(.vectors,+FIRST)
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*(.text)
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*(.text.*)
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aeabi_sdiv.o
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dfixull.o
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dnaninf.o
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usenofp.o
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*(.fixup)
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*(.gnu.warning)
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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*(.ARM.extab*)
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*(.gnu.linkonce.armextab.*)
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}
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init_section AlignExpr(ImageLimit(text), 0x4)
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{
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*(.init_array)
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*(.init_array.*)
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}
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ARM.extab AlignExpr(ImageLimit(init_section), 0x4)
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{
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*(.ARM.extab*)
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}
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ARM.exidx AlignExpr(ImageLimit(ARM.extab), 0x4)
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{
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*(.ARM.exidx*)
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*(.gnu.linkonce.armexidx.*)
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}
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eronly AlignExpr(ImageLimit(ARM.exidx), 0x4)
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{
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}
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tdata AlignExpr(ImageLimit(eronly), 0x4)
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{
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*(.tdata)
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*(.tdata.*)
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*(.gnu.linkonce.td.*)
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}
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tbss AlignExpr(ImageLimit(tdata), 0x4)
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{
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*(.tbss)
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*(.tbss.*)
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*(.gnu.linkonce.tb.*)
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*(.tcommon);
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}
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data AlignExpr(ImageLimit(tbss), 0x4)
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{
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*(.data)
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*(.data.*)
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*(.gnu.linkonce.d.*)
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CONSTRUCTORS
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}
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bss AlignExpr(ImageLimit(data), 0x8)
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{
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*(.bss)
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*(.bss.*)
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*(.gnu.linkonce.b.*)
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*(COMMON)
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*(+ZI)
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}
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noinit AlignExpr(ImageLimit(bss), 0x100)
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{
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*(.noinit*)
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}
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stab 0 { *(.stab) }
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stabstr 0 { *(.stabstr) }
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stab.excl 0 { *(.stab.excl) }
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stab.exclstr 0 { *(.stab.exclstr) }
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stab.index 0 { *(.stab.index) }
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stab.indexstr 0 { *(.stab.indexstr) }
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comment 0 { *(.comment) }
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debug_abbrev 0 { *(.debug_abbrev) }
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debug_info 0 { *(.debug_info) }
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debug_line 0 { *(.debug_line) }
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debug_pubnames 0 { *(.debug_pubnames) }
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debug_aranges 0 { *(.debug_aranges) }
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}
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@ -22,7 +22,11 @@ include $(TOPDIR)/.config
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include $(TOPDIR)/tools/Config.mk
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include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
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ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)ld.script
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ifeq ($(CONFIG_ARM_TOOLCHAIN_ARMCLANG),y)
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ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)ld.sct
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else
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ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)ld.script
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endif
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ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
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ifeq ($(CONFIG_NXFLAT),y)
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114
boards/arm/tiva/lm3s6965-ek/scripts/ld.sct
Normal file
114
boards/arm/tiva/lm3s6965-ek/scripts/ld.sct
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@ -0,0 +1,114 @@
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#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m3
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/****************************************************************************
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* boards/arm/tiva/lm3s6965-ek/scripts/ld.sct
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#define FLASH_START 0x00000000
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#define FLASH_SIZE 0x00040000
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#define SRAM_START 0x20000000
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#define SRAM_SIZE 0x00010000
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SRAM_SECTIONS FLASH_START FLASH_SIZE
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{
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text +0
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{
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*(.vectors,+FIRST)
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*(.text)
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*(.text.*)
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*(.fixup)
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*(.gnu.warning)
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.t.*)
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*(.glue_7)
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*(.glue_7t)
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*(.got)
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*(.gcc_except_table)
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*(.gnu.linkonce.r.*)
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}
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init_section AlignExpr(ImageLimit(text), 0x4)
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{
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*(.init_array)
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*(.init_array.*)
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}
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ARM.extab AlignExpr(ImageLimit(init_section), 0x4)
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{
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*(.ARM.extab*)
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}
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ARM.exidx AlignExpr(ImageLimit(ARM.extab), 0x4)
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{
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*(.ARM.exidx*)
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}
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ARM.Collect AlignExpr(ImageLimit(ARM.exidx), 0x4)
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{
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*(.ARM.Collect*)
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}
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eronly AlignExpr(ImageLimit(ARM.Collect), 0x4)
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{
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}
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tdata SRAM_START SRAM_SIZE
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{
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*(.tdata)
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*(.tdata.*)
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*(.gnu.linkonce.td.*)
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}
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tbss AlignExpr(ImageLimit(tdata), 0x4)
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{
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*(.tbss)
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*(.tbss.*)
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*(.gnu.linkonce.tb.*)
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*(.tcommon);
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}
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noinit AlignExpr(ImageLimit(tbss), 0x4)
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{
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*(.noinit*)
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}
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data AlignExpr(ImageLimit(noinit), 0x4)
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{
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*(+RW)
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}
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bss AlignExpr(ImageLimit(data), 0x8)
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{
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*(+ZI)
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}
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stab 0 { *(.stab) }
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stabstr 0 { *(.stabstr) }
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stab.excl 0 { *(.stab.excl) }
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stab.exclstr 0 { *(.stab.exclstr) }
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stab.index 0 { *(.stab.index) }
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stab.indexstr 0 { *(.stab.indexstr) }
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comment 0 { *(.comment) }
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debug_abbrev 0 { *(.debug_abbrev) }
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debug_info 0 { *(.debug_info) }
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debug_line 0 { *(.debug_line) }
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debug_pubnames 0 { *(.debug_pubnames) }
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debug_aranges 0 { *(.debug_aranges) }
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}
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