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arch/arm/src/stm32f0l0g0: Support timers available on STM32G070

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arch/arm/src/stm32f0l0g0: Pinmap TIM1 GPIOs available for STM32G0
arch/arm/src/stm32f0l0g0: Add TIM driver lowerhalf
arch/arm/src/stm32f0l0g0/stm32_tim_lowerhalf.c:  Handle 32-bit overflow on some calculations.
This commit is contained in:
Daniel Pereira Volpato 2019-10-07 22:07:21 -06:00 committed by Gregory Nutt
parent 8c62600cc1
commit 0d1934a740
4 changed files with 1123 additions and 1 deletions
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21
arch/arm/src/stm32f0l0g0/Kconfig
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@ -796,6 +796,14 @@ config STM32F0L0G0_STM32G0
select STM32F0L0G0_HAVE_DMAMUX
select STM32F0L0G0_HAVE_IP_USART_V2
select STM32F0L0G0_HAVE_IP_EXTI_V2
select STM32F0L0G0_HAVE_TIM1
select STM32F0L0G0_HAVE_TIM3
select STM32F0L0G0_HAVE_TIM6
select STM32F0L0G0_HAVE_TIM7
select STM32F0L0G0_HAVE_TIM14
select STM32F0L0G0_HAVE_TIM15
select STM32F0L0G0_HAVE_TIM16
select STM32F0L0G0_HAVE_TIM17
config STM32F0L0G0_STM32L0
bool
@ -1297,45 +1305,55 @@ config STM32F0L0G0_TIM1
bool "TIM1"
default n
depends on STM32F0L0G0_HAVE_TIM1
select STM32F0L0G0_TIM
config STM32F0L0G0_TIM2
bool "TIM2"
default n
depends on STM32F0L0G0_HAVE_TIM2
select STM32F0L0G0_TIM
config STM32F0L0G0_TIM3
bool "TIM3"
default n
depends on STM32F0L0G0_HAVE_TIM3
select STM32F0L0G0_TIM
config STM32F0L0G0_TIM6
bool "TIM6"
default n
depends on STM32F0L0G0_HAVE_TIM6
select STM32F0L0G0_TIM
config STM32F0L0G0_TIM7
bool "TIM7"
default n
depends on STM32F0L0G0_HAVE_TIM7
select STM32F0L0G0_TIM
config STM32F0L0G0_TIM14
bool "TIM14"
default n
depends on STM32F0L0G0_HAVE_TIM14
select STM32F0L0G0_TIM
config STM32F0L0G0_TIM15
bool "TIM15"
default n
depends on STM32F0L0G0_HAVE_TIM15
select STM32F0L0G0_TIM
config STM32F0L0G0_TIM16
bool "TIM16"
default n
depends on STM32F0L0G0_HAVE_TIM16
select STM32F0L0G0_TIM
config STM32F0L0G0_TIM17
bool "TIM17"
default n
depends on STM32F0L0G0_HAVE_TIM17
select STM32F0L0G0_TIM
config STM32F0L0G0_TSC
bool "TSC"
@ -1436,6 +1454,9 @@ config STM32F0L0G0_CAN
config STM32F0L0G0_USART
bool
config STM32F0L0G0_TIM
bool
config STM32F0L0G0_SERIALDRIVER
bool

4
arch/arm/src/stm32f0l0g0/Make.defs
View File

@ -125,3 +125,7 @@ endif
ifeq ($(CONFIG_STM32F0L0G0_RNG),y)
CHIP_CSRCS += stm32_rng.c
endif
ifeq ($(CONFIG_STM32F0L0G0_TIM),y)
CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c
endif

1068
arch/arm/src/stm32f0l0g0/hardware/stm32_tim.h
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File diff suppressed because it is too large Load Diff

31
arch/arm/src/stm32f0l0g0/hardware/stm32g0_pinmap.h
View File

@ -4,6 +4,9 @@
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Mateusz Szafoni <raiden00@railab.me>
*
* Copyright (C) 2019 Fundação CERTI. All rights reserved.
* Author: Daniel Pereira Volpato <dpo@certi.org.br>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
@ -81,6 +84,34 @@
/* TODO: Timers */
#define GPIO_TIM1_BKIN_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN6)
#define GPIO_TIM1_BKIN_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN12)
#define GPIO_TIM1_BKIN_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN13)
#define GPIO_TIM1_BKIN_4 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN5)
#define GPIO_TIM1_BKIN2_1 (GPIO_ALT | GPIO_AF5 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_TIM1_BKIN2_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN14)
#define GPIO_TIM1_BKIN2_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN9)
#define GPIO_TIM1_CH1_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN8)
#define GPIO_TIM1_CH1_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN8)
#define GPIO_TIM1_CH1N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN7)
#define GPIO_TIM1_CH1N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN13)
#define GPIO_TIM1_CH1N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN2)
#define GPIO_TIM1_CH2_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN9)
#define GPIO_TIM1_CH2_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN3)
#define GPIO_TIM1_CH2_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN9)
#define GPIO_TIM1_CH2N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN0)
#define GPIO_TIM1_CH2N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN14)
#define GPIO_TIM1_CH2N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN3)
#define GPIO_TIM1_CH3_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN10)
#define GPIO_TIM1_CH3_2 (GPIO_ALT | GPIO_AF1 | GPIO_PORTB | GPIO_PIN6)
#define GPIO_TIM1_CH3_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN10)
#define GPIO_TIM1_CH3N_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN1)
#define GPIO_TIM1_CH3N_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTB | GPIO_PIN15)
#define GPIO_TIM1_CH3N_3 (GPIO_ALT | GPIO_AF2 | GPIO_PORTD | GPIO_PIN4)
#define GPIO_TIM1_CH4_1 (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN11)
#define GPIO_TIM1_CH4_2 (GPIO_ALT | GPIO_AF2 | GPIO_PORTC | GPIO_PIN11)
#define GPIO_TIM1_ETR (GPIO_ALT | GPIO_AF2 | GPIO_PORTA | GPIO_PIN12)
/* TODO: USART */
#define GPIO_USART1_CTS_1 (GPIO_ALT | GPIO_AF1 | GPIO_PORTA | GPIO_PIN11)