Completes coding of the STM32 F4 Ethernet driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4161 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
parent
8c1436b4a6
commit
0d20925085
@ -2252,3 +2252,4 @@
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because CodeSourcery doesn't support hard flowing point!)
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* arch/arm/src/stm32/chip/stm32_eth.h: Add Ethernet register definitions
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for the STM32 F4.
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* arch/arm/srcm/stm32/stm32_eth.c: Adds an Ethernet driver for the STM32 F4.
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@ -149,6 +149,11 @@
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#ifndef CONFIG_STM32_ETH_BUFSIZE
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# define CONFIG_STM32_ETH_BUFSIZE CONFIG_NET_BUFSIZE
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#endif
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#if CONFIG_STM32_ETH_BUFSIZE > ETH_TDES1_TBS1_MASK
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# error "CONFIG_STM32_ETH_BUFSIZE is too large"
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#endif
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#ifndef CONFIG_STM32_ETH_NRXDESC
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# define CONFIG_STM32_ETH_NRXDESC 8
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#endif
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@ -156,11 +161,9 @@
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# define CONFIG_STM32_ETH_NTXDESC 4
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#endif
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#if CONFIG_STM32_ETH_NTXDESC > 2
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# define STM32_ETH_NFREEBUFFERS CONFIG_STM32_ETH_NTXDESC
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#else
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# define STM32_ETH_NFREEBUFFERS 2
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#endif
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/* We need at least one more free buffer than transmit buffers */
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#define STM32_ETH_NFREEBUFFERS (CONFIG_STM32_ETH_NTXDESC+1)
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/* Clocking *****************************************************************/
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/* Set MACMIIAR CR bits depending on HCLK setting */
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@ -396,9 +399,9 @@
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* ETH_DMABMR_DSL Bits 2-6: Descriptor skip length
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* ETH_DMABMR_EDFE Bit 7: Enhanced descriptor format enable
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* ETH_DMABMR_PBL Bits 8-13: Programmable burst length
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* ETH_DMABMR_RTPR Bits 14-15: Rx Tx priority ratio
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* ETH_DMABMR_RTPR Bits 14-15: RX TX priority ratio
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* ETH_DMABMR_FB Bit 16: Fixed burst
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* ETH_DMABMR_RDP Bits 17-22: Rx DMA PBL
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* ETH_DMABMR_RDP Bits 17-22: RX DMA PBL
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* ETH_DMABMR_USP Bit 23: Use separate PBL
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* ETH_DMABMR_FPM Bit 24: 4xPBL mode
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* ETH_DMABMR_AAB Bit 25: Address-aligned beats
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@ -418,9 +421,9 @@
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* ETH_DMABMR_DSL Descriptor skip length 0
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* ETH_DMABMR_EDFE Enhanced descriptor format enable Depends on CONFIG_STM32_ETH_ENHANCEDDESC
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* ETH_DMABMR_PBL Programmable burst length 32 beats
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* ETH_DMABMR_RTPR Rx Tx priority ratio 2:1
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* ETH_DMABMR_RTPR RX TX priority ratio 2:1
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* ETH_DMABMR_FB Fixed burst 1 (enabled)
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* ETH_DMABMR_RDP Rx DMA PBL 32 beats
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* ETH_DMABMR_RDP RX DMA PBL 32 beats
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* ETH_DMABMR_USP Use separate PBL 1 (enabled)
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* ETH_DMABMR_FPM 4xPBL mode 0 (disabled)
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* ETH_DMABMR_AAB Address-aligned beats 1 (enabled)
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@ -489,10 +492,13 @@ struct stm32_ethmac_s
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/* Used to track transmit and receive descriptors */
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struct eth_txdesc_s *txdesc; /* Next TX descriptor */
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struct eth_rxdesc_s *rxdesc; /* Next RX descriptor */
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struct eth_rxdesc_s *rxfirst; /* First RX descriptor of the segment */
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uint32_t segcount; /* Segment count */
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struct eth_txdesc_s *txhead; /* Next available TX descriptor */
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struct eth_rxdesc_s *rxhead; /* Next available RX descriptor */
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struct eth_txdesc_s *txtail; /* First "in_flight" TX descriptor */
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struct eth_rxdesc_s *rxcurr; /* First RX descriptor of the segment */
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uint16_t segments; /* RX segment count */
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uint16_t inflight; /* Number of TX transfers "in_flight" */
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sq_queue_t freeb; /* The free buffer list */
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/* Descriptor allocations */
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@ -530,9 +536,10 @@ static int stm32_uiptxpoll(struct uip_driver_s *dev);
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/* Interrupt handling */
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static void stm32_freesegment(FAR struct stm32_ethmac_s *priv,
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FAR struct eth_rxdesc_s *rxfirst, int nsegments);
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FAR struct eth_rxdesc_s *rxfirst, int segments);
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static int stm32_recvframe(FAR struct stm32_ethmac_s *priv);
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static void stm32_receive(FAR struct stm32_ethmac_s *priv);
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static void stm32_freeframe(FAR struct stm32_ethmac_s *priv);
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static void stm32_txdone(FAR struct stm32_ethmac_s *priv);
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static int stm32_interrupt(int irq, FAR void *context);
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@ -543,12 +550,12 @@ static void stm32_txtimeout(int argc, uint32_t arg, ...);
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/* NuttX callback functions */
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static int stm32_ifup(struct uip_driver_s *dev);
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static int stm32_ifdown(struct uip_driver_s *dev);
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static int stm32_txavail(struct uip_driver_s *dev);
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static int stm32_ifup(struct uip_driver_s *dev);
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static int stm32_ifdown(struct uip_driver_s *dev);
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static int stm32_txavail(struct uip_driver_s *dev);
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#ifdef CONFIG_NET_IGMP
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static int stm32_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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static int stm32_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
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#endif
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/* Descriptor Initialization */
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@ -558,17 +565,18 @@ static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv);
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/* PHY Initialization */
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static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value);
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static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value);
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static int stm32_phyinit(FAR struct stm32_ethmac_s *priv);
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static int stm32_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value);
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static int stm32_phywrite(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t value);
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static int stm32_phyinit(FAR struct stm32_ethmac_s *priv);
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/* MAC/DMA Initialization */
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static inline void stm32_ethgpioconfig(FAR struct stm32_ethmac_s *priv);
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static void stm32_ethreset(FAR struct stm32_ethmac_s *priv);
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static int stm32_macconfig(FAR struct stm32_ethmac_s *priv);
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static int stm32_macenable(FAR struct stm32_ethmac_s *priv);
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static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv);
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static int stm32_macconfig(FAR struct stm32_ethmac_s *priv);
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static void stm32_macaddress(FAR struct stm32_ethmac_s *priv);
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static int stm32_macenable(FAR struct stm32_ethmac_s *priv);
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static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv);
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/****************************************************************************
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* Private Functions
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@ -701,18 +709,149 @@ static inline bool stm32_isfreebuffer(FAR struct stm32_ethmac_s *priv)
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static int stm32_transmit(FAR struct stm32_ethmac_s *priv)
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{
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struct eth_txdesc_s *txdesc;
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uint32_t regval;
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/* The internal uIP buffer size may be configured to be larger than the
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* Ethernet buffer size.
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*/
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#if CONFIG_NET_BUFSIZE > CONFIG_STM32_ETH_BUFSIZE
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struct eth_txdesc_s *txnext;
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uint8_t *buffer;
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int bufcount;
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int lastsize;
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int i;
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#endif
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/* Verify that the hardware is ready to send another packet. If we get
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* here, then we are committed to sending a packet; Higher level logic
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* must have assured that there is no transmission in progress.
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*/
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/* Increment statistics */
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txdesc = priv->txhead;
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DEBUGASSERT(txdesc && (txdesc->tdes0 & ETH_TDES0_OWN) == 0);
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/* Send the packet: address=priv->dev.d_buf, length=priv->dev.d_len */
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/* Is the size to be sent greater than the size of the Ethernet buffer? */
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/* Enable Tx interrupts */
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#if CONFIG_NET_BUFSIZE > CONFIG_STM32_ETH_BUFSIZE
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if (priv->dev.d_len > CONFIG_STM32_ETH_BUFSIZE)
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{
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/* Yes... how many buffers will be need to send the packet? */
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bufcount = (priv->dev.d_len + (CONFIG_STM32_ETH_BUFSIZE-1)) / CONFIG_STM32_ETH_BUFSIZE;
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lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_STM32_ETH_BUFSIZE;
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/* Set the first segment bit in the first TX descriptor */
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txdesc->tdes0 |= ETH_TDES0_FS;
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/* Set up all but the last TX descriptor */
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txnext = txdesc;
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buffer = priv->dev.d_buf;
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for (i = 0; i < bufcount; i++)
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{
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/* This could be a normal event but the design does not handle it */
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DEBUGASSERT((txnext->tdes0 & ETH_TDES0_OWN) == 0);
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/* Set the Buffer1 address pointer */
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txdesc->tdes2 = (uint32_t)buffer;
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/* Set the buffer size in all TX descriptors, set the last segment
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* bit in the last TX descriptor
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*/
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if (i == (bufcount-1))
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{
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txnext->tdes0 |= ETH_TDES0_LS;
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txnext->tdes1 = lastsize;
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buffer += lastsize;
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}
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else
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{
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txnext->tdes1 = CONFIG_STM32_ETH_BUFSIZE;
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buffer += CONFIG_STM32_ETH_BUFSIZE;
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}
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/* Give descriptor back to DMA */
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txnext->tdes0 |= ETH_TDES0_OWN;
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txnext = (struct eth_txdesc_s *)txnext->tdes3;
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}
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/* Remember the start of the next available TX descriptor */
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txdesc = txnext;
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}
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else
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#endif
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{
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/* The single descriptor is both the first and last segment */
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txdesc->tdes0 |= (ETH_TDES0_FS | ETH_TDES0_LS);
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/* Set frame size */
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DEBUGASSERT(priv->dev.d_len <= CONFIG_NET_BUFSIZE);
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txdesc->tdes1 = priv->dev.d_len;
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/* Set the Buffer1 address pointer */
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txdesc->tdes2 = (uint32_t)priv->dev.d_buf;
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/* Set OWN bit of the TX descriptor tdes0. This gives the buffer to
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* Ethernet DMA
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*/
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txdesc->tdes0 |= ETH_TDES0_OWN;
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/* Point to the next available TX descriptor */
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txdesc = (struct eth_txdesc_s *)txdesc->tdes3;
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}
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/* Remember where we left off in the TX descriptor chain */
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priv->txhead = txdesc;
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/* Detach the buffer from priv->dev structure. That buffer is now
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* "in-flight".
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*/
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priv->dev.d_buf = NULL;
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/* If there is no other TX buffer, in flight, then remember this
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* as the location to check for TX done events.
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*/
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if (!priv->txtail)
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{
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DEBUGASSERT(priv->inflight == 0);
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priv->txtail = txdesc;
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}
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/* Increment the number of TX transfer in-flight */
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priv->inflight++;
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/* Check if the TX Buffer unavailable flag is set */
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if ((getreg32(STM32_ETH_DMASR) & ETH_DMAINT_TBUI) != 0)
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{
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/* Clear TX Buffer unavailable flag */
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putreg32(ETH_DMAINT_TBUI, STM32_ETH_DMASR);
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/* Resume DMA transmission */
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putreg32(0, STM32_ETH_DMATPDR);
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}
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/* Enable TX interrupts */
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regval = getreg32(STM32_ETH_DMAIER);
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regval |= ETH_DMAINT_XMIT_ENABLE;
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@ -758,12 +897,24 @@ static int stm32_uiptxpoll(struct uip_driver_s *dev)
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if (priv->dev.d_len > 0)
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{
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/* Send the packet */
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uip_arp_out(&priv->dev);
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stm32_transmit(priv);
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/* Check if there is room in the device to hold another packet. If not,
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* return a non-zero value to terminate the poll.
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/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We
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* cannot perform the TX poll if we are unable to accept another packet for
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* transmission.
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*/
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if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0)
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{
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/* There is room in the device to hold another packet. Return a non-
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* zero value to terminate the poll.
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*/
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return -EBUSY;
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}
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}
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/* If zero is returned, the polling will continue until all connections have
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@ -792,7 +943,7 @@ static int stm32_uiptxpoll(struct uip_driver_s *dev)
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****************************************************************************/
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static void stm32_freesegment(FAR struct stm32_ethmac_s *priv,
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FAR struct eth_rxdesc_s *rxfirst, int nsegments)
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FAR struct eth_rxdesc_s *rxfirst, int segments)
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{
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struct eth_rxdesc_s *rxdesc;
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int i;
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@ -800,7 +951,7 @@ static void stm32_freesegment(FAR struct stm32_ethmac_s *priv,
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/* Set OWN bit in RX descriptors. This gives the buffers back to DMA */
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rxdesc = rxfirst;
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for (i = 0; i < nsegments; i++)
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for (i = 0; i < segments; i++)
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{
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rxdesc->rdes0 = ETH_RDES0_OWN;
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rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3;
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@ -808,8 +959,8 @@ static void stm32_freesegment(FAR struct stm32_ethmac_s *priv,
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/* Reset the segment managment logic */
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priv->rxfirst = NULL;
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priv->segcount = 0;
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priv->rxcurr = NULL;
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priv->segments = 0;
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/* Check if the RX Buffer unavailable flag is set */
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@ -849,7 +1000,7 @@ static void stm32_freesegment(FAR struct stm32_ethmac_s *priv,
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static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
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{
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struct eth_rxdesc_s *rxdesc;
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struct eth_rxdesc_s *rxfirst;
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struct eth_rxdesc_s *rxcurr;
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uint8_t *buffer;
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int i;
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@ -865,7 +1016,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
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/* Scan descriptors owned by the CPU */
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rxdesc = priv->rxdesc;
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rxdesc = priv->rxhead;
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for (i = 0;
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(rxdesc->rdes0 & ETH_RDES0_OWN) == 0 && i < CONFIG_STM32_ETH_NRXDESC;
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i++)
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@ -875,8 +1026,8 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
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if ((rxdesc->rdes0 & ETH_RDES0_FS) != 0 &&
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(rxdesc->rdes0 & ETH_RDES0_LS) == 0)
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{
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priv->rxfirst = rxdesc;
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priv->segcount = 1;
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priv->rxcurr = rxdesc;
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priv->segments = 1;
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}
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/* Check if this is an intermediate segment in the frame */
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@ -884,24 +1035,24 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
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else if (((rxdesc->rdes0 & ETH_RDES0_LS) == 0)&&
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((rxdesc->rdes0 & ETH_RDES0_FS) == 0))
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{
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priv->segcount++;
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priv->segments++;
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}
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/* Otherwise, it is the last segment in the frame */
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else
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{
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priv->segcount++;
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priv->segments++;
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/* Check if the there is only one segment in the frame */
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if (priv->segcount == 1)
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if (priv->segments == 1)
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{
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rxfirst = rxdesc;
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rxcurr = rxdesc;
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}
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else
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{
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rxfirst = priv->rxfirst;
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rxcurr = priv->rxcurr;
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}
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/* Check if any errors are reported in the frame */
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@ -929,15 +1080,16 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
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* buffer.
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*/
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dev->d_buf = (uint8_t*)rxfirst->rdes2;
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rxfirst->rdes2 = (uint32_t)buffer;
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DEBUGASSERT(dev->d_buf == NULL);
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dev->d_buf = (uint8_t*)rxcurr->rdes2;
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rxcurr->rdes2 = (uint32_t)buffer;
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/* Return success, remebering where we should re-start scanning
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* and resetting the segment scanning logic
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*/
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priv->rxdesc = (struct eth_rxdesc_s*)rxdesc->rdes3;
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stm32_freesegment(priv, rxfirst, priv->segcount);
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priv->rxhead = (struct eth_rxdesc_s*)rxdesc->rdes3;
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stm32_freesegment(priv, rxcurr, priv->segments);
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return OK;
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}
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else
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@ -947,7 +1099,7 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
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*/
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nlldbg("DROPPED: RX descriptor errors: %08x\n", rxdesc->rdes0);
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stm32_freesegment(priv, rxfirst, priv->segcount);
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stm32_freesegment(priv, rxcurr, priv->segments);
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}
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}
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@ -956,11 +1108,11 @@ static int stm32_recvframe(FAR struct stm32_ethmac_s *priv)
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rxdesc = (struct eth_rxdesc_s*)rxdesc->rdes3;
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}
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||||
/* We get here after all of the descriptors have been scanned. Remember
|
||||
* where we left off.
|
||||
/* We get here after all of the descriptors have been scanned or when rxdesc points
|
||||
* to the first descriptor owned by the DMA. Remember where we left off.
|
||||
*/
|
||||
|
||||
priv->rxdesc = rxdesc;
|
||||
priv->rxhead = rxdesc;
|
||||
return -EAGAIN;
|
||||
}
|
||||
|
||||
@ -1003,9 +1155,9 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
|
||||
/* We only accept IP packets of the configured type and ARP packets */
|
||||
|
||||
#ifdef CONFIG_NET_IPv6
|
||||
if (BUF->type == HTONS(UIP_ETHTYPE_IP6))
|
||||
else if (BUF->type == HTONS(UIP_ETHTYPE_IP6))
|
||||
#else
|
||||
if (BUF->type == HTONS(UIP_ETHTYPE_IP))
|
||||
else if (BUF->type == HTONS(UIP_ETHTYPE_IP))
|
||||
#endif
|
||||
{
|
||||
uip_arp_ipin(&priv->dev);
|
||||
@ -1034,6 +1186,102 @@ static void stm32_receive(FAR struct stm32_ethmac_s *priv)
|
||||
stm32_transmit(priv);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
nlldbg("DROPPED: Unknown type: %04x\n", BUF->type);
|
||||
}
|
||||
|
||||
/* We are finished with the RX buffer. NOTE: If the buffer is
|
||||
* re-used for transmission, the dev->d_buf field will have been
|
||||
* nullified.
|
||||
*/
|
||||
|
||||
if (dev->d_buf)
|
||||
{
|
||||
/* Free the receive packet buffer */
|
||||
|
||||
stm32_freebuffer(priv, dev->d_buf);
|
||||
dev->d_buf = NULL;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_freeframe
|
||||
*
|
||||
* Description:
|
||||
* Scans the TX descriptors and frees the buffers of completed TX transfers.
|
||||
*
|
||||
* Parameters:
|
||||
* priv - Reference to the driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* None.
|
||||
*
|
||||
* Assumptions:
|
||||
* Global interrupts are disabled by interrupt handling logic.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void stm32_freeframe(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
struct eth_txdesc_s *txdesc;
|
||||
int i;
|
||||
|
||||
/* Scan for "in-flight" descriptors owned by the CPU */
|
||||
|
||||
txdesc = priv->txtail;
|
||||
if (txdesc)
|
||||
{
|
||||
DEBUGASSERT(priv->inflight > 0);
|
||||
|
||||
for (i = 0; (txdesc->tdes0 & ETH_TDES0_OWN) == 0; i++)
|
||||
{
|
||||
/* There should be a buffer assigned to all in-flight
|
||||
* TX descriptors.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(txdesc->tdes2 != 0);
|
||||
|
||||
/* Check if this is the first segment of a TX frame. */
|
||||
|
||||
if ((txdesc->tdes0 & ETH_TDES0_FS) != 0)
|
||||
{
|
||||
/* Yes.. Free the buffer */
|
||||
|
||||
stm32_freebuffer(priv, (uint8_t*)txdesc->tdes2);
|
||||
}
|
||||
|
||||
/* In any event, make sure that TDES2 is nullified. */
|
||||
|
||||
txdesc->tdes2 = 0;
|
||||
|
||||
/* Check if this is the last segement of a TX frame */
|
||||
|
||||
if ((txdesc->tdes0 & ETH_TDES0_FS) != 0)
|
||||
{
|
||||
/* Yes.. Decrement the number of frames "in-flight".
|
||||
* If there are no more frames in-flight, then bail.
|
||||
*/
|
||||
|
||||
if (--priv->inflight <= 0)
|
||||
{
|
||||
priv->txtail = NULL;
|
||||
priv->inflight = 0;
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* Try the next descriptor in the TX chain */
|
||||
|
||||
txdesc = (struct eth_txdesc_s*)txdesc->tdes3;
|
||||
}
|
||||
|
||||
/* We get here if (1) there are still frames "in-flight". Remember
|
||||
* where we left off.
|
||||
*/
|
||||
|
||||
priv->txtail = txdesc;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1058,17 +1306,24 @@ static void stm32_txdone(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Check for errors and update statistics */
|
||||
DEBUGASSERT(priv->txtail != NULL);
|
||||
|
||||
/* Scan the TX desciptor change, returning buffers to free list */
|
||||
|
||||
stm32_freeframe(priv);
|
||||
|
||||
/* If no further xmits are pending, then cancel the TX timeout */
|
||||
|
||||
wd_cancel(priv->txtimeout);
|
||||
if (priv->inflight <= 0)
|
||||
{
|
||||
wd_cancel(priv->txtimeout);
|
||||
|
||||
/* And disable further Tx interrupts. */
|
||||
/* And disable further TX interrupts. */
|
||||
|
||||
regval = getreg32(STM32_ETH_DMAIER);
|
||||
regval &= ~ETH_DMAINT_XMIT_DISABLE;
|
||||
putreg32(regval, STM32_ETH_DMAIER);
|
||||
regval = getreg32(STM32_ETH_DMAIER);
|
||||
regval &= ~ETH_DMAINT_XMIT_DISABLE;
|
||||
putreg32(regval, STM32_ETH_DMAIER);
|
||||
}
|
||||
|
||||
/* Then poll uIP for new XMIT data */
|
||||
|
||||
@ -1127,7 +1382,7 @@ static int stm32_interrupt(int irq, FAR void *context)
|
||||
}
|
||||
|
||||
/* Check if a packet transmission just completed. If so, call
|
||||
* stm32_txdone(). This may disable further Tx interrupts if there
|
||||
* stm32_txdone(). This may disable further TX interrupts if there
|
||||
* are no pending tansmissions.
|
||||
*/
|
||||
|
||||
@ -1194,9 +1449,12 @@ static void stm32_txtimeout(int argc, uint32_t arg, ...)
|
||||
{
|
||||
FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg;
|
||||
|
||||
/* Increment statistics and dump debug info */
|
||||
/* Then reset the hardware. Just take the interface down, then back
|
||||
* up again.
|
||||
*/
|
||||
|
||||
/* Then reset the hardware */
|
||||
stm32_ifdown(&priv->dev);
|
||||
stm32_ifup(&priv->dev);
|
||||
|
||||
/* Then poll uIP for new XMIT data */
|
||||
|
||||
@ -1225,16 +1483,20 @@ static void stm32_polltimer(int argc, uint32_t arg, ...)
|
||||
{
|
||||
FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)arg;
|
||||
|
||||
/* Check if there is room in the send another TX packet. We cannot perform
|
||||
* the TX poll if he are unable to accept another packet for transmission.
|
||||
/* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We
|
||||
* cannot perform the TX poll if we are unable to accept another packet for
|
||||
* transmission.
|
||||
*/
|
||||
|
||||
/* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
|
||||
* might be bug here. Does this mean if there is a transmit in progress,
|
||||
* we will missing TCP time state updates?
|
||||
*/
|
||||
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0)
|
||||
{
|
||||
/* If so, update TCP timing states and poll uIP for new XMIT data. Hmmm..
|
||||
* might be bug here. Does this mean if there is a transmit in progress,
|
||||
* we will missing TCP time state updates?
|
||||
*/
|
||||
|
||||
(void)uip_timer(&priv->dev, stm32_uiptxpoll, STM32_POLLHSEC);
|
||||
(void)uip_timer(&priv->dev, stm32_uiptxpoll, STM32_POLLHSEC);
|
||||
}
|
||||
|
||||
/* Setup the watchdog poll timer again */
|
||||
|
||||
@ -1365,11 +1627,18 @@ static int stm32_txavail(struct uip_driver_s *dev)
|
||||
|
||||
if (priv->ifup)
|
||||
{
|
||||
/* Check if there is room in the hardware to hold another outgoing packet. */
|
||||
/* Check if the next TX descriptor is owned by the Ethernet DMA or
|
||||
* CPU. We cannot perform the TX poll if we are unable to accept
|
||||
* another packet for
|
||||
* transmission.
|
||||
*/
|
||||
|
||||
/* If so, then poll uIP for new XMIT data */
|
||||
if ((priv->txhead->tdes0 & ETH_TDES0_OWN) == 0)
|
||||
{
|
||||
/* If we have the descriptor, then poll uIP for new XMIT data */
|
||||
|
||||
(void)uip_poll(&priv->dev, stm32_uiptxpoll);
|
||||
(void)uip_poll(&priv->dev, stm32_uiptxpoll);
|
||||
}
|
||||
}
|
||||
|
||||
irqrestore(flags);
|
||||
@ -1400,6 +1669,7 @@ static int stm32_addmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
|
||||
FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)dev->d_private;
|
||||
|
||||
/* Add the MAC address to the hardware multicast routing table */
|
||||
#error "Missing logic"
|
||||
|
||||
return OK;
|
||||
}
|
||||
@ -1429,6 +1699,7 @@ static int stm32_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
|
||||
FAR struct stm32_ethmac_s *priv = (FAR struct stm32_ethmac_s *)dev->d_private;
|
||||
|
||||
/* Add the MAC address to the hardware multicast routing table */
|
||||
#error "Missing logic"
|
||||
|
||||
return OK;
|
||||
}
|
||||
@ -1455,9 +1726,19 @@ static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv)
|
||||
struct eth_txdesc_s *txdesc;
|
||||
int i;
|
||||
|
||||
/* Set the priv->txdesc pointer with the first descriptor in the table */
|
||||
/* priv->txhead will point to the first, available TX descriptor in the chain.
|
||||
* Set the priv->txhead pointer to the first descriptor in the table.
|
||||
*/
|
||||
|
||||
priv->txdesc = priv->txtable;
|
||||
priv->txhead = priv->txtable;
|
||||
|
||||
/* priv->txtail will point to the first segment of the oldest pending
|
||||
* "in-flight" TX transfer. NULL means that there are no active TX
|
||||
* transfers.
|
||||
*/
|
||||
|
||||
priv->txtail = NULL;
|
||||
priv->inflight = 0;
|
||||
|
||||
/* Initialize each TX descriptor */
|
||||
|
||||
@ -1470,7 +1751,7 @@ static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv)
|
||||
txdesc->tdes0 = ETH_TDES0_TCH;
|
||||
|
||||
#ifdef CHECKSUM_BY_HARDWARE
|
||||
/* Enable the checksum insertion for the Tx frames */
|
||||
/* Enable the checksum insertion for the TX frames */
|
||||
|
||||
txdesc->tdes0 |= ETH_TDES0_CIC_ALL;
|
||||
#endif
|
||||
@ -1479,7 +1760,7 @@ static void stm32_txdescinit(FAR struct stm32_ethmac_s *priv)
|
||||
* are used)
|
||||
*/
|
||||
|
||||
txdesc->tdes2 = 0;;
|
||||
txdesc->tdes2 = 0;
|
||||
|
||||
/* Initialize the next descriptor with the Next Descriptor Polling Enable */
|
||||
|
||||
@ -1527,9 +1808,18 @@ static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv)
|
||||
struct eth_rxdesc_s *rxdesc;
|
||||
int i;
|
||||
|
||||
/* Set the priv->rxdesc pointer with the first one of the table list */
|
||||
/* priv->rxhead will point to the first, RX descriptor in the chain.
|
||||
* This will be where we receive the first incomplete frame.
|
||||
*/
|
||||
|
||||
priv->rxdesc = priv->rxtable;
|
||||
priv->rxhead = priv->rxtable;
|
||||
|
||||
/* If we accumulate the frame in segments, priv->rxcurr points to the
|
||||
* RX descriptor of the first segment in the current TX frame.
|
||||
*/
|
||||
|
||||
priv->rxcurr = NULL;
|
||||
priv->segments = 0;
|
||||
|
||||
/* Initialize each TX descriptor */
|
||||
|
||||
@ -1537,7 +1827,7 @@ static void stm32_rxdescinit(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
rxdesc = &priv->rxtable[i];
|
||||
|
||||
/* Set Own bit of the Rx descriptor rdes0 */
|
||||
/* Set Own bit of the RX descriptor rdes0 */
|
||||
|
||||
rxdesc->rdes0 = ETH_RDES0_OWN;
|
||||
|
||||
@ -2079,6 +2369,41 @@ static int stm32_macconfig(FAR struct stm32_ethmac_s *priv)
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_macaddress
|
||||
*
|
||||
* Description:
|
||||
* Configure the selected MAC address.
|
||||
*
|
||||
* Parameters:
|
||||
* priv - A reference to the private driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void stm32_macaddress(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the MAC address high register */
|
||||
|
||||
regval = ((uint32_t)priv->dev.d_mac.ether_addr_octet[5] << 8) |
|
||||
(uint32_t)priv->dev.d_mac.ether_addr_octet[4];
|
||||
putreg32(regval, STM32_ETH_MACA0HR);
|
||||
|
||||
/* Set the MAC address low register */
|
||||
|
||||
regval = ((uint32_t)priv->dev.d_mac.ether_addr_octet[3] << 24) |
|
||||
((uint32_t)priv->dev.d_mac.ether_addr_octet[2] << 16) |
|
||||
((uint32_t)priv->dev.d_mac.ether_addr_octet[1] << 8) |
|
||||
(uint32_t)priv->dev.d_mac.ether_addr_octet[0];
|
||||
putreg32(regval, STM32_ETH_MACA0LR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_macenable
|
||||
*
|
||||
@ -2099,6 +2424,10 @@ static int stm32_macenable(FAR struct stm32_ethmac_s *priv)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the MAC address */
|
||||
|
||||
stm32_macaddress(priv);
|
||||
|
||||
/* Enable transmit state machine of the MAC for transmission on the MII */
|
||||
|
||||
regval = getreg32(STM32_ETH_MACCR);
|
||||
@ -2203,11 +2532,11 @@ static int stm32_ethconfig(FAR struct stm32_ethmac_s *priv)
|
||||
|
||||
stm32_initbuffer(priv);
|
||||
|
||||
/* Initialize Tx Descriptors list: Chain Mode */
|
||||
/* Initialize TX Descriptors list: Chain Mode */
|
||||
|
||||
stm32_txdescinit(priv);
|
||||
|
||||
/* Initialize Rx Descriptors list: Chain Mode */
|
||||
/* Initialize RX Descriptors list: Chain Mode */
|
||||
|
||||
stm32_rxdescinit(priv);
|
||||
|
||||
|
||||
@ -419,4 +419,12 @@ Where <subdir> is one of the following:
|
||||
examples/ostest. By default, this project assumes that you are
|
||||
using the DFU bootloader.
|
||||
|
||||
CONFIG_STM32_BUILDROOT=y : CodeSourcery under Windows
|
||||
CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows
|
||||
|
||||
nsh:
|
||||
---
|
||||
Configures the NuttShell (nsh) located at apps/examples/nsh. The
|
||||
Configuration enables both the serial and telnet NSH interfaces.
|
||||
|
||||
CONFIG_STM32_CODESOURCERYW=y : CodeSourcery under Windows
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user